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Original question:

TMS320F28379D: CLBCLKCTL register doubt

TMS320F28388D: CLB clock

Jordan Zhou
Genius 9770 points
Part Number: TMS320F28388D
Other Parts Discussed in Thread: C2000WARE

Hi,

Some doubts about CLB clock:

1) CLB max clock is 100MHz, so CLBCLKDIV should be 2 or larger values

2) TILECLKDIV, what's the max frequency? Can TILE clock be lower than CLB clock?

Do we have a detaild doc?

Br, Jordan

  • 0
    TI__Expert 3720 points

    Hi,

    Yes you are correct that there are 2 dividers that scales the "source" to CLB CLK. The first divider can provide a division upto 8 while the second one (tile clock divider) can provide a division upto 2. The details of the API and the parameters to configure it are available as part of F2838x Driverlib API User guide (inside C2000Ware) as shown below :

    If my reply answers your question please click on "This resolved my issue" button located at the bottom of my post.

    Regards

    Himanshu

  • 0 in reply to Himanshu Chaudhary60
    TI__Genius 9770 points

    Himanshu,

    CLBCLKDIV is the divider from system clock (200MHz). 

    What about TILECLKDIV? Is it from system clock or CLB clock?

    Br, Jordan

  • 0 in reply to Jordan Zhou
    TI__Expert 3720 points

    Jordan,

    TILECLK is the divider from the CLB clock so yes it is possible that TILE clock to be lower than CLB Register clock.

    If my reply answers your question please click on "This resolved my issue" button located at the bottom of my post.

    Regards

    Himanshu