UCC28782EVM-030: UCC28782 document SLUAAF9

Hello Robin, 

We are not in a position to accept customer boards and debug them.  We try to help customers do their own debugging by providing advice based on the extent of the information provided to us by the customer.  More information is better, and hard numbers are preferable over qualitative descriptions, where possible.  Especially well-identified waveforms with the complete operating conditions under which they were acquired.  (Much of this reply may be obvious to you, but is for the benefit of other readers of this forum.)
Also, refer to my reply to your parallel thread, about re-entering all of the design and component changes you have made into the Excel calculator tool to obtain the updated control parameters and values need to accommodate the revisions.  In ACF, it seems like everything interacts with everything else, so you can't make one change without also changing something else to compensate, or operation will deteriorate.  

Based on the scenario above, your debug procedure would be to slowly bring up the board as if it were a new design and check each stage to verify that the signals look like they are supposed to look like at that stage.  When something doesn't look as expected, then investigate until the cause is found and corrected and the signals do look right.  Proceed further until the next abnormal thing is encountered, then debug that.  Inspect the board for solder shorts, opens, reversed polarity, etc first before applying power.  

I start by applying 5Vac (using programmable ac source) and verifying that there is about 7V on the bulk caps. If not, find out why and fix.  If okay, its not enough to charge VDD, so raise up to 10Vac.  VDD should start to charge up through the depl-Fet, but may not make it to 17Vdc.  If it's not rising, debug.  If okay, raise to 20Vac.  Now, VDD should make it to 17.5V to start the IC and it should try to drive the low-side Fet through PWML.  But there is not enough Vbulk to meet the criterion on CS to reach 0.2V within 2us, so there should be only a single pulse (thinking there is a shorted CS to GND), then the IC should wait 1.5 seconds (while VDD cycles) before trying another PWML pulse. If okay, then raise Vac a little further.  Eventually, you should see 3 pulses.  Etc... Etc...  Bring up the board a little at a time.

You need to be able to probe PWML and PWMH signals themselves somewhere because you can't rely on the Fets to tell you if the signals are active or not, if the Fets or their drivers are dead.  And you can't get pulses out of the transformer or the Fets if the IC is not pulsing. The high-side driver bootstrap VDD can be checked by probing from primary GND and comparing to the switching node voltage while VAC is still relatively low, like at 50Vac or so.  A 10-15V difference from HB to HS should be discernable on a 20V/div scale to prove that the bootstrap works even though the high side may not be driven yet.   

If there are additional circuits that are not directly related to the ACF conversion, such as downstream converters or USB controllers, etc, it may be prudent to disable or bypass them to focus on getting the main ACF plant to work properly.  Once that is working nominally to full power under normal conditions, and all stresses are verified to be within ratings, one of the other circuits can be introduced to assess its functionality and its affect on the ACF stage.  Introduce one change at a time, and verify that nothing bad is happening somewhere at all corners of normal operation. Debug any problems before adding another change.  Eventually you'll get the whole system running as expected with stresses and temperature rises as expected. 

If one board is so far damaged that you're replacing almost everything, I suggest to abandon it and start with a fresh board from the beginning as described above.  That way, if there are an issue introduced by the board design itself, such as a short circuit or noise coupling, it may be caught earlier in the bring-up before it can escalate to wide-spread damage.  The pcb always has the possibility of having parasitics and issues not modeled by a perfectly working schematic diagram.  And a heavily-reworked board may have some undetected damage to tracks or pads and cause frustrating repeats of failures for what seems like no apparent reason.  

You mention that you have 2 other working assemblies.  I suggest to take one and bring it up as if it was the very first prototype, to assess all of the stresses on all of the components at each stage of operation.  You can head-off a trend of unexpected increasing stress.  Meanwhile, build up a fourth  board to replace the first one (with all the failures). When all three are running normally as expected, you can gradually introduce any required abnormal conditions and assess their performance.  Once they all pass, you can increase a pilot run with high confidence.  

Regards,
Ulrich

ok, thnx much. will try to continue as you describe.

Hello Ulrich:

Infinitely grateful for your precious corrective actions.  Everything you suggested/noted/remarked is consistent with the goals: so we updated the Spreadsheet as you noted & now everything seems to fall in place!

Lm is entirely under our control, using the suggested value is not a penalty. 

I think if it appeared to us Rcs was limiting peak current, it would seem for other reasons - you point them out - so we can use .22 / SMD 2512 which we have.

Cannot get ISO7310 yet, but have IPL510.( from NVE Spin electronics folks)..darned thing has a different pinout, but can manage for this series.

An update: we found we cannot use really any MOSFET for SR at this time( requires a heat sink we did not plan for)- gets to 80 deg C with 68W OUTPUT - so we are going back to EPC2034 WITH A DRAMATIC CHANGE IN ASSEMBLY PROCESS. 

 EPC2034C will get to 48 deg C within the same constraints!

Another uplifting info: we succeeded in making a DIY Litz wire much better version. Temp rise was back to 64 deg C inside the core.

This surely cannot be made in "planar " version. This is also not a problem- we can stay with a wired version. 

The dramatic change is that we are installing a DIY video setup to look at the part for alignment & another for vision during the vacuum release event.

We have a very simple pick-place system (from Canada).

And we are going to get the first batch through the x-ray to make sure  EPC is well soldered & the others as a bonus . Scheduled for next Thursday.

Goal will be to use updated BOM, updated litz-wire xmfr, and much-enhanced assembly: then GO!

Thnx again.

r