HD3SS3220: Only one side of usb is able to work properly at 10Gbps speed

Hi Huang,

Huang Bang said:

1. Is coupling capacitance required between TUSB1002RGER and HD3SS3220IRNHR? Or direct DC coupling?

There are a few ways to handle AC coupling with the 1002A and the 3220. You can AC couple the TX and RX lines between the 1002A and 3220 and it would be ok. Alternatively, you can AC couple the TX and RX lines between the 3220 and the USB connector. I drew an example diagram for the first implementation.

In your schematic I cannot tell what the capacitor values are, but I see you have the TX lines AC coupled on both sides of the 3220.

Can you share what values these capacitors are? You need to keep the total capacitance on the TX lines above 75nF, so it is possible these capacitors will violate that spec.

Huang Bang said:

2. Do the RX1 and RX2 of the HD3SS3220IRNHR require coupling capacitors?

Capacitors are not required for the RX lines. If you do include capacitors, use 330nF as their value.

Huang Bang said:

3. Do I need to ensure that the VDD5 pin voltage remains stable for 2 ms before the VCC33 pin rises? VCC33 We use slow rise instead of delayed rise. Is slow rise feasible?

Yes, you need to be sure VDD5 is stable for 2ms before VCC33 because you have ENn_CC tied to ground. Here is the signal diagram in the datasheet:

Slow rise should be ok as long as you follow the timing in the datasheet (VCC33 hits 0.4V 2ms after VDD5 hits 3.3V)

Huang Bang said:

4. The VBUS_DET pin of HD3SS3220IRNHR is connected with 5V voltage, do I need to control the timing of VBUS? It is now out of control.

You do not need to control the VBUS as you are operating as a UFP. If you were a DFP, then you would need to control VBUS timing.

Huang Bang said:

5. We did not use 3.3V voltage, but 3.0V. Does this have an impact?

The 3.3V supply on the 3220 can accept 3V so this shouldn't be an issue.

Best,

Shane

Hi Shane,

The capacitance value of both sides of the TX line of the HD3SS3220IRNHR is 220nf, which has been marked in the following figure.

The capacitance 224 of the schematic indicates that 22*10^4=220000pf=220nf
The capacitance 104 of the schematic indicates that 10*10^4=100000pf=100nf

According to your reply, we will optimize the timing of starting voltage 3v and 5v and then do the test. Thank you for your answer.

Hi Huang,

Let me know if you see the same issue after testing.

Best,

Shane

Hi Shane,

I have tried to optimize the startup timing of 5v and 3v, and now the delay is 3.6ms, but the problem has not been solved。is there anything else to pay attention to?

Today I also found some problems, different pc motherboards have different test results，I'm sure I plugged in a usb(10Gbps) port。

The above test has a compatibility problem, what is the general cause of this problem?

Hi Huang,

The orientation of your type-C cable is communicated through the CC1/CC2 lines. If the voltage rail timing is correct and you still can't detect the connected host in one orientation, then I suspect there is an issue with the CC negotiation. Can you show the signal on CC1 and CC2 when the host is attached?

As a follow up question, are you trying to transmit video data over the USB-C connection? If this is the case, you would likely need an alt-mode re-driver/MUX like the TUSB1064.

Best,

Shane

Hi Shane,

The following is the table I made after testing: cc1/cc2/dir corresponds to the pin voltage of HD3SS3220 after the host is attached.

How to see usb-c negotiation is successful? Observing the voltage of cc1 and cc2 seems to be fine.Take the PRIME Z790-P motherboard as an example,  it can recognize usb3.1(10Gbps), but when dir is low, it does not work properly and cannot consistently output usb signals.

The following is a brief product block diagram. Compared with TUSB1002RGER, is it better to use TUSB1064 in signal performance? I think it has more DP ports, while my product does not need dp ports.

Thanks

Huang

Hi Huang,

Huang Bang said:

Compared with TUSB1002RGER, is it better to use TUSB1064 in signal performance? I think it has more DP ports, while my product does not need dp ports.

How are you passing video through the Type-C connector? This is typically done using DisplayPort alt-mode.

From the table you've provided, the orientation seems to be negotiated correctly (DIR goes high in one orientation and low in the other). The issue I see is that you are passing video through the HD3SS3220, which is a MUX not intended for transmitting video over Type-C interfaces. This could be why the intel boards do not pass video at all.

You would need a PD controller to negotiate DP alt mode over the CC1/2 lines. The CC controller integrated within the 3220 cannot negotiate alternate modes. Furthermore, the 3220 is not equipped to handle the pin assignment MUXing that DP alt mode requires. You would need a DP alt mode MUX like the TUSB1064 to MUX the data and SBU lanes correctly. 

I see from your diagram that your video sink uses HDMI. Are you trying to pass HDMI signals through the type-C interface? In addition, how do you handle the SBU/AUX MUXing for the flip orientation?

Best,

Shane

Hi Shane,

   -> How are you passing video through the Type-C connector? This is typically done using DisplayPort alt-mode.

video and audio data will enter the fpga chip, a usb ip core inside the fpga chip, audio and video signals are through the usb ip core led rx, tx differential pins and usb type-c interface to interact.

video uses the uvc protocol for transferring video under the usb protocol.

audio uses the uac protocol for transmitting audio under the usb protocol.

uvc and uac are two protocols under the USB specification protocol Device class specification.

   -> From the table you've provided, the orientation seems to be negotiated correctly (DIR goes high in one orientation and low in the other). The issue I see is that you are passing video through the HD3SS3220, which is a MUX not intended for transmitting video over Type-C interfaces. This could be why the intel boards do not pass video at all.

We used intel's fpga development board to verify the feasibility when making the product. The circuit schematic diagram of the development board and test execl table are attached below. intel's fpga development board also uses HD3SS3220+TUSB1002RGER. If the motherboard of the pc is intel NUC11PABi5, both sides of the development board can output 4K60 frames of video data. The only drawback is that, If the pc's motherboard is ASUS PRIME Z790-P, there is a problem that only one side will work. We have also tested a lot of computer motherboards, in order to reduce the complexity of your data, the execl table only lists two, so far only found ASUS PRIME Z790-P usb only one side of the problem. It is also not ruled out that the ASUS PRIME Z790-P pc motherboard is faulty.

In addition to whether the front and back of usb can work, another problem is compatibility. Different pc motherboards or using different usb cables have different results. The company's homemade board cannot recognize usb3.1 (10Gbps) on intel NUC11PABi5, while the intel development board can recognize and output 4K60 frames of video through the usb port. The scheme I used for the circuit board was similar to that of the development board. we did not do usb signal integrity test on the pcb. I suspect that something is wrong here. The pcb may not be designed well. Does TI have relevant usb (10Gbps) signal integrity detection service?

ps：The problem mainly occurs when usb is running at 10Gbps, 5Gbps has no problems.

TI test.xlsx

3554.intel fpga development board schematic diagram.pdf

Thanks

Huang

Hi Huang,

Thank you for clarifying. We usually see DP alt mode used for video over type-C connectors, not UVC, so I assumed that is what you intended.

At 10G the insertion loss in the PCB trace would be higher then at 5G. There is a possibility your trace is too long for the 10G signal. I have a couple questions to estimate the trace loss in your PCB

1. What material do you use for your PCB trace?

2. What length is the trace of the Superspeed signal?

If the signal is passing at 5G but not at 10G there may be a layout issue that the schematic wouldn't show. Are you able to share the layout for this design? You can direct message me the layout file by sending me a friend request on E2E. This could be helpful if you do not want your file shared on the public forum

Best,

Shane

Hi Shane,

  ->  1. What material do you use for your PCB trace?

Isn't the material of pcb wiring all copper?  Is there any other material?  

  ->  2. What length is the trace of the Superspeed signal?

In the execl table of the attachment, I have counted the length of each cable of the intel development board and self-made board. The x and y columns show the total length value.

By analyzing the execl table data, I find that intel's development board is better than the company's board in terms of line isometric design. Is this the cause of the problem?

4747.TI test.xlsx

I haven't got the company's permission to send the layout design file for the time being.

Thanks

Huang

Hi Huang,

Huang Bang said:

Isn't the material of pcb wiring all copper?  Is there any other material?  

PCBs can use different trace materials that will have an affect on the loss in the trace. The standard material is typically FR4, however there are also low-loss options like Megtron. Your board trace length is relatively small (around 3in) so I don't believe the board insertion loss would be a concern with the TUSB1002 to help compensate. Have you tried different EQ values on the 1002 to see if the signal will pass at 10G?

Huang Bang said:

I find that intel's development board is better than the company's board in terms of line isometric design. Is this the cause of the problem?

At 10G this may be the case. I recommend matching the trace lengths to within 10mil if possible.

Since you cannot share the layout file, I have a few recommendations to minimize signal reflections in the high-speed trace.

1. Make sure the capacitors you are using on the trace are size 0201. This would keep them similar in size to the trace.

2. Minimize the number of vias in the high speed trace. We typically recommend keeping a two via maximum on a 10G trace.

3. Keep a solid ground plane under the high speed trace, and between differential pairs when possible. 

Best,

Shane

Hi Shane, 

   ->   PCBs can use different trace materials that will have an affect on the loss in the trace. The standard material is typically FR4, however there are also low-loss options like Megtron. 

Thanks to popular science, we have learned some knowledge. The material we use is FR4, and we will try to use Megtron for the next version of PCB.

   ->   Your board trace length is relatively small (around 3in) so I don't believe the board insertion loss would be a concern with the TUSB1002 to help compensate. Have you tried different EQ values on the 1002 to see if the signal will pass at 10G?

I did not try different EQ values in 1002, do I need to try all 16 EQ values? It is a bit too much, I need some time to complete it.

   ->   At 10G this may be the case. I recommend matching the trace lengths to within 10mil if possible.

We will control the length within 10mil for the next version of PCB.

   ->   1. Make sure the capacitors you are using on the trace are size 0201. This would keep them similar in size to the trace.

The current capacitor size is 0402, and we will modify it to 0201 for the next version of PCB.

   ->  2. Minimize the number of vias in the high speed trace. We typically recommend keeping a two via maximum on a 10G trace.

The USB link in the PCB board just has 2 vias, can it be understood that it is better not to have vias? The PCB currently uses an 8-layer board. If there are vias, is the signal quality related to the number of layers of vias?

The layout file has been sent. Please take a look when you have time. Thank you very much.

Thanks,

Huang 

Hi Shane,

As for the problem that only one side of usb can work normally, I carefully observed the layout file of the intel development board, and found that the differential bus on one side of usb passes through two vias, and the other side passes through four vias, which will cause insertion loss, which may be the source of the inconsistency between positive and negative insertion.When I set the EQ SETTING to 11, the phenomenon that only one side of the intel development board can work normally disappeared. Now both sides of the usb can work normally, and the EQ value adjustment is effective.

Through the layout review file you sent me, I found that the company's pcb has many problems in differential high-speed wiring. We will make modifications in the next version according to your suggestion. Thank you for your reply during this time.

Thanks,

Huang 

Hi Shane,

I still have some pcb wiring problems, do I need to open a single post for similar pcb problems? Because I noticed that the questions I was asking were drifting away from the title.

What is the appropriate trace width and trace spacing design for the differential bus?
The TUSB1002A document refers to a trace width of 4mil, the trace spacing is not found, and the distance from other high-speed differential buses is 3 times the trace width;
The HD3SS3220 document reference trace width is 6mil, trace spacing is 8mil, and the distance from other high-speed differential buses is 5 times the trace width;
The smaller the trace width and the smaller the trace spacing, will the signal attenuation and distortion of the differential signal in the transmission process be smaller? If so, I will use 4mil as the trace width and trace spacing, and the production cost will increase significantly only when the trace width or trace spacing is lower than 4mil.

Thanks,

Huang 

Hi Huang,

Huang Bang said:

I still have some pcb wiring problems, do I need to open a single post for similar pcb problems? Because I noticed that the questions I was asking were drifting away from the title.

Its ok to ask any questions related to your issue in this thread. If you do create a new thread, please link this thread for context on the design.

Huang Bang said:

The smaller the trace width and the smaller the trace spacing, will the signal attenuation and distortion of the differential signal in the transmission process be smaller?

It is actually the opposite. A smaller trace width will increase the insertion loss because there is less cross-sectional area for the signal to pass through. The trace width and spacing will contribute to the differential impedance of your high speed pair. For USB3 signals, you want to target a 90ohm differential impedance.

Best,

Shane