Other Parts Discussed in Thread: DXP, TEST2
Dear experts,
I'm trying to use TDA4VM to output DSI super frame to the UB948 screen for display. (Screen resolution is 1920*720@60Fps)
The background is:
1.TDA4VM output super frame: 1920*720@60Fps.
2.UB941 works in Left/Right 3D Splitter mode.
3.Only FPD Link port0 is connected with UB948, port1 is not connected to any device because there is only one screen.
The current update is:
1.The Screen(UB948) can display the color bar image output by UB941 which configured with internal clock and timing in Pattern mode.
2.The Screen can't display anything when UB941 is configured to use external timing. And the value read from the indirect register DSI_VC_DTYPE(0x2A) of UB941 is 0x00.
This phenomenon seems to be consistent with the example in section 4.2 of the DS90UB941AS-Q1 DSI Bringup Guide.pdf
The question is ：
1.How can I configure TDA4 DSS to "enter Low Power Mode at least once per frame during one of the available BLLP periods" ?
2. Is there any problem If I only connect the fisrt port of FPD Link when UB941 is in splitter mode?
More information is shown below：
1. Configuration of UB941:
uint8_t Ub941Config[][3] = {
/*
* CMS Display
* 1920*720*2@60Fps
* HSW = 16 * 2
* HFP = 72 * 2
* HBP = 72 * 2
* VSW = 2
* VFP = 19
* VBP = 19
* PCLK= 95 * 2
*/
{0x1a, 0x01, 0x08}, // Disable the DSI inputs
{0x1a, 0x06, 0x00}, // Read Deserializer ID
{0x1a, 0x1E, 0x01}, // Select FPD-Link Port 0
{0x1a, 0x03, 0x9A}, // Enable Pass-Through, Enable CRC Cheker, Enable Filter, Enable auto-switch
{0x32, 0x20, 0x99}, // Set 948 to lighte screen
{0x32, 0x21, 0x09}, // Set 948
{0x1a, 0x1E, 0x01}, // Select FPD Link port 0
{0x1a, 0x4F, 0x8C}, // Set Continuous DSI clock mode, Single-DSI mode, DSI Input port 0, 4Lanes
{0x1a, 0x5B, 0x07}, // Select Force Splitter mode
{0x1a, 0x56, 0x80}, // Enable Left/Right 3D processing, Select DSI Reference Clock Mode
{0x1a, 0x32, 0x80}, // Set the line size to 1920(LSB)
{0x1a, 0x33, 0x07}, // Set the line size to 1920(MSB)
// Crop Port0 1920*720 image
{0x1a, 0x1E, 0x01}, // Select FPD-Link Port 0
{0x1a, 0x36, 0x00}, // Set crop start X position to 0(bit[0:7])
{0x1a, 0x37, 0x80}, // Set crop start X position to 0(bit[8:12]) and enable cropping
{0x1a, 0x38, 0x7F}, // Set crop stop X position to 1919 (LSB)
{0x1a, 0x39, 0x07}, // Set crop stop X position to 1919 (MSB)
{0x1a, 0x3A, 0x00}, // Set crop start Y position to 0 (LSB)
{0x1a, 0x3B, 0x00}, // Set crop start Y position to 0 (MSB)
{0x1a, 0x3C, 0xCF}, // Set crop stop Y position to 719 (LSB)
{0x1a, 0x3D, 0x02}, // Set crop stop Y position to 719 (MSB)
// Crop Port1 1920*720 image
{0x1a, 0x1E, 0x02}, // Select FPD-Link Port 1
{0x1a, 0x36, 0x00}, // Set crop start X position to 0(bit[0:7])
{0x1a, 0x37, 0x80}, // Set crop start X position to 0(bit[8:12]) and enable cropping
{0x1a, 0x38, 0x7F}, // Set crop stop X position to 1919 (LSB)
{0x1a, 0x39, 0x07}, // Set crop stop X position to 1919 (MSB)
{0x1a, 0x3A, 0x00}, // Set crop start Y position to 0 (LSB)
{0x1a, 0x3B, 0x00}, // Set crop start Y position to 0 (MSB)
{0x1a, 0x3C, 0xCF}, // Set crop stop Y position to 719 (LSB)
{0x1a, 0x3D, 0x02}, // Set crop stop Y position to 719 (MSB)
// Program TSKIP_CNT DSI parameter on DSI Port0
{0x1a, 0x40, 0x04}, // Select Indirect register access to DIS Port 0 registers
{0x1a, 0x41, 0x05}, // Select DPHY_SKINP_TIMING register
{0x1a, 0x42, 0x40}, // Write TSKIP_CNT value for 2*47.5 = 95 MHz DSI clock frequency, Round(95*2*3*65/1000 - 5) = 32
#if 1
{0x1a, 0x40, 0x10}, // Select DSI/D-PHY Analog Indirect Registers
{0x1a, 0x41, 0x86}, // Set Indirect register addr to DSI0_CLK_INVERSION
{0x1a, 0x42, 0x0A}, // Set DSI0_CLK_INVERSION Register, Inverted sampling clock (normal operation)
{0x1a, 0x41, 0x94}, // Set Indirect register addr to DSI1_CLK_INVERSION
{0x1a, 0x42, 0x0A}, // Set DSI1_CLK_INVERSION Register, Inverted sampling clock (normal operation)
#endif
{0x1a, 0x1E, 0x01}, // Select FPD-Link Port 0
{0x1a, 0x40, 0x04},
{0x1a, 0x41, 0x20}, // Select DSI_CONFIG_0
{0x1a, 0x42, 0x6F}, // Don't regenerate orignal VS/HS Timing
{0x1a, 0x01, 0x00}, // Enable the DSI inputs
};
2.DSI timing configuration at SOC:
#if def ENABLE_DSS_DSI
prm.display_type = APP_DSS_DEFAULT_DISPLAY_TYPE_DSI;
prm.timings.width = 2*1920U;
prm.timings.height = 720U;
prm.timings.hFrontPorch = 2*72U;
prm.timings.hBackPorch = 2*72U;
prm.timings.hSyncLen = 2*16U;
prm.timings.vFrontPorch = 19U;
prm.timings.vBackPorch = 19U;
prm.timings.vSyncLen = 2U;
prm.timings.pixelClock = 2*95000000ULL;
#endif
status = appDssDefaultInit(&prm);
APP_ASSERT_SUCCESS(status);
Best regards
Damon
