TDA4VM: CCS: Error on running the MCU1_0 core with TI Debugger

Namashivayam Rajendran

Part Number: TDA4VM

Hello Team,

I am using the external XDS110 debugger on the J7 TDA4V EVM with Virtualbox 6.1 running Ubuntu 18.04. The EVM is in No boot mode and i am able to load the launch scripts.Then, i try to load the binaries or when i try to run the default sciserver application on MCU1_0 core, the below error message pops up and i am not able to proceed further.This issue is always reproducible and it does not gets resolved.

I am unable to understand the root cause of the issue.

As a backup plan, i have installed CCS on windows environment, the same EVM with the XDS110 debugger works seamlessly.

Kindly let me know how to resolve this issue.

over 3 years ago

0 Namashivayam Rajendran over 3 years ago

Intellectual 960 points

4341.CCS_log.txt

DMSC_Cortex_M3_0: GEL Output: Configuring ATCM for the R5Fs
DMSC_Cortex_M3_0: GEL Output: ATCM Configured.
DMSC_Cortex_M3_0: GEL Output: This GEL is currently only supported for use from the Cortex-M3 inside the DMSC.
DMSC_Cortex_M3_0: GEL Output: Do not run this GEL from any other CPU on the SoC.
DMSC_Cortex_M3_0: GEL Output: This script sets the first address translation region to [0x8000_0000, 0x0000_0000].
DMSC_Cortex_M3_0: GEL Output: It also sets the second address translation region to [0x6000_0000, 0x4000_0000].
DMSC_Cortex_M3_0: GEL Output: This is consistent with the SoC DV assumptions.
DMSC_Cortex_M3_0: GEL Output: C66xx_0 configured for Wait In Reset Mode
DMSC_Cortex_M3_0: GEL Output: C66xx_1 configured for Wait In Reset Mode
DMSC_Cortex_M3_0: GEL Output: C71x_0 configured for Wait In Reset Mode
DMSC_Cortex_M3_0: GEL Output: R5F Halt bits set.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_WKUPMCU2MAIN
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Checking LPSC_WKUPMCU2MAIN
DMSC_Cortex_M3_0: GEL Output: Power Domain: On
DMSC_Cortex_M3_0: GEL Output: Module State: Enable
DMSC_Cortex_M3_0: GEL Output: Programming all PLLs.
DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 0 (Main PLL)
DMSC_Cortex_M3_0: GEL Output: Main PLL 0 (Main PLL) Set.
DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 1 (Peripheral 0 PLL)
DMSC_Cortex_M3_0: GEL Output: Main PLL 1 (Peripheral 0 PLL) Set.
DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 2 (Peripheral 1 PLL)
DMSC_Cortex_M3_0: GEL Output: Main PLL 2 (Peripheral 1 PLL) Set.
DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 3 (CPSW9G PLL)
DMSC_Cortex_M3_0: GEL Output: Main PLL 3 (CPSW9G PLL) Set.
DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 4 (Audio 0 PLL)
DMSC_Cortex_M3_0: GEL Output: Main PLL 4 (Audio 0 PLL) Set.
DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 5 (Video PLL)
DMSC_Cortex_M3_0: GEL Output: Main PLL 5 (Video PLL) Set.
DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 6 (GPU PLL)
DMSC_Cortex_M3_0: GEL Output: Main PLL 6 (GPU PLL) Set.
DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 7 (C7x PLL)
DMSC_Cortex_M3_0: GEL Output: Main PLL 7 (C7x PLL) Set.
DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 8 (ARM0 PLL)
DMSC_Cortex_M3_0: GEL Output: Main PLL 8 (ARM0 PLL) Set.
DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 12 (DDR PLL)
DMSC_Cortex_M3_0: GEL Output: DDR PLL Calibration Control MMR value: 0x80170000
DMSC_Cortex_M3_0: GEL Output: DDR PLL Calibration Control MMR value: 0x80000F0D
DMSC_Cortex_M3_0: GEL Output: Main PLL 12 (DDR PLL) Set.
DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 13 (C66x PLL)
DMSC_Cortex_M3_0: GEL Output: Main PLL 13 (C66x PLL) Set.
DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 14 (Main Domain Pulsar) PLL)
DMSC_Cortex_M3_0: GEL Output: Main PLL 14 (Main Domain Pulsar PLL) Set.
DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 15 (Audio 1 PLL)
DMSC_Cortex_M3_0: GEL Output: Main PLL 15 (Audio 1 PLL) Set.
DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 16 (DSS0 PLL)
DMSC_Cortex_M3_0: GEL Output: Main PLL 16 (DSS0 PLL) Set.
DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 17 (DSS1 PLL)
DMSC_Cortex_M3_0: GEL Output: Main PLL 17 (DSS1 PLL) Set.
DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 18 (DSS2 PLL)
DMSC_Cortex_M3_0: GEL Output: Main PLL 17 (DSS2 PLL) Set.
DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 19 (DSS3 PLL)
DMSC_Cortex_M3_0: GEL Output: Main PLL 19 (DSS3 PLL) Set.
DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 23 (DSS7 PLL)
DMSC_Cortex_M3_0: GEL Output: Main PLL 23 (DSS7 PLL) Set.
DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 25 (Vision PLL)
DMSC_Cortex_M3_0: GEL Output: Main PLL 25 (Vision PLL) Set.
DMSC_Cortex_M3_0: GEL Output: Programming MCU PLL 0 (MCU PLL)
DMSC_Cortex_M3_0: GEL Output: MCU PLL 0 (MCU PLL) Set.
DMSC_Cortex_M3_0: GEL Output: Programming MCU PLL 1 (MCU Peripheral PLL)
DMSC_Cortex_M3_0: GEL Output: MCU PLL 1 (MCU PLL) Set.
DMSC_Cortex_M3_0: GEL Output: Programming MCU PLL 2 (MCU CPSW PLL)
DMSC_Cortex_M3_0: GEL Output: MCU PLL 2 (MCU PLL) Set.
DMSC_Cortex_M3_0: GEL Output: All PLLs programmed.
DMSC_Cortex_M3_0: GEL Output: Powering up all PSC power domains in progress...
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_WKUP_ALWAYSON
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_DMSC
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_DEBUG2DMSC
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_WKUP_GPIO
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_WKUPMCU2MAIN
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_TEST
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_DEBUG
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_MCAN_0
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_MCAN_1
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_OSPI_0
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_OSPI_1
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_HYPERBUS
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_I3C_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_I3C_1
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_ADC_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_ADC_1
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_R5_0
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_R5_1
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_PULSAR_PBIST_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_ALWAYSON
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_TEST
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_PBIST
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PER_AUDIO
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PER_ATL
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PER_MLB
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PER_MOTOR
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PER_MISCIO
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PER_GPMC
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PER_VPFE
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PER_VPE
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_DEBUG
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_EMIF_CFG_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_EMIF_DATA_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_EMIF_CFG_1
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_EMIF_DATA_1
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_DMTIMER_0
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_DMTIMER_1
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_DMTIMER_2
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_DMTIMER_3
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MMC4B_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MMC4B_1
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MMC8B_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_UFS_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_UFS_1
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_SAUL
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PER_I3C
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_MCANSS_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_MCANSS_1
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_MCANSS_2
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_MCANSS_3
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_MCANSS_4
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_MCANSS_5
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_MCANSS_6
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_MCANSS_7
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_MCANSS_8
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_MCANSS_9
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_MCANSS_10
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_MCANSS_11
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_MCANSS_12
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_MCANSS_13
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_SERDES_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_SERDES_1
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_SERDES_2
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_SERDES_3
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_SERDES_4
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_SERDES_5
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_USB_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_USB_1
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_USB_2
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PCIE_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PCIE_1
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PCIE_2
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PCIE_3
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_ICSSG_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_ICSSG_1
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_9GSS
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_DSS_PBIST
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_DSS
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_TX_DPHY_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_DSI
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_EDP_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_EDP_1
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_CSITX_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_CSIRX_PHY_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_CSIRX_PHY_1
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_CSIRX_PHY_2
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_CSIRX_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_CSIRX_1
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_CSIRX_2
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_C71X_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_C71X_1
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_C71X_0_PBIST
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_C71X_1_PBIST
DMSC_Cortex_M3_0: GEL Output: ERROR: module state NOT changed!
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_A72_CLUSTER_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_A72_CLUSTER_0_PBIST
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_A72_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_A72_1
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_A72_CLUSTER_1
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_A72_CLUSTER_1_PBIST
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_A72_2
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_A72_3
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_GPUCOM
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_GPUPBIST
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_GPUCORE
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_C66X_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_C66X_PBIST_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_C66X_1
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_C66X_PBIST_1
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PULSAR_0_R5_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PULSAR_0_R5_1
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PULSAR_0_PBIST
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PULSAR_1_R5_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PULSAR_1_R5_1
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PULSAR_1_PBIST
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_DECODE_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_DECODE_PBIST
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_ENCODE_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_ENCODE_PBIST
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_DMPAC
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_SDE
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_DMPAC_PBIST
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_VPAC
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_VPAC_PBIST
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up all PSC power domains done!
DMSC_Cortex_M3_0: GEL Output: Configuring drive strength.
DMSC_Cortex_M3_0: GEL Output: First, unlock the MMRs.
DMSC_Cortex_M3_0: GEL Output: Unlocked MMRs.
DMSC_Cortex_M3_0: GEL Output: Configuring horizontal drive strength.
DMSC_Cortex_M3_0: GEL Output: Horizontal drive strength configured.
DMSC_Cortex_M3_0: GEL Output: Configuring vertical drive strength.
DMSC_Cortex_M3_0: GEL Output: Vertical drive strength configured.
DMSC_Cortex_M3_0: GEL Output: LVCMOS drive strength configured to 0xD
DMSC_Cortex_M3_0: GEL Output: --->>> LPDDR4 Initialization is in progress ... <<<---
DMSC_Cortex_M3_0: GEL Output: Setting DDR PLL to 20MHz/19.2MHz on silicon (bypass)
DMSC_Cortex_M3_0: GEL Output: Set PLL to external bypass (20MHz/19.2MHz on SVB/EVM).
DMSC_Cortex_M3_0: GEL Output: --->>> DDR controller programming in progress.. <<<---
DMSC_Cortex_M3_0: GEL Output: --->>> DDR controller programming completed... <<<---
DMSC_Cortex_M3_0: GEL Output: --->>> DDR PI programming in progress.. <<<---
DMSC_Cortex_M3_0: GEL Output: --->>> DDR PI programming completed... <<<---
DMSC_Cortex_M3_0: GEL Output: --->>> DDR PHY Data Slice 0 programming in progress.. <<<---
DMSC_Cortex_M3_0: GEL Output: --->>> DDR PHY Data Slice 0 programming completed... <<<---
DMSC_Cortex_M3_0: GEL Output: --->>> DDR PHY Data Slice 1 programming in progress.. <<<---
DMSC_Cortex_M3_0: GEL Output: --->>> DDR PHY Data Slice 1 programming completed... <<<---
DMSC_Cortex_M3_0: GEL Output: --->>> DDR PHY Data Slice 2 programming in progress.. <<<---
DMSC_Cortex_M3_0: GEL Output: --->>> DDR PHY Data Slice 2 programming completed... <<<---
DMSC_Cortex_M3_0: GEL Output: --->>> DDR PHY Data Slice 3 programming in progress.. <<<---
DMSC_Cortex_M3_0: GEL Output: --->>> DDR PHY Data Slice 3 programming completed... <<<---
DMSC_Cortex_M3_0: GEL Output: --->>> DDR PHY Address slice 0 programming in progress.. <<<---
DMSC_Cortex_M3_0: GEL Output: --->>> DDR PHY Address Slice 0 programming completed... <<<---
DMSC_Cortex_M3_0: GEL Output: --->>> DDR PHY programming in progress.. <<<---
DMSC_Cortex_M3_0: GEL Output: --->>> DDR PHY programming completed... <<<---
DMSC_Cortex_M3_0: GEL Output: --->>> DDR PI initialization started... <<<---
DMSC_Cortex_M3_0: GEL Output: --->>> DDR Controller initialization started... <<<---
DMSC_Cortex_M3_0: GEL Output: --->>> Waiting for frequency change requests ... <<<---
DMSC_Cortex_M3_0: GEL Output: Frequency change request type 1 received from controller
DMSC_Cortex_M3_0: GEL Output: Setting DDR PLL + HSDIV to 933MHz
DMSC_Cortex_M3_0: GEL Output: DDR PLL Calibration Control MMR value: 0x80170000
DMSC_Cortex_M3_0: GEL Output: DDR PLL Calibration Control MMR value: 0x80000F16
DMSC_Cortex_M3_0: GEL Output: DDR PLL + HSDIV set to 933MHz.
DMSC_Cortex_M3_0: GEL Output: Frequency change request type 0 received from controller
DMSC_Cortex_M3_0: GEL Output: Setting DDR PLL to 20MHz/19.2MHz on silicon (bypass)
DMSC_Cortex_M3_0: GEL Output: Set PLL to external bypass (20MHz/19.2MHz on SVB/EVM).
DMSC_Cortex_M3_0: GEL Output: Frequency change request type 1 received from controller
DMSC_Cortex_M3_0: GEL Output: Setting DDR PLL + HSDIV to 933MHz
DMSC_Cortex_M3_0: GEL Output: DDR PLL Calibration Control MMR value: 0x80170000
DMSC_Cortex_M3_0: GEL Output: DDR PLL Calibration Control MMR value: 0x80000EDE
DMSC_Cortex_M3_0: GEL Output: DDR PLL + HSDIV set to 933MHz.
DMSC_Cortex_M3_0: GEL Output: Frequency change request type 0 received from controller
DMSC_Cortex_M3_0: GEL Output: Setting DDR PLL to 20MHz/19.2MHz on silicon (bypass)
DMSC_Cortex_M3_0: GEL Output: Set PLL to external bypass (20MHz/19.2MHz on SVB/EVM).
DMSC_Cortex_M3_0: GEL Output: Frequency change request type 1 received from controller
DMSC_Cortex_M3_0: GEL Output: Setting DDR PLL + HSDIV to 933MHz
DMSC_Cortex_M3_0: GEL Output: DDR PLL Calibration Control MMR value: 0x80170000
DMSC_Cortex_M3_0: GEL Output: DDR PLL Calibration Control MMR value: 0x80000ED5
DMSC_Cortex_M3_0: GEL Output: DDR PLL + HSDIV set to 933MHz.
DMSC_Cortex_M3_0: GEL Output: Frequency change request type 2 received from controller
DMSC_Cortex_M3_0: GEL Output: Setting DDR PLL + HSDIV to 933MHz
DMSC_Cortex_M3_0: GEL Output: DDR PLL Calibration Control MMR value: 0x80170000
DMSC_Cortex_M3_0: GEL Output: DDR PLL Calibration Control MMR value: 0x80000FD6
DMSC_Cortex_M3_0: GEL Output: DDR PLL + HSDIV set to 933MHz.
DMSC_Cortex_M3_0: GEL Output: Frequency change request type 1 received from controller
DMSC_Cortex_M3_0: GEL Output: Setting DDR PLL + HSDIV to 933MHz
DMSC_Cortex_M3_0: GEL Output: DDR PLL Calibration Control MMR value: 0x80170000
DMSC_Cortex_M3_0: GEL Output: DDR PLL Calibration Control MMR value: 0x80000ED5
DMSC_Cortex_M3_0: GEL Output: DDR PLL + HSDIV set to 933MHz.
DMSC_Cortex_M3_0: GEL Output: Frequency change request type 2 received from controller
DMSC_Cortex_M3_0: GEL Output: Setting DDR PLL + HSDIV to 933MHz
DMSC_Cortex_M3_0: GEL Output: DDR PLL Calibration Control MMR value: 0x80170000
DMSC_Cortex_M3_0: GEL Output: DDR PLL Calibration Control MMR value: 0x80000EE2
DMSC_Cortex_M3_0: GEL Output: DDR PLL + HSDIV set to 933MHz.
DMSC_Cortex_M3_0: GEL Output: Frequency change request type 1 received from controller
DMSC_Cortex_M3_0: GEL Output: Setting DDR PLL + HSDIV to 933MHz
DMSC_Cortex_M3_0: GEL Output: DDR PLL Calibration Control MMR value: 0x80170000
DMSC_Cortex_M3_0: GEL Output: DDR PLL Calibration Control MMR value: 0x80000EC2
DMSC_Cortex_M3_0: GEL Output: DDR PLL + HSDIV set to 933MHz.
DMSC_Cortex_M3_0: GEL Output: Frequency change request type 2 received from controller
DMSC_Cortex_M3_0: GEL Output: Setting DDR PLL + HSDIV to 933MHz
DMSC_Cortex_M3_0: GEL Output: DDR PLL Calibration Control MMR value: 0x80170000
DMSC_Cortex_M3_0: GEL Output: DDR PLL Calibration Control MMR value: 0x80000EAE
DMSC_Cortex_M3_0: GEL Output: DDR PLL + HSDIV set to 933MHz.
DMSC_Cortex_M3_0: GEL Output: --->>> All frequency change requests have completed... <<<---
DMSC_Cortex_M3_0: GEL Output: --->>> LPDDR4 Initialization is DONE! <<<---
MCU_Cortex_R5_0: Trouble Reading Memory Block at 0x18e59ff0 on Page 0 of Length 0x4: (Error -1205 @ 0x18E59FF0) Device memory bus has an error and may be hung. Verify that the memory address is in valid memory. If error persists, confirm configuration, power-cycle board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 9.4.0.00129)
MCU_Cortex_R5_0: Trouble Reading Memory Block at 0x4101667c on Page 0 of Length 0x4: (Error -1205 @ 0x4101667C) Device memory bus has an error and may be hung. Verify that the memory address is in valid memory. If error persists, confirm configuration, power-cycle board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 9.4.0.00129)
MCU_Cortex_R5_0: Trouble Reading Memory Block at 0x41c1c53c on Page 0 of Length 0x4: (Error -1205 @ 0x41C1C53C) Device memory bus has an error and may be hung. Verify that the memory address is in valid memory. If error persists, confirm configuration, power-cycle board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 9.4.0.00129)
MCU_Cortex_R5_0: Can't Run Target CPU: (Error -1205 @ 0x41CA772C) Device memory bus has an error and may be hung. Verify that the memory address is in valid memory. If error persists, confirm configuration, power-cycle board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 9.4.0.00129)
MCU_Cortex_R5_0: Trouble Reading Memory Block at 0x41016680 on Page 0 of Length 0x4: (Error -1205 @ 0x41016680) Device memory bus has an error and may be hung. Verify that the memory address is in valid memory. If error persists, confirm configuration, power-cycle board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 9.4.0.00129)
MCU_Cortex_R5_0: Trouble Reading Memory Block at 0x41016688 on Page 0 of Length 0x4: (Error -1205 @ 0x41016688) Device memory bus has an error and may be hung. Verify that the memory address is in valid memory. If error persists, confirm configuration, power-cycle board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 9.4.0.00129)
MCU_Cortex_R5_0: Trouble Reading Memory Block at 0x410166b4 on Page 0 of Length 0x4: (Error -1205 @ 0x410166B4) Device memory bus has an error and may be hung. Verify that the memory address is in valid memory. If error persists, confirm configuration, power-cycle board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 9.4.0.00129)
MCU_Cortex_R5_0: Trouble Reading Memory Block at 0x41c1c538 on Page 0 of Length 0x4: (Error -1205 @ 0x41C1C538) Device memory bus has an error and may be hung. Verify that the memory address is in valid memory. If error persists, confirm configuration, power-cycle board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 9.4.0.00129)
MCU_Cortex_R5_0: Trouble Reading Memory Block at 0x20000200 on Page 0 of Length 0x1: (Error -1205 @ 0x20000200) Device memory bus has an error and may be hung. Verify that the memory address is in valid memory. If error persists, confirm configuration, power-cycle board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 9.4.0.00129)
MCU_Cortex_R5_0: Trouble Reading Memory Block at 0x0 on Page 0 of Length 0x1: (Error -1205 @ 0x0) Device memory bus has an error and may be hung. Verify that the memory address is in valid memory. If error persists, confirm configuration, power-cycle board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 9.4.0.00129)
MCU_Cortex_R5_0: Trouble Reading Memory Block at 0x20000200 on Page 0 of Length 0x1: (Error -1205 @ 0x20000200) Device memory bus has an error and may be hung. Verify that the memory address is in valid memory. If error persists, confirm configuration, power-cycle board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 9.4.0.00129)
MCU_Cortex_R5_0: Error: (Error -1170 @ 0x40040000) Unable to access the DAP. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 9.4.0.00129)
MCU_Cortex_R5_0: Error: (Error -1170 @ 0x0) Unable to access the DAP. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 9.4.0.00129)
MCU_Cortex_R5_0: Unable to determine target status after 20 attempts
MCU_Cortex_R5_0: Failed to remove the debug state from the target before disconnecting. There may still be breakpoint op-codes embedded in program memory. It is recommended that you reset the emulator before you connect and reload your program before you continue debugging

Hello Team,

I have also installed the new CCS version 10.4 with sudo access, i am still getting the same error as in previous post and along with it some more errors.

0 Ki over 3 years ago in reply to Namashivayam Rajendran

TI__Guru**** 433871 points

Hello,

Based on the messages, it appears that the debugger can communicate to the target via the debug probe.

The main errors are:

https://software-dl.ti.com/ccs/esd/documents/ccs_debugging_jtag_connectivity_issues.html#device-hung

https://software-dl.ti.com/ccs/esd/documents/ccs_debugging_jtag_connectivity_issues.html#cannot-access-the-dap

These errors are almost always due to the device/target being in a bad state. It is usually because of a target configuration or initialization issue.

A power cycle or system reset can help here. Please give that a try. If that fails to remedy the problem, I'll need to escalate this to the device time for further suggestions.

Thanks

0 Namashivayam Rajendran over 3 years ago in reply to Ki

Intellectual 960 points

Hello Ki,

I have tried out with the target configuration and resolution for the issues, but i am always affected by the same issue.

I have also tried with installation of CCS on Windows and using the onboard Debugger on J7 TDA4 EVM. But i see that the issue remains the same.

Please let me know how we can resolve the issue at the earliest.

Thanks and Regards,

0 Ki over 3 years ago in reply to Namashivayam Rajendran

TI__Guru**** 433871 points

Namashivayam Rajendran said:
I have also tried with installation of CCS on Windows and using the onboard Debugger on J7 TDA4 EVM. But i see that the issue remains the same.

In your first post, you mentioned that it was working on Windows. Is it no longer working now?

0 Namashivayam Rajendran over 3 years ago in reply to Ki

Intellectual 960 points

Hello Ki,

Yes, its erratic on Windows, sometimes it works and sometimes it doesn't. Karthik has suggested to set the loadsciserverflag to 0, as a workaround and now i am still getting this error. But after a relaunch it gets resolved.

0 Ki over 3 years ago in reply to Namashivayam Rajendran

TI__Guru**** 433871 points

Thanks for the confirmation. As mentioned earlier, these issues are often due to the device getting in a bad state. I will bring this attention to the device experts for further assistance.

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TDA4VM: CCS: Error on running the MCU1_0 core with TI Debugger