This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
Summary:
We are using the AM3358 with a DDR3 DRAM from ISSI (4GBit) in one of our custom boards. We have a wierd issue where 8-bit values (char, uint8_t etc.) are not getting written to DRAM locations properly. Even if it does get written (very rare occasion) hey are erratic. No issues with 16-bit or larger variables.
Test scenario:
1. Connect JTAG to our board with CCS (10.2) and go through the initialization procedure for clocks and EMIF with a GEL file. This GEL file was cloned from AM33558 SK GEL with the DDR parameters replaced by the values calculated by TI's EMIF config tool
2. Load a simple program with a test function as shown below:
#pragma GCC push_options
#pragma GCC optimize ("O0")
void testFunction(){
char i1 = 0;
char i2 = 0;
char i3 = 0;
char i4 = 0;
i1 = 0xFF;
i2 = 0xFF;
i3 = 0xFF;
i4 = 0xFF;
}
#pragma GCC pop_options
3. Step through assembly instruction while observing the memory locations of i1,i2,i3,i4 using the memory browser
Observation:
Each ix = 0xFF; line are 2 assembly instructions: a mov and a strb. When the strb instruciton is executed i cannot see the memory location (DRAM) getting updated in the memory browser.
Supporting evidence:
Instead of char, if I try short or int I can see the memory locations getting updated 16-bits and 32-bits respectively
Control experiment:
Tried following the exact same steps with a BeagleBone Black (with the same EMIF settings as ours, and original GEL file for the BBB) and I can see the memory locations getting updated for char, short and int
Would highly appreciate if anyone could assist
Thanks in advance!
Aka
Thanks for the response James. Would it be ok if I share the schematics with you via a private message?
Thanks
Aka
Hi James,
Schematics already provided via email. Do let me know if you didn't receive it.
I think the problem is that the schematics show the different byte lanes are not connected correctly. DQ7:0 is connected to the upper byte of the memory (DQU7:0), yet DQS0 and DQM0 are connected to the lower byte (DQSL and DQL respectively). The same is true for the upper byte. Thus when you perform byte wise transactions, the data will not be present on the correct byte lane when written.
Regards,
James