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Original question:

AM4378: MIN values for Input signal rise time and Input signal fall time

AM4378: Input signal transition time of CPU and CODEC

Kanae
Mastermind 9745 points
Part Number: AM4378
Other Parts Discussed in Thread: TLV320AIC3104, SN74AVC4T245

Hi Support Team,

I have the following question regarding the signals (McASP) between AM437x processor and CODEC (TLV320AIC3104).

AM437x datasheet states that tR and tF for the following input signals are between 1 and 4ns.



I understand that this transition time is specified as 10 to 90% from the following forum response.

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1091140/am4378-min-values-for-input-signal-rise-time-and-input-signal-fall-time

Also, CODEC datasheet states that tR and tF are ~10ns at IOVDD=3.3V.

Currently, in my customer's prototype board, AM437x processor and CODEC (TLV320AIC3104) are connected via McASP (I2S).

The signal lines (WCLK, BCLK, Din, Dout) are directly connected between CPU and CODEC using CODEC as Master mode,
but the actual measurement of tR and tF of each signal WCLK, BCLK, Din, Dout is about 15ns,
which exceeds the maximum value of input signal transition time of CPU and CODEC.

So, here are questions.

Q1: For WCLK, BCLK, and Data timing requests (setup, hold), the current signal transition time of 15ns has enough margin,
 but is this transition time acceptable?
 If not, what kind of problem would be caused?

Q2: To achieve the transition time requirement, it is necessary to add a buffer between CPU and CODEC.
 Referring to the AM437x evaluation board schematic, the connection is made via SN74AVC4T245 and 74LVC1G125 as shown below.

The datasheets for the SN74AVC4T245 and 74LVC1G125 could not be found any mention of transition times for the output signals.
How can I confirm that the transition time of the CPU's McASP input signal is 1 to 4 ns
and the transition time of the CODEC's I2S input signal is ~10 ns?

Best regards,
Kanae

  • 0
    Mastermind 9745 points

    Hi Support Team,

    My customer has reported the following.

    We are very sorry for the prompt response to this matter.
    Further confirmation has revealed that there was an error in the measurement device settings and that the transition time was not measured correctly.
    As a result of re-measuring with normal settings, we have confirmed that the McASP signal transition time between CPU and CODEC is within the value described in the datasheet and that there is no problem.
    Based on the above, we ask that this question be closed.
    We apologize again for any inconvenience caused by our lack of confirmation.

    Therefore, I am closing this issue.
    Thank you for your support.

    Best regards,
    Kanae

  • 0 in reply to Kanae
    TI__Mastermind 29440 points

    Hi Kanae,

    Thank you for following up with that correction. Apologies for taking so long to reply.

    As long as the timing analysis shows positive margin (which is typical for codecs), then the McASP communication should work fine.

    Regards,
    Mark