This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AM625: PIMIC Part Number Selection

Part Number: AM625
Other Parts Discussed in Thread: TPS65219,

Hi E2E Team,

There are four difference configurations available for PIMIC- TPS65219. Factory setting for all four configurations are given in table 3-1 of Powering the AM62x with the TPS65219 PMIC.

Our use case is similar to use case given in " 4.4 TPS6521904 Powering AM62x" on page no 12 into Powering the AM62x with the TPS65219 PMIC. But we are planning to use LPDDR4 instead of DDR4 which has volt. req. of 1.1V instead of 1.2V.

We can generate the required volt. (1.1V instead of 1.2V) by changing the value of BUCKx_VSET resistor but we don't want to add extra controller into design just to updated the values into BUCKx_VSET resistor via I2C interrace each time we power on the board..

Please let us know your suggestion here on how we can avoid extra controller into design.

Regards,

Aditya

  • Hello Aditya,

    Apologies for the delayed response. Your thread was assigned to the wrong team member. I am reassigning the thread. Please ping the thread if you do not get a response within 1-2 business days.

    Regards,

    Nick

  • Hello Aditya

    Thank you for the query.

    As you mentioned, The PMIC configurations are fixed. AM625 does not support dynamic switching of supply rails. 

    We do not have any other suggestion on changing the voltage other than the register configuration.

    Have you analyzed the effect of programming the LPDDR voltage on-board on the LPDDR performance ?

    Regards,

    Sreenivasa

  • Hello Kallikuppa,

    Thanks for your response.

    "Have you analyzed the effect of programming the LPDDR voltage on-board on the LPDDR performance ?"

    Our use case is similar to use case given in " 4.4 TPS6521904 Powering AM62x" on page no 12 into Powering the AM62x with the TPS65219 PMIC. Only change is that we want to use LPDDR4 instead of DDR4. LPDDR4 requires 1.1V and 1.8V in contrast to DDR4 which requires 1.2V and 2.5V. Hence require 1.1V from PIMIC.

    "We do not have any other suggestion on changing the voltage other than the register configuration."

    Do we need to add an extra controller into our design just to configure the PIMIC?

    Is there any way to add an memory (for example EEPROM) with required configuration files on PIMIC I2C interface and during POR, PIMIC can first configure itself based on memory content then start voltage regulation?

    Regards,

    Aditya

  • Hello Aditya

    Thank you for the inputs. 

    Do we need to add an extra controller into our design just to configure the PIMIC?

    Not sure on how this controller would help since the PMIC is already operating and generating the supply rails.

    I will assign to the PMIC expert to check if they have some suggestions. Please expect a delay in response.

    Regards,

    Sreenivasa

     

  • Hi Aditya,

    Thank You for using E2E! I'm the applications engineer for the TPS65219 PMIC. We recently created a new NVM configuration to support applications using 3.3V supply, LPDDR4 and 0.85V on the CORE rail. 

    The part number for this new NVM is TPS6521908RHBR and we are currently supporting pre-production samples under OPN "PTPS6521908RHBR". The block diagram below shows the recommended connections. Similar to the "04" version, this NVM also has LDO2 configured as bypass and will require a 1.8V input supply. The "EN/PB/VSENSE" pin is configured as "ENABLE" instead of push-button. Please let us know if you have any additional questions. 

    Thanks,

    Brenda

  • Hello Brenda, 

    Thank you for the detailed note.

    I have a follow-up question. In case customer would want to program the NVM, do you have some recommendations ?

    Regards,

    Sreenivasa

  • Hi Sreenivasa,

    Yes, we also plan to release a user programmable version of the TPS65219 PMIC. It will come with all the rails disabled by default and customers will have the option to work with approved TI distributors to program their own custom NVM settings. We are expecting to release collateral for the DYI version later in 4Q2022. 

    Thanks,

    Brenda

  • Hi Brenda,

    Thanks for the detailed information.

    Currently released PIMIC versions like PTPS6521901RHBR and PTPS6521903RHBR are pre-flashed and will follow the default settings during POR. 

    Once system is up and running, can we updated the resistor values (for example: to generate 0.85V instead of 0.75V from Buck1) and do the soft-reset via I2C interface? Our expectation here is that after soft reset the PIMIC will generate the voltages as per new resistor values.

    Regards,

    Aditya

  • Hi Aditya,

    Thanks for the discussion this morning! As we talked, it seems like the new NVMs that were recently defined will meet your application requirements. I'll be providing the technical reference manual for TPS6521907 and TPS6521908. 

    Any changes to the register settings will go back to the default values after reset or power cycle. 

    Thanks,

    Brenda