J7200XSOMXEVM: CAN Interfaces

Part Number: J7200XSOMXEVM
Other Parts Discussed in Thread: DRA821, TCA6408, TCA6416, TCA6424, TCAN1042-Q1

Customer having trouble with CAN (and USB) Interfaces on this EVM.

  1. How to configure/enable the CAN interface on the DRA821 evaluation kit (how do we test?).
  • Hi,

    Can you please create another thread for USB and we and we can discuss CAN here?

    How to configure/enable the CAN interface on the DRA821 evaluation kit (how do we test?).

    Do you want to test CAN from A72 Linux or from FreeRTOS running on the R5Fs?

    Regards

    Karan

  • Mainly I need to know how to enable the interface and the driver and once enabled which interface will be usable.

    I am running the default  Linux kernel provided on the 16G SD card:

    Linux netbotz8643b288 5.10.100-g7a7a3af903 #1 SMP PREEMPT Thu Mar 24 08:25:59 UTC 2022 aarch64 aarch64 aarch64 GNU/Linux

  • I also see this in the console occasionally when booting , but I do not see any /dev/can0:


    [ 109.082624] can: controller area network core
    [ 109.087120] NET: Registered protocol family 29
    [ 109.106123] can: raw protocol

  • Please use the below linked e2e, it should guide you through the process of testing CAN from Linux. You will NOT need any patches now but refer the "Debug tips" section.

    https://e2e.ti.com/support/processors-group/processors/f/processors-forum/922168/faq-tda4vm-how-can-i-use-can-on-linux

    Regards

    Karan

  • Hi, I am not sure how to get this across.
    On the default linux kernel provided there is NOT a /dev/can0.  So I cannot test or use anything CAN related. The link provide nothing in regards to the issue and  provides nothing that is usable in this case.

  • Hi, I am not sure how to get this across.
    On the default linux kernel provided there is NOT a /dev/can0.  So I cannot test or use anything CAN related. The link provide nothing in regards to the issue and  provides nothing that is usable in this case.

  • I have can running after patching the DTB files. I now have access to can0. I noted from the document that can0 was supposed to be on J30 a 4 pin header but I am seeing that J31 is actually where I can see can data using the candump. I am also seeing a lot of bus restarts:

    root@netbotz8643b288:~# [ 804.355740] m_can_platform 40568000.can can0: bus-off, scheduling restart in 100 ms
    [ 804.465061] IPv6: ADDRCONF(NETDEV_CHANGE): can0: link becomes ready
    [ 807.359499] m_can_platform 40568000.can can0: bus-off, scheduling restart in 100 ms
    [ 807.469064] IPv6: ADDRCONF(NETDEV_CHANGE): can0: link becomes ready
    [ 810.363309] m_can_platform 40568000.can can0: bus-off, scheduling restart in 100 ms

    when I  issue a cansend message with nothing connected to the can interface I get the following

    cansend can0 123#DEADBEEF
    root@netbotz8643b288:~# [ 646.515196] m_can_platform 40568000.can can0: bus-off, scheduling restart in 100 ms
    [ 646.625551] IPv6: ADDRCONF(NETDEV_CHANGE): can0: link becomes ready

    My can settings are:
    /sbin/ip link set can0 up type can bitrate 62500 restart-ms 100

    and I see

    ip -details -statistics link show can0
    3: can0: <NOARP,UP,LOWER_UP,ECHO> mtu 16 qdisc pfifo_fast state UP mode DEFAULT group default qlen 10
    link/can promiscuity 0 minmtu 0 maxmtu 0
    can state ERROR-ACTIVE (berr-counter tx 0 rx 0) restart-ms 100
    bitrate 62500 sample-point 0.875
    tq 62 prop-seg 111 phase-seg1 112 phase-seg2 32 sjw 1
    m_can: tseg1 2..256 tseg2 2..128 sjw 1..128 brp 1..512 brp-inc 1
    m_can: dtseg1 1..32 dtseg2 1..16 dsjw 1..16 dbrp 1..32 dbrp-inc 1
    clock 80000000
    re-started bus-errors arbit-lost error-warn error-pass bus-off
    5 0 0 11 11 5 numtxqueues 1 numrxqueues 1 gso_max_size 65536 gso_max_segs 65535
    RX: bytes packets errors dropped missed mcast
    256 32 0 0 0 0
    TX: bytes packets errors dropped carrier collsns
    0 0 0 5 0 0





    my dts (decoded dtb) contents are:

    /dts-v1/;

    / {
    model = "Texas Instruments K3 J7200 SoC";
    compatible = "ti,j7200";
    interrupt-parent = <0x01>;
    #address-cells = <0x02>;
    #size-cells = <0x02>;

    aliases {
    serial0 = "/bus@100000/bus@28380000/serial@42300000";
    serial1 = "/bus@100000/bus@28380000/serial@40a00000";
    serial2 = "/bus@100000/serial@2800000";
    serial3 = "/bus@100000/serial@2810000";
    serial4 = "/bus@100000/serial@2820000";
    serial5 = "/bus@100000/serial@2830000";
    serial6 = "/bus@100000/serial@2840000";
    serial7 = "/bus@100000/serial@2850000";
    serial8 = "/bus@100000/serial@2860000";
    serial9 = "/bus@100000/serial@2870000";
    serial10 = "/bus@100000/serial@2880000";
    serial11 = "/bus@100000/serial@2890000";
    };

    chosen {
    stdout-path = "serial2:115200n8";
    bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
    };

    cpus {
    #address-cells = <0x01>;
    #size-cells = <0x00>;

    cpu-map {

    cluster0 {
    phandle = <0x47>;

    core0 {
    cpu = <0x02>;
    };

    core1 {
    cpu = <0x03>;
    };
    };
    };

    cpu@0 {
    compatible = "arm,cortex-a72";
    reg = <0x00>;
    device_type = "cpu";
    enable-method = "psci";
    i-cache-size = <0xc000>;
    i-cache-line-size = <0x40>;
    i-cache-sets = <0x100>;
    d-cache-size = <0x8000>;
    d-cache-line-size = <0x40>;
    d-cache-sets = <0x100>;
    next-level-cache = <0x04>;
    phandle = <0x02>;
    };

    cpu@1 {
    compatible = "arm,cortex-a72";
    reg = <0x01>;
    device_type = "cpu";
    enable-method = "psci";
    i-cache-size = <0xc000>;
    i-cache-line-size = <0x40>;
    i-cache-sets = <0x100>;
    d-cache-size = <0x8000>;
    d-cache-line-size = <0x40>;
    d-cache-sets = <0x100>;
    next-level-cache = <0x04>;
    phandle = <0x03>;
    };
    };

    l2-cache0 {
    compatible = "cache";
    cache-level = <0x02>;
    cache-size = <0x100000>;
    cache-line-size = <0x40>;
    cache-sets = <0x400>;
    next-level-cache = <0x05>;
    phandle = <0x04>;
    };

    l3-cache0 {
    compatible = "cache";
    cache-level = <0x03>;
    phandle = <0x05>;
    };

    firmware {

    optee {
    compatible = "linaro,optee-tz";
    method = "smc";
    };

    psci {
    compatible = "arm,psci-1.0";
    method = "smc";
    phandle = <0x48>;
    };
    };

    timer-cl0-cpu0 {
    compatible = "arm,armv8-timer";
    interrupts = <0x01 0x0d 0x08 0x01 0x0e 0x08 0x01 0x0b 0x08 0x01 0x0a 0x08>;
    phandle = <0x49>;
    };

    pmu {
    compatible = "arm,cortex-a72-pmu";
    interrupts = <0x01 0x07 0x04>;
    phandle = <0x4a>;
    };

    bus@100000 {
    compatible = "simple-bus";
    #address-cells = <0x02>;
    #size-cells = <0x02>;
    ranges = <0x00 0x100000 0x00 0x100000 0x00 0x20000 0x00 0x600000 0x00 0x600000 0x00 0x31100 0x00 0xa40000 0x00 0xa40000 0x00 0x800 0x00 0x1000000 0x00 0x1000000 0x00 0xd000000 0x00 0x30000000 0x00 0x30000000 0x00 0xc400000 0x00 0x6f000000 0x00 0x6f000000 0x00 0x310000 0x00 0x70000000 0x00 0x70000000 0x00 0x800000 0x00 0x18000000 0x00 0x18000000 0x00 0x8000000 0x41 0x00 0x41 0x00 0x01 0x00 0x00 0x28380000 0x00 0x28380000 0x00 0x3880000 0x00 0x40200000 0x00 0x40200000 0x00 0x998400 0x00 0x40f00000 0x00 0x40f00000 0x00 0x20000 0x00 0x41000000 0x00 0x41000000 0x00 0x20000 0x00 0x41400000 0x00 0x41400000 0x00 0x20000 0x00 0x41c00000 0x00 0x41c00000 0x00 0x100000 0x00 0x42040000 0x00 0x42040000 0x00 0x3ac2400 0x00 0x45100000 0x00 0x45100000 0x00 0xc24000 0x00 0x46000000 0x00 0x46000000 0x00 0x200000 0x00 0x47000000 0x00 0x47000000 0x00 0x68400 0x00 0x50000000 0x00 0x50000000 0x00 0x10000000 0x05 0x00 0x05 0x00 0x01 0x00 0x07 0x00 0x07 0x00 0x01 0x00>;
    phandle = <0x4b>;

    bus@28380000 {
    compatible = "simple-bus";
    #address-cells = <0x02>;
    #size-cells = <0x02>;
    ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x3880000 0x00 0x40200000 0x00 0x40200000 0x00 0x998400 0x00 0x40f00000 0x00 0x40f00000 0x00 0x20000 0x00 0x41000000 0x00 0x41000000 0x00 0x20000 0x00 0x41400000 0x00 0x41400000 0x00 0x20000 0x00 0x41c00000 0x00 0x41c00000 0x00 0x100000 0x00 0x42040000 0x00 0x42040000 0x00 0x3ac2400 0x00 0x45100000 0x00 0x45100000 0x00 0xc24000 0x00 0x46000000 0x00 0x46000000 0x00 0x200000 0x00 0x47000000 0x00 0x47000000 0x00 0x68400 0x00 0x50000000 0x00 0x50000000 0x00 0x10000000 0x05 0x00 0x05 0x00 0x01 0x00 0x07 0x00 0x07 0x00 0x01 0x00>;
    phandle = <0x4c>;

    dmsc@44083000 {
    compatible = "ti,k2g-sci";
    ti,host-id = <0x0c>;
    mbox-names = "rx\0tx";
    mboxes = <0x06 0x0b 0x06 0x0d>;
    reg-names = "debug_messages";
    reg = <0x00 0x44083000 0x00 0x1000>;
    phandle = <0x09>;

    power-controller {
    compatible = "ti,sci-pm-domain";
    #power-domain-cells = <0x02>;
    phandle = <0x07>;
    };

    clocks {
    compatible = "ti,k2g-sci-clk";
    #clock-cells = <0x02>;
    phandle = <0x08>;
    };

    reset-controller {
    compatible = "ti,sci-reset";
    #reset-cells = <0x02>;
    phandle = <0x1c>;
    };
    };

    syscon@40f00000 {
    compatible = "syscon\0simple-mfd";
    reg = <0x00 0x40f00000 0x00 0x20000>;
    #address-cells = <0x01>;
    #size-cells = <0x01>;
    ranges = <0x00 0x00 0x40f00000 0x20000>;
    phandle = <0x10>;

    phy@4040 {
    compatible = "ti,am654-phy-gmii-sel";
    reg = <0x4040 0x04>;
    #phy-cells = <0x01>;
    phandle = <0x11>;
    };
    };

    chipid@43000014 {
    compatible = "ti,am654-chipid";
    reg = <0x00 0x43000014 0x00 0x04>;
    };

    pinctrl@4301c000 {
    compatible = "pinctrl-single";
    reg = <0x00 0x4301c000 0x00 0x178>;
    #pinctrl-cells = <0x01>;
    pinctrl-single,register-width = <0x20>;
    pinctrl-single,function-mask = <0xffffffff>;
    phandle = <0x4d>;

    mcu-fss0-hpb0-pins-default {
    pinctrl-single,pins = <0x00 0x10001 0x04 0x10001 0x2c 0x10001 0x30 0x10001 0x08 0x50001 0x0c 0x50001 0x10 0x50001 0x14 0x50001 0x18 0x50001 0x1c 0x50001 0x20 0x50001 0x24 0x50001 0x28 0x50001>;
    phandle = <0x14>;
    };

    mcu-fss0-ospi0-pins-default {
    pinctrl-single,pins = <0x00 0x10000 0x2c 0x10000 0x0c 0x50000 0x10 0x50000 0x14 0x50000 0x18 0x50000 0x1c 0x50000 0x20 0x50000 0x24 0x50000 0x28 0x50000 0x08 0x50000>;
    phandle = <0x15>;
    };

    mcu-cpsw-pins-default {
    pinctrl-single,pins = <0x68 0x10000 0x6c 0x50000 0x70 0x10000 0x74 0x10000 0x78 0x10000 0x7c 0x10000 0x88 0x50000 0x8c 0x50000 0x90 0x50000 0x94 0x50000 0x80 0x10000 0x84 0x50000>;
    phandle = <0x0e>;
    };

    mcu-mdio1-pins-default {
    pinctrl-single,pins = <0x9c 0x10000 0x98 0x50000>;
    phandle = <0x0f>;
    };

    mcu-mcan0-pins-default {
    pinctrl-single,pins = <0xbc 0x50000 0xb8 0x10000>;
    phandle = <0x17>;
    };

    mcu-mcan0-gpio-pins-default {
    pinctrl-single,pins = <0xc0 0x50007 0x98 0x50007>;
    phandle = <0x18>;
    };

    mcu-mcan1-pins-default {
    pinctrl-single,pins = <0xd4 0x50000 0xd0 0x10000>;
    phandle = <0x1a>;
    };

    mcu-mcan1-gpio-pins-default {
    pinctrl-single,pins = <0xc8 0x50007>;
    phandle = <0x1b>;
    };
    };

    sram@41c00000 {
    compatible = "mmio-sram";
    reg = <0x00 0x41c00000 0x00 0x100000>;
    ranges = <0x00 0x00 0x41c00000 0x100000>;
    #address-cells = <0x01>;
    #size-cells = <0x01>;
    phandle = <0x4e>;
    };

    serial@42300000 {
    compatible = "ti,j721e-uart\0ti,am654-uart";
    reg = <0x00 0x42300000 0x00 0x100>;
    reg-shift = <0x02>;
    reg-io-width = <0x04>;
    interrupts = <0x00 0x381 0x04>;
    clock-frequency = <0x2dc6c00>;
    current-speed = <0x1c200>;
    power-domains = <0x07 0x11f 0x01>;
    clocks = <0x08 0x11f 0x02>;
    clock-names = "fclk";
    status = "reserved";
    phandle = <0x4f>;
    };

    serial@40a00000 {
    compatible = "ti,j721e-uart\0ti,am654-uart";
    reg = <0x00 0x40a00000 0x00 0x100>;
    reg-shift = <0x02>;
    reg-io-width = <0x04>;
    interrupts = <0x00 0x34e 0x04>;
    clock-frequency = <0x5b8d800>;
    current-speed = <0x1c200>;
    power-domains = <0x07 0x95 0x01>;
    clocks = <0x08 0x95 0x02>;
    clock-names = "fclk";
    phandle = <0x50>;
    };

    interrupt-controller2 {
    compatible = "ti,sci-intr";
    ti,intr-trigger-type = <0x01>;
    interrupt-controller;
    interrupt-parent = <0x01>;
    #interrupt-cells = <0x01>;
    ti,sci = <0x09>;
    ti,sci-dev-id = <0x89>;
    ti,interrupt-ranges = <0x10 0x3c0 0x10>;
    phandle = <0x0a>;
    };

    gpio@42110000 {
    compatible = "ti,j721e-gpio\0ti,keystone-gpio";
    reg = <0x00 0x42110000 0x00 0x100>;
    gpio-controller;
    #gpio-cells = <0x02>;
    interrupt-parent = <0x0a>;
    interrupts = <0x67 0x68 0x69 0x6a 0x6b 0x6c>;
    interrupt-controller;
    #interrupt-cells = <0x02>;
    #address-cells = <0x00>;
    ti,ngpio = <0x55>;
    ti,davinci-gpio-unbanked = <0x00>;
    power-domains = <0x07 0x71 0x01>;
    clocks = <0x08 0x71 0x00>;
    clock-names = "gpio";
    phandle = <0x19>;
    };

    gpio@42100000 {
    compatible = "ti,j721e-gpio\0ti,keystone-gpio";
    reg = <0x00 0x42100000 0x00 0x100>;
    gpio-controller;
    #gpio-cells = <0x02>;
    interrupt-parent = <0x0a>;
    interrupts = <0x70 0x71 0x72 0x73 0x74 0x75>;
    interrupt-controller;
    #interrupt-cells = <0x02>;
    #address-cells = <0x00>;
    ti,ngpio = <0x55>;
    ti,davinci-gpio-unbanked = <0x00>;
    power-domains = <0x07 0x72 0x01>;
    clocks = <0x08 0x72 0x00>;
    clock-names = "gpio";
    status = "disabled";
    phandle = <0x51>;
    };

    bus@28380000 {
    compatible = "simple-mfd";
    #address-cells = <0x02>;
    #size-cells = <0x02>;
    ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x3880000>;
    dma-coherent;
    dma-ranges;
    ti,sci-dev-id = <0xe8>;
    phandle = <0x52>;

    ringacc@2b800000 {
    compatible = "ti,am654-navss-ringacc";
    reg = <0x00 0x2b800000 0x00 0x400000 0x00 0x2b000000 0x00 0x400000 0x00 0x28590000 0x00 0x100 0x00 0x2a500000 0x00 0x40000>;
    reg-names = "rt\0fifos\0proxy_gcfg\0proxy_target";
    ti,num-rings = <0x11e>;
    ti,sci-rm-range-gp-rings = <0x01>;
    ti,sci = <0x09>;
    ti,sci-dev-id = <0xeb>;
    msi-parent = <0x0b>;
    phandle = <0x0c>;
    };

    dma-controller@285c0000 {
    compatible = "ti,j721e-navss-mcu-udmap";
    reg = <0x00 0x285c0000 0x00 0x100 0x00 0x2a800000 0x00 0x40000 0x00 0x2aa00000 0x00 0x40000>;
    reg-names = "gcfg\0rchanrt\0tchanrt";
    msi-parent = <0x0b>;
    #dma-cells = <0x01>;
    ti,sci = <0x09>;
    ti,sci-dev-id = <0xec>;
    ti,ringacc = <0x0c>;
    ti,sci-rm-range-tchan = <0x0d 0x0f>;
    ti,sci-rm-range-rchan = <0x0a 0x0b>;
    ti,sci-rm-range-rflow = <0x00>;
    phandle = <0x0d>;
    };
    };

    ethernet@46000000 {
    compatible = "ti,j721e-cpsw-nuss";
    #address-cells = <0x02>;
    #size-cells = <0x02>;
    reg = <0x00 0x46000000 0x00 0x200000>;
    reg-names = "cpsw_nuss";
    ranges = <0x00 0x00 0x00 0x46000000 0x00 0x200000>;
    dma-coherent;
    clocks = <0x08 0x12 0x15>;
    clock-names = "fck";
    power-domains = <0x07 0x12 0x01>;
    dmas = <0x0d 0xf000 0x0d 0xf001 0x0d 0xf002 0x0d 0xf003 0x0d 0xf004 0x0d 0xf005 0x0d 0xf006 0x0d 0xf007 0x0d 0x7000>;
    dma-names = "tx0\0tx1\0tx2\0tx3\0tx4\0tx5\0tx6\0tx7\0rx";
    pinctrl-names = "default";
    pinctrl-0 = <0x0e 0x0f>;
    phandle = <0x53>;

    ethernet-ports {
    #address-cells = <0x01>;
    #size-cells = <0x00>;

    port@1 {
    reg = <0x01>;
    ti,mac-only;
    label = "port1";
    ti,syscon-efuse = <0x10 0x200>;
    phys = <0x11 0x01>;
    phy-mode = "rgmii-rxid";
    phy-handle = <0x12>;
    phandle = <0x54>;
    };
    };

    mdio@f00 {
    compatible = "ti,cpsw-mdio\0ti,davinci_mdio";
    reg = <0x00 0xf00 0x00 0x100>;
    #address-cells = <0x01>;
    #size-cells = <0x00>;
    clocks = <0x08 0x12 0x15>;
    clock-names = "fck";
    bus_freq = <0x4e20>;
    phandle = <0x55>;

    ethernet-phy@0 {
    reg = <0x00>;
    ti,rx-internal-delay = <0x07>;
    ti,fifo-depth = <0x01>;
    phandle = <0x12>;
    };
    };

    cpts@3d000 {
    compatible = "ti,am65-cpts";
    reg = <0x00 0x3d000 0x00 0x400>;
    clocks = <0x08 0x12 0x02>;
    clock-names = "cpts";
    interrupts-extended = <0x01 0x00 0x35a 0x04>;
    interrupt-names = "cpts";
    ti,cpts-ext-ts-inputs = <0x04>;
    ti,cpts-periodic-outputs = <0x02>;
    };
    };

    i2c@40b00000 {
    compatible = "ti,j721e-i2c\0ti,omap4-i2c";
    reg = <0x00 0x40b00000 0x00 0x100>;
    interrupts = <0x00 0x354 0x04>;
    #address-cells = <0x01>;
    #size-cells = <0x00>;
    clock-names = "fck";
    clocks = <0x08 0xc2 0x01>;
    power-domains = <0x07 0xc2 0x01>;
    phandle = <0x56>;
    };

    i2c@40b10000 {
    compatible = "ti,j721e-i2c\0ti,omap4-i2c";
    reg = <0x00 0x40b10000 0x00 0x100>;
    interrupts = <0x00 0x355 0x04>;
    #address-cells = <0x01>;
    #size-cells = <0x00>;
    clock-names = "fck";
    clocks = <0x08 0xc3 0x01>;
    power-domains = <0x07 0xc3 0x01>;
    phandle = <0x57>;
    };

    i2c@42120000 {
    compatible = "ti,j721e-i2c\0ti,omap4-i2c";
    reg = <0x00 0x42120000 0x00 0x100>;
    interrupts = <0x00 0x380 0x04>;
    #address-cells = <0x01>;
    #size-cells = <0x00>;
    clock-names = "fck";
    clocks = <0x08 0xc5 0x01>;
    power-domains = <0x07 0xc5 0x00>;
    phandle = <0x58>;
    };

    syscon@47000000 {
    compatible = "syscon\0simple-mfd";
    reg = <0x00 0x47000000 0x00 0x100>;
    #address-cells = <0x02>;
    #size-cells = <0x02>;
    ranges;
    phandle = <0x59>;

    hbmc-mux {
    compatible = "mmio-mux";
    #mux-control-cells = <0x01>;
    mux-reg-masks = <0x04 0x02>;
    phandle = <0x13>;
    };

    hyperbus@47034000 {
    compatible = "ti,am654-hbmc";
    reg = <0x00 0x47034000 0x00 0x100 0x05 0x00 0x01 0x00>;
    power-domains = <0x07 0x66 0x01>;
    clocks = <0x08 0x66 0x00>;
    assigned-clocks = <0x08 0x66 0x05>;
    assigned-clock-rates = <0x13de4355>;
    #address-cells = <0x02>;
    #size-cells = <0x01>;
    mux-controls = <0x13 0x00>;
    status = "disabled";
    pinctrl-names = "default";
    pinctrl-0 = <0x14>;
    ranges = <0x00 0x00 0x05 0x00 0x4000000 0x01 0x00 0x05 0x4000000 0x800000>;
    phandle = <0x5a>;

    flash@0,0 {
    compatible = "cypress,hyperflash\0cfi-flash";
    reg = <0x00 0x00 0x4000000>;

    partitions {
    compatible = "fixed-partitions";
    #address-cells = <0x01>;
    #size-cells = <0x01>;

    partition@0 {
    label = "hbmc.tiboot3";
    reg = <0x00 0x100000>;
    };

    partition@100000 {
    label = "hbmc.tispl";
    reg = <0x100000 0x200000>;
    };

    partition@300000 {
    label = "hbmc.u-boot";
    reg = <0x300000 0x400000>;
    };

    partition@700000 {
    label = "hbmc.env";
    reg = <0x700000 0x40000>;
    };

    partition@800000 {
    label = "hbmc.rootfs";
    reg = <0x800000 0x3800000>;
    };
    };
    };
    };

    spi@47040000 {
    compatible = "ti,am654-ospi";
    reg = <0x00 0x47040000 0x00 0x100 0x05 0x00 0x01 0x00>;
    interrupts = <0x00 0x348 0x04>;
    cdns,fifo-depth = <0x100>;
    cdns,fifo-width = <0x04>;
    cdns,trigger-address = <0x00>;
    clocks = <0x08 0x67 0x00>;
    assigned-clocks = <0x08 0x67 0x00>;
    assigned-clock-parents = <0x08 0x67 0x02>;
    assigned-clock-rates = <0x9ef21aa>;
    power-domains = <0x07 0x67 0x01>;
    #address-cells = <0x01>;
    #size-cells = <0x00>;
    pinctrl-names = "default";
    pinctrl-0 = <0x15>;
    phandle = <0x5b>;

    flash@0 {
    compatible = "jedec,spi-nor";
    reg = <0x00>;
    spi-tx-bus-width = <0x08>;
    spi-rx-bus-width = <0x08>;
    spi-max-frequency = <0x17d7840>;
    cdns,tshsl-ns = <0x3c>;
    cdns,tsd2d-ns = <0x3c>;
    cdns,tchsh-ns = <0x3c>;
    cdns,tslch-ns = <0x3c>;
    cdns,read-delay = <0x04>;
    #address-cells = <0x01>;
    #size-cells = <0x01>;

    partitions {
    compatible = "fixed-partitions";
    #address-cells = <0x01>;
    #size-cells = <0x01>;

    partition@0 {
    label = "ospi.tiboot3";
    reg = <0x00 0x100000>;
    };

    partition@100000 {
    label = "ospi.tispl";
    reg = <0x100000 0x200000>;
    };

    partition@300000 {
    label = "ospi.u-boot";
    reg = <0x300000 0x400000>;
    };

    partition@700000 {
    label = "ospi.env";
    reg = <0x700000 0x40000>;
    };

    partition@740000 {
    label = "ospi.env.backup";
    reg = <0x740000 0x40000>;
    };

    partition@800000 {
    label = "ospi.rootfs";
    reg = <0x800000 0x37c0000>;
    };

    partition@3fc0000 {
    label = "ospi.phypattern";
    reg = <0x3fc0000 0x40000>;
    };
    };
    };
    };
    };

    tscadc@40200000 {
    compatible = "ti,am3359-tscadc";
    reg = <0x00 0x40200000 0x00 0x1000>;
    interrupts = <0x00 0x35c 0x04>;
    power-domains = <0x07 0x00 0x01>;
    clocks = <0x08 0x00 0x01>;
    assigned-clocks = <0x08 0x00 0x03>;
    assigned-clock-rates = <0x3938700>;
    clock-names = "adc_tsc_fck";
    dmas = <0x16 0x7400 0x16 0x7401>;
    dma-names = "fifo0\0fifo1";
    phandle = <0x5c>;

    adc {
    #io-channel-cells = <0x01>;
    compatible = "ti,am3359-adc";
    ti,adc-channels = <0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07>;
    };
    };

    can@40528000 {
    compatible = "bosch,m_can";
    reg = <0x00 0x40528000 0x00 0x200 0x00 0x40500000 0x00 0x8000>;
    reg-names = "m_can\0message_ram";
    power-domains = <0x07 0xac 0x01>;
    clocks = <0x08 0xac 0x02 0x08 0xac 0x00>;
    clock-names = "cclk\0hclk";
    interrupts = <0x00 0x340 0x04 0x00 0x341 0x04>;
    interrupt-names = "int0\0int1";
    bosch,mram-cfg = <0x00 0x00 0x00 0x20 0x00 0x00 0x01 0x01>;
    status = "okay";
    pinctrl-names = "default";
    pinctrl-0 = <0x17 0x18>;
    stb-gpios = <0x19 0x36 0x00>;
    en-gpios = <0x19 0x00 0x00>;
    phandle = <0x5d>;

    can-transceiver {
    max-bitrate = <0x4c4b40>;
    };
    };

    can@40568000 {
    compatible = "bosch,m_can";
    reg = <0x00 0x40568000 0x00 0x200 0x00 0x40540000 0x00 0x8000>;
    reg-names = "m_can\0message_ram";
    power-domains = <0x07 0xad 0x01>;
    clocks = <0x08 0xad 0x02 0x08 0xad 0x00>;
    clock-names = "cclk\0hclk";
    interrupts = <0x00 0x343 0x04 0x00 0x344 0x04>;
    interrupt-names = "int0\0int1";
    bosch,mram-cfg = <0x00 0x00 0x00 0x20 0x00 0x00 0x01 0x01>;
    status = "okay";
    pinctrl-names = "default";
    pinctrl-0 = <0x1a 0x1b>;
    stb-gpios = <0x19 0x02 0x01>;
    phandle = <0x5e>;

    can-transceiver {
    max-bitrate = <0x4c4b40>;
    };
    };

    r5fss@41000000 {
    compatible = "ti,j7200-r5fss";
    ti,cluster-mode = <0x01>;
    #address-cells = <0x01>;
    #size-cells = <0x01>;
    ranges = <0x41000000 0x00 0x41000000 0x20000 0x41400000 0x00 0x41400000 0x20000>;
    power-domains = <0x07 0xf9 0x01>;
    phandle = <0x5f>;

    r5f@41000000 {
    compatible = "ti,j7200-r5f";
    reg = <0x41000000 0x10000 0x41010000 0x10000>;
    reg-names = "atcm\0btcm";
    ti,sci = <0x09>;
    ti,sci-dev-id = <0xfa>;
    ti,sci-proc-ids = <0x01 0xff>;
    resets = <0x1c 0xfa 0x01>;
    firmware-name = "j7200-mcu-r5f0_0-fw";
    ti,atcm-enable = <0x01>;
    ti,btcm-enable = <0x01>;
    ti,loczrama = <0x01>;
    mboxes = <0x1d 0x1e>;
    memory-region = <0x1f 0x20>;
    phandle = <0x60>;
    };

    r5f@41400000 {
    compatible = "ti,j7200-r5f";
    reg = <0x41400000 0x8000 0x41410000 0x8000>;
    reg-names = "atcm\0btcm";
    ti,sci = <0x09>;
    ti,sci-dev-id = <0xfb>;
    ti,sci-proc-ids = <0x02 0xff>;
    resets = <0x1c 0xfb 0x01>;
    firmware-name = "j7200-mcu-r5f0_1-fw";
    ti,atcm-enable = <0x01>;
    ti,btcm-enable = <0x01>;
    ti,loczrama = <0x01>;
    mboxes = <0x1d 0x21>;
    memory-region = <0x22 0x23>;
    phandle = <0x61>;
    };
    };

    crypto@40900000 {
    compatible = "ti,j721e-sa2ul";
    reg = <0x00 0x40900000 0x00 0x1200>;
    power-domains = <0x07 0x109 0x00>;
    #address-cells = <0x02>;
    #size-cells = <0x02>;
    ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>;
    dmas = <0x0d 0xf501 0x0d 0x7502 0x0d 0x7503>;
    dma-names = "tx\0rx1\0rx2";
    dma-coherent;
    phandle = <0x62>;

    rng@40910000 {
    compatible = "inside-secure,safexcel-eip76";
    reg = <0x00 0x40910000 0x00 0x7d>;
    interrupts = <0x00 0x3b1 0x04>;
    clocks = <0x08 0x109 0x01>;
    status = "disabled";
    phandle = <0x63>;
    };
    };

    temperature-sensor@42040000 {
    compatible = "ti,j7200-vtm";
    reg = <0x00 0x42040000 0x00 0x350 0x00 0x42050000 0x00 0x350 0x00 0x43000300 0x00 0x10>;
    power-domains = <0x07 0x9a 0x01>;
    #thermal-sensor-cells = <0x01>;
    phandle = <0x40>;
    };
    };

    sram@70000000 {
    compatible = "mmio-sram";
    reg = <0x00 0x70000000 0x00 0x100000>;
    #address-cells = <0x01>;
    #size-cells = <0x01>;
    ranges = <0x00 0x00 0x70000000 0x100000>;
    phandle = <0x64>;

    atf-sram@0 {
    reg = <0x00 0x20000>;
    };
    };

    scm-conf@100000 {
    compatible = "ti,j721e-system-controller\0syscon\0simple-mfd";
    reg = <0x00 0x100000 0x00 0x1c000>;
    #address-cells = <0x01>;
    #size-cells = <0x01>;
    ranges = <0x00 0x00 0x100000 0x1c000>;
    phandle = <0x30>;

    mux-controller@4080 {
    compatible = "mmio-mux";
    #mux-control-cells = <0x01>;
    mux-reg-masks = <0x4080 0x03 0x4084 0x03 0x4088 0x03 0x408c 0x03>;
    idle-states = <0x01 0x01 0x00 0x03>;
    phandle = <0x65>;
    };

    phy@4044 {
    compatible = "ti,j7200-cpsw5g-phy-gmii-sel";
    ti,qsgmii-main-ports = <0x01>;
    reg = <0x4044 0x10>;
    #phy-cells = <0x01>;
    phandle = <0x66>;
    };

    mux-controller@4000 {
    compatible = "mmio-mux";
    #mux-control-cells = <0x01>;
    mux-reg-masks = <0x4000 0x8000000>;
    idle-states = <0x01>;
    phandle = <0x67>;
    };
    };

    interrupt-controller@1800000 {
    compatible = "arm,gic-v3";
    #address-cells = <0x02>;
    #size-cells = <0x02>;
    ranges;
    #interrupt-cells = <0x03>;
    interrupt-controller;
    reg = <0x00 0x1800000 0x00 0x10000 0x00 0x1900000 0x00 0x100000 0x00 0x6f000000 0x00 0x2000 0x00 0x6f010000 0x00 0x1000 0x00 0x6f020000 0x00 0x2000>;
    interrupts = <0x01 0x09 0x04>;
    phandle = <0x01>;

    msi-controller@1820000 {
    compatible = "arm,gic-v3-its";
    reg = <0x00 0x1820000 0x00 0x10000>;
    socionext,synquacer-pre-its = <0x1000000 0x400000>;
    msi-controller;
    #msi-cells = <0x01>;
    phandle = <0x31>;
    };
    };

    interrupt-controller0 {
    compatible = "ti,sci-intr";
    ti,intr-trigger-type = <0x01>;
    interrupt-controller;
    interrupt-parent = <0x01>;
    #interrupt-cells = <0x01>;
    ti,sci = <0x09>;
    ti,sci-dev-id = <0x83>;
    ti,interrupt-ranges = <0x08 0x188 0x38>;
    phandle = <0x36>;
    };

    bus@30000000 {
    compatible = "simple-mfd";
    #address-cells = <0x02>;
    #size-cells = <0x02>;
    ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0xc400000>;
    ti,sci-dev-id = <0xc7>;
    dma-coherent;
    dma-ranges;
    phandle = <0x68>;

    interrupt-controller1 {
    compatible = "ti,sci-intr";
    ti,intr-trigger-type = <0x04>;
    interrupt-controller;
    interrupt-parent = <0x01>;
    #interrupt-cells = <0x01>;
    ti,sci = <0x09>;
    ti,sci-dev-id = <0xd5>;
    ti,interrupt-ranges = <0x00 0x40 0x40 0x40 0x1c0 0x40 0x80 0x2a0 0x40>;
    phandle = <0x24>;
    };

    msi-controller@33d00000 {
    compatible = "ti,sci-inta";
    reg = <0x00 0x33d00000 0x00 0x100000>;
    interrupt-controller;
    #interrupt-cells = <0x00>;
    interrupt-parent = <0x24>;
    msi-controller;
    ti,sci = <0x09>;
    ti,sci-dev-id = <0xd1>;
    ti,interrupt-ranges = <0x00 0x00 0x100>;
    phandle = <0x0b>;
    };

    mailbox@32c00000 {
    compatible = "ti,am654-secure-proxy";
    #mbox-cells = <0x01>;
    reg-names = "target_data\0rt\0scfg";
    reg = <0x00 0x32c00000 0x00 0x100000 0x00 0x32400000 0x00 0x100000 0x00 0x32800000 0x00 0x100000>;
    interrupt-names = "rx_011";
    interrupts = <0x00 0x25 0x04>;
    phandle = <0x06>;
    };

    spinlock@30e00000 {
    compatible = "ti,am654-hwspinlock";
    reg = <0x00 0x30e00000 0x00 0x1000>;
    #hwlock-cells = <0x01>;
    phandle = <0x69>;
    };

    mailbox@31f80000 {
    compatible = "ti,am654-mailbox";
    reg = <0x00 0x31f80000 0x00 0x200>;
    #mbox-cells = <0x01>;
    ti,mbox-num-users = <0x04>;
    ti,mbox-num-fifos = <0x10>;
    interrupt-parent = <0x24>;
    interrupts = <0x1b4>;
    phandle = <0x1d>;

    mbox-mcu-r5fss0-core0 {
    ti,mbox-rx = <0x00 0x00 0x00>;
    ti,mbox-tx = <0x01 0x00 0x00>;
    phandle = <0x1e>;
    };

    mbox-mcu-r5fss0-core1 {
    ti,mbox-rx = <0x02 0x00 0x00>;
    ti,mbox-tx = <0x03 0x00 0x00>;
    phandle = <0x21>;
    };
    };

    mailbox@31f81000 {
    compatible = "ti,am654-mailbox";
    reg = <0x00 0x31f81000 0x00 0x200>;
    #mbox-cells = <0x01>;
    ti,mbox-num-users = <0x04>;
    ti,mbox-num-fifos = <0x10>;
    interrupt-parent = <0x24>;
    interrupts = <0x1b0>;
    phandle = <0x37>;

    mbox-main-r5fss0-core0 {
    ti,mbox-rx = <0x00 0x00 0x00>;
    ti,mbox-tx = <0x01 0x00 0x00>;
    phandle = <0x38>;
    };

    mbox-main-r5fss0-core1 {
    ti,mbox-rx = <0x02 0x00 0x00>;
    ti,mbox-tx = <0x03 0x00 0x00>;
    phandle = <0x3d>;
    };
    };

    mailbox@31f82000 {
    compatible = "ti,am654-mailbox";
    reg = <0x00 0x31f82000 0x00 0x200>;
    #mbox-cells = <0x01>;
    ti,mbox-num-users = <0x04>;
    ti,mbox-num-fifos = <0x10>;
    interrupt-parent = <0x24>;
    status = "disabled";
    phandle = <0x6a>;
    };

    mailbox@31f83000 {
    compatible = "ti,am654-mailbox";
    reg = <0x00 0x31f83000 0x00 0x200>;
    #mbox-cells = <0x01>;
    ti,mbox-num-users = <0x04>;
    ti,mbox-num-fifos = <0x10>;
    interrupt-parent = <0x24>;
    status = "disabled";
    phandle = <0x6b>;
    };

    mailbox@31f84000 {
    compatible = "ti,am654-mailbox";
    reg = <0x00 0x31f84000 0x00 0x200>;
    #mbox-cells = <0x01>;
    ti,mbox-num-users = <0x04>;
    ti,mbox-num-fifos = <0x10>;
    interrupt-parent = <0x24>;
    status = "disabled";
    phandle = <0x6c>;
    };

    mailbox@31f85000 {
    compatible = "ti,am654-mailbox";
    reg = <0x00 0x31f85000 0x00 0x200>;
    #mbox-cells = <0x01>;
    ti,mbox-num-users = <0x04>;
    ti,mbox-num-fifos = <0x10>;
    interrupt-parent = <0x24>;
    status = "disabled";
    phandle = <0x6d>;
    };

    mailbox@31f86000 {
    compatible = "ti,am654-mailbox";
    reg = <0x00 0x31f86000 0x00 0x200>;
    #mbox-cells = <0x01>;
    ti,mbox-num-users = <0x04>;
    ti,mbox-num-fifos = <0x10>;
    interrupt-parent = <0x24>;
    status = "disabled";
    phandle = <0x6e>;
    };

    mailbox@31f87000 {
    compatible = "ti,am654-mailbox";
    reg = <0x00 0x31f87000 0x00 0x200>;
    #mbox-cells = <0x01>;
    ti,mbox-num-users = <0x04>;
    ti,mbox-num-fifos = <0x10>;
    interrupt-parent = <0x24>;
    status = "disabled";
    phandle = <0x6f>;
    };

    mailbox@31f88000 {
    compatible = "ti,am654-mailbox";
    reg = <0x00 0x31f88000 0x00 0x200>;
    #mbox-cells = <0x01>;
    ti,mbox-num-users = <0x04>;
    ti,mbox-num-fifos = <0x10>;
    interrupt-parent = <0x24>;
    status = "disabled";
    phandle = <0x70>;
    };

    mailbox@31f89000 {
    compatible = "ti,am654-mailbox";
    reg = <0x00 0x31f89000 0x00 0x200>;
    #mbox-cells = <0x01>;
    ti,mbox-num-users = <0x04>;
    ti,mbox-num-fifos = <0x10>;
    interrupt-parent = <0x24>;
    status = "disabled";
    phandle = <0x71>;
    };

    mailbox@31f8a000 {
    compatible = "ti,am654-mailbox";
    reg = <0x00 0x31f8a000 0x00 0x200>;
    #mbox-cells = <0x01>;
    ti,mbox-num-users = <0x04>;
    ti,mbox-num-fifos = <0x10>;
    interrupt-parent = <0x24>;
    status = "disabled";
    phandle = <0x72>;
    };

    mailbox@31f8b000 {
    compatible = "ti,am654-mailbox";
    reg = <0x00 0x31f8b000 0x00 0x200>;
    #mbox-cells = <0x01>;
    ti,mbox-num-users = <0x04>;
    ti,mbox-num-fifos = <0x10>;
    interrupt-parent = <0x24>;
    status = "disabled";
    phandle = <0x73>;
    };

    ringacc@3c000000 {
    compatible = "ti,am654-navss-ringacc";
    reg = <0x00 0x3c000000 0x00 0x400000 0x00 0x38000000 0x00 0x400000 0x00 0x31120000 0x00 0x100 0x00 0x33000000 0x00 0x40000>;
    reg-names = "rt\0fifos\0proxy_gcfg\0proxy_target";
    ti,num-rings = <0x400>;
    ti,sci-rm-range-gp-rings = <0x01>;
    ti,sci = <0x09>;
    ti,sci-dev-id = <0xd3>;
    msi-parent = <0x0b>;
    phandle = <0x25>;
    };

    dma-controller@31150000 {
    compatible = "ti,j721e-navss-main-udmap";
    reg = <0x00 0x31150000 0x00 0x100 0x00 0x34000000 0x00 0x100000 0x00 0x35000000 0x00 0x100000>;
    reg-names = "gcfg\0rchanrt\0tchanrt";
    msi-parent = <0x0b>;
    #dma-cells = <0x01>;
    ti,sci = <0x09>;
    ti,sci-dev-id = <0xd4>;
    ti,ringacc = <0x25>;
    ti,sci-rm-range-tchan = <0x0d 0x0f 0x10>;
    ti,sci-rm-range-rchan = <0x0a 0x0b 0x0c>;
    ti,sci-rm-range-rflow = <0x00>;
    phandle = <0x16>;
    };

    cpts@310d0000 {
    compatible = "ti,j721e-cpts";
    reg = <0x00 0x310d0000 0x00 0x400>;
    reg-names = "cpts";
    clocks = <0x08 0xc9 0x01>;
    clock-names = "cpts";
    interrupts-extended = <0x24 0x187>;
    interrupt-names = "cpts";
    ti,cpts-periodic-outputs = <0x06>;
    ti,cpts-ext-ts-inputs = <0x08>;
    };
    };

    ethernet@c000000 {
    compatible = "ti,j7200-cpswxg-nuss";
    #address-cells = <0x02>;
    #size-cells = <0x02>;
    reg = <0x00 0xc000000 0x00 0x200000>;
    reg-names = "cpsw_nuss";
    ranges = <0x00 0x00 0x00 0xc000000 0x00 0x200000>;
    clocks = <0x08 0x13 0x21>;
    clock-names = "fck";
    power-domains = <0x07 0x13 0x01>;
    dmas = <0x16 0xca00 0x16 0xca01 0x16 0xca02 0x16 0xca03 0x16 0xca04 0x16 0xca05 0x16 0xca06 0x16 0xca07 0x16 0x4a00>;
    dma-names = "tx0\0tx1\0tx2\0tx3\0tx4\0tx5\0tx6\0tx7\0rx";
    status = "disabled";
    phandle = <0x74>;

    ethernet-ports {
    #address-cells = <0x01>;
    #size-cells = <0x00>;

    port@1 {
    reg = <0x01>;
    ti,mac-only;
    label = "port1";
    phandle = <0x75>;
    };

    port@2 {
    reg = <0x02>;
    ti,mac-only;
    label = "port2";
    phandle = <0x76>;
    };

    port@3 {
    reg = <0x03>;
    ti,mac-only;
    label = "port3";
    phandle = <0x77>;
    };

    port@4 {
    reg = <0x04>;
    ti,mac-only;
    label = "port4";
    phandle = <0x78>;
    };
    };

    mdio@f00 {
    compatible = "ti,cpsw-mdio\0ti,davinci_mdio";
    reg = <0x00 0xf00 0x00 0x100>;
    #address-cells = <0x01>;
    #size-cells = <0x00>;
    clocks = <0x08 0x13 0x21>;
    clock-names = "fck";
    bus_freq = <0xf4240>;
    phandle = <0x79>;
    };

    cpts@3d000 {
    compatible = "ti,j721e-cpts";
    reg = <0x00 0x3d000 0x00 0x400>;
    clocks = <0x08 0x13 0x10>;
    clock-names = "cpts";
    interrupts-extended = <0x01 0x00 0x10 0x04>;
    interrupt-names = "cpts";
    ti,cpts-ext-ts-inputs = <0x04>;
    ti,cpts-periodic-outputs = <0x02>;
    };
    };

    pinctrl@11c000 {
    compatible = "pinctrl-single";
    reg = <0x00 0x11c000 0x00 0x2b4>;
    #pinctrl-cells = <0x01>;
    pinctrl-single,register-width = <0x20>;
    pinctrl-single,function-mask = <0xffffffff>;
    phandle = <0x7a>;

    main-i2c0-pins-default {
    pinctrl-single,pins = <0xd4 0x60000 0xd8 0x60000>;
    phandle = <0x26>;
    };

    main-i2c1-pins-default {
    pinctrl-single,pins = <0xdc 0x60003 0xe0 0x60003>;
    phandle = <0x27>;
    };

    main-mmc1-pins-default {
    pinctrl-single,pins = <0x104 0x50000 0x100 0x50000 0xfc 0x50000 0xf8 0x50000 0xf4 0x50000 0xf0 0x50000 0xec 0x50000 0xe4 0x50008>;
    phandle = <0x28>;
    };

    main-usbss0-pins-default {
    pinctrl-single,pins = <0x120 0x10000>;
    phandle = <0x35>;
    };

    vdd-sd-dv-pins-default {
    pinctrl-single,pins = <0xd0 0x10007>;
    phandle = <0x44>;
    };
    };

    serial@2800000 {
    compatible = "ti,j721e-uart\0ti,am654-uart";
    reg = <0x00 0x2800000 0x00 0x100>;
    reg-shift = <0x02>;
    reg-io-width = <0x04>;
    interrupts = <0x00 0xc0 0x04>;
    clock-frequency = <0x2dc6c00>;
    current-speed = <0x1c200>;
    power-domains = <0x07 0x92 0x00>;
    clocks = <0x08 0x92 0x02>;
    clock-names = "fclk";
    phandle = <0x7b>;
    };

    serial@2810000 {
    compatible = "ti,j721e-uart\0ti,am654-uart";
    reg = <0x00 0x2810000 0x00 0x100>;
    reg-shift = <0x02>;
    reg-io-width = <0x04>;
    interrupts = <0x00 0xc1 0x04>;
    clock-frequency = <0x2dc6c00>;
    current-speed = <0x1c200>;
    power-domains = <0x07 0x116 0x01>;
    clocks = <0x08 0x116 0x02>;
    clock-names = "fclk";
    phandle = <0x7c>;
    };

    serial@2820000 {
    compatible = "ti,j721e-uart\0ti,am654-uart";
    reg = <0x00 0x2820000 0x00 0x100>;
    reg-shift = <0x02>;
    reg-io-width = <0x04>;
    interrupts = <0x00 0xc2 0x04>;
    clock-frequency = <0x2dc6c00>;
    current-speed = <0x1c200>;
    power-domains = <0x07 0x117 0x01>;
    clocks = <0x08 0x117 0x02>;
    clock-names = "fclk";
    status = "reserved";
    phandle = <0x7d>;
    };

    serial@2830000 {
    compatible = "ti,j721e-uart\0ti,am654-uart";
    reg = <0x00 0x2830000 0x00 0x100>;
    reg-shift = <0x02>;
    reg-io-width = <0x04>;
    interrupts = <0x00 0xc3 0x04>;
    clock-frequency = <0x2dc6c00>;
    current-speed = <0x1c200>;
    power-domains = <0x07 0x118 0x01>;
    clocks = <0x08 0x118 0x02>;
    clock-names = "fclk";
    status = "disabled";
    phandle = <0x7e>;
    };

    serial@2840000 {
    compatible = "ti,j721e-uart\0ti,am654-uart";
    reg = <0x00 0x2840000 0x00 0x100>;
    reg-shift = <0x02>;
    reg-io-width = <0x04>;
    interrupts = <0x00 0xc4 0x04>;
    clock-frequency = <0x2dc6c00>;
    current-speed = <0x1c200>;
    power-domains = <0x07 0x119 0x01>;
    clocks = <0x08 0x119 0x02>;
    clock-names = "fclk";
    status = "disabled";
    phandle = <0x7f>;
    };

    serial@2850000 {
    compatible = "ti,j721e-uart\0ti,am654-uart";
    reg = <0x00 0x2850000 0x00 0x100>;
    reg-shift = <0x02>;
    reg-io-width = <0x04>;
    interrupts = <0x00 0xc5 0x04>;
    clock-frequency = <0x2dc6c00>;
    current-speed = <0x1c200>;
    power-domains = <0x07 0x11a 0x01>;
    clocks = <0x08 0x11a 0x02>;
    clock-names = "fclk";
    status = "disabled";
    phandle = <0x80>;
    };

    serial@2860000 {
    compatible = "ti,j721e-uart\0ti,am654-uart";
    reg = <0x00 0x2860000 0x00 0x100>;
    reg-shift = <0x02>;
    reg-io-width = <0x04>;
    interrupts = <0x00 0xc6 0x04>;
    clock-frequency = <0x2dc6c00>;
    current-speed = <0x1c200>;
    power-domains = <0x07 0x11b 0x01>;
    clocks = <0x08 0x11b 0x02>;
    clock-names = "fclk";
    status = "disabled";
    phandle = <0x81>;
    };

    serial@2870000 {
    compatible = "ti,j721e-uart\0ti,am654-uart";
    reg = <0x00 0x2870000 0x00 0x100>;
    reg-shift = <0x02>;
    reg-io-width = <0x04>;
    interrupts = <0x00 0xc7 0x04>;
    clock-frequency = <0x2dc6c00>;
    current-speed = <0x1c200>;
    power-domains = <0x07 0x11c 0x01>;
    clocks = <0x08 0x11c 0x02>;
    clock-names = "fclk";
    status = "disabled";
    phandle = <0x82>;
    };

    serial@2880000 {
    compatible = "ti,j721e-uart\0ti,am654-uart";
    reg = <0x00 0x2880000 0x00 0x100>;
    reg-shift = <0x02>;
    reg-io-width = <0x04>;
    interrupts = <0x00 0xf8 0x04>;
    clock-frequency = <0x2dc6c00>;
    current-speed = <0x1c200>;
    power-domains = <0x07 0x11d 0x01>;
    clocks = <0x08 0x11d 0x02>;
    clock-names = "fclk";
    status = "disabled";
    phandle = <0x83>;
    };

    serial@2890000 {
    compatible = "ti,j721e-uart\0ti,am654-uart";
    reg = <0x00 0x2890000 0x00 0x100>;
    reg-shift = <0x02>;
    reg-io-width = <0x04>;
    interrupts = <0x00 0xf9 0x04>;
    clock-frequency = <0x2dc6c00>;
    current-speed = <0x1c200>;
    power-domains = <0x07 0x11e 0x01>;
    clocks = <0x08 0x11e 0x02>;
    clock-names = "fclk";
    status = "disabled";
    phandle = <0x84>;
    };

    i2c@2000000 {
    compatible = "ti,j721e-i2c\0ti,omap4-i2c";
    reg = <0x00 0x2000000 0x00 0x100>;
    interrupts = <0x00 0xc8 0x04>;
    #address-cells = <0x01>;
    #size-cells = <0x00>;
    clock-names = "fck";
    clocks = <0x08 0xbb 0x01>;
    power-domains = <0x07 0xbb 0x00>;
    pinctrl-names = "default";
    pinctrl-0 = <0x26>;
    clock-frequency = <0x61a80>;
    phandle = <0x85>;

    gpio@21 {
    compatible = "ti,tca6408";
    reg = <0x21>;
    gpio-controller;
    #gpio-cells = <0x02>;
    gpio-line-names = "USB2.0_MUX_SEL\0CANUART_MUX1_SEL0\0CANUART_MUX2_SEL0\0CANUART_MUX_SEL1\0UART/LIN_MUX_SEL\0TRC_D17/AUDIO_REFCLK_SEL\0GPIO_LIN_EN\0CAN_STB";
    phandle = <0x86>;

    usb_hub@0 {
    gpio-hog;
    gpios = <0x00 0x00>;
    output-high;
    line-name = "USB2.0_MUX_SEL";
    };
    };

    gpio@20 {
    compatible = "ti,tca6416";
    reg = <0x20>;
    gpio-controller;
    #gpio-cells = <0x02>;
    phandle = <0x33>;
    };

    gpio@22 {
    compatible = "ti,tca6424";
    reg = <0x22>;
    gpio-controller;
    #gpio-cells = <0x02>;
    phandle = <0x43>;
    };
    };

    i2c@2010000 {
    compatible = "ti,j721e-i2c\0ti,omap4-i2c";
    reg = <0x00 0x2010000 0x00 0x100>;
    interrupts = <0x00 0xc9 0x04>;
    #address-cells = <0x01>;
    #size-cells = <0x00>;
    clock-names = "fck";
    clocks = <0x08 0xbc 0x01>;
    power-domains = <0x07 0xbc 0x01>;
    pinctrl-names = "default";
    pinctrl-0 = <0x27>;
    clock-frequency = <0x61a80>;
    phandle = <0x87>;

    gpio@20 {
    compatible = "ti,tca6408";
    reg = <0x20>;
    gpio-controller;
    #gpio-cells = <0x02>;
    gpio-line-names = "CODEC_RSTz\0CODEC_SPARE1\0UB926_RESETn\0UB926_LOCK\0UB926_PWR_SW_CNTRL\0UB926_TUNER_RESET\0UB926_GPIO_SPARE\0";
    phandle = <0x88>;
    };
    };

    i2c@2020000 {
    compatible = "ti,j721e-i2c\0ti,omap4-i2c";
    reg = <0x00 0x2020000 0x00 0x100>;
    interrupts = <0x00 0xca 0x04>;
    #address-cells = <0x01>;
    #size-cells = <0x00>;
    clock-names = "fck";
    clocks = <0x08 0xbd 0x01>;
    power-domains = <0x07 0xbd 0x01>;
    phandle = <0x89>;
    };

    i2c@2030000 {
    compatible = "ti,j721e-i2c\0ti,omap4-i2c";
    reg = <0x00 0x2030000 0x00 0x100>;
    interrupts = <0x00 0xcb 0x04>;
    #address-cells = <0x01>;
    #size-cells = <0x00>;
    clock-names = "fck";
    clocks = <0x08 0xbe 0x01>;
    power-domains = <0x07 0xbe 0x01>;
    phandle = <0x8a>;
    };

    i2c@2040000 {
    compatible = "ti,j721e-i2c\0ti,omap4-i2c";
    reg = <0x00 0x2040000 0x00 0x100>;
    interrupts = <0x00 0xcc 0x04>;
    #address-cells = <0x01>;
    #size-cells = <0x00>;
    clock-names = "fck";
    clocks = <0x08 0xbf 0x01>;
    power-domains = <0x07 0xbf 0x01>;
    phandle = <0x8b>;
    };

    i2c@2050000 {
    compatible = "ti,j721e-i2c\0ti,omap4-i2c";
    reg = <0x00 0x2050000 0x00 0x100>;
    interrupts = <0x00 0xcd 0x04>;
    #address-cells = <0x01>;
    #size-cells = <0x00>;
    clock-names = "fck";
    clocks = <0x08 0xc0 0x01>;
    power-domains = <0x07 0xc0 0x01>;
    phandle = <0x8c>;
    };

    i2c@2060000 {
    compatible = "ti,j721e-i2c\0ti,omap4-i2c";
    reg = <0x00 0x2060000 0x00 0x100>;
    interrupts = <0x00 0xce 0x04>;
    #address-cells = <0x01>;
    #size-cells = <0x00>;
    clock-names = "fck";
    clocks = <0x08 0xc1 0x01>;
    power-domains = <0x07 0xc1 0x01>;
    phandle = <0x8d>;
    };

    watchdog@2200000 {
    compatible = "ti,j7-rti-wdt";
    reg = <0x00 0x2200000 0x00 0x100>;
    clocks = <0x08 0xfc 0x01>;
    power-domains = <0x07 0xfc 0x01>;
    assigned-clocks = <0x08 0xfc 0x01>;
    assigned-clock-parents = <0x08 0xfc 0x05>;
    phandle = <0x8e>;
    };

    watchdog@2210000 {
    compatible = "ti,j7-rti-wdt";
    reg = <0x00 0x2210000 0x00 0x100>;
    clocks = <0x08 0xfd 0x01>;
    power-domains = <0x07 0xfd 0x01>;
    assigned-clocks = <0x08 0xfd 0x01>;
    assigned-clock-parents = <0x08 0xfd 0x05>;
    phandle = <0x8f>;
    };

    mmc@4f80000 {
    compatible = "ti,j7200-sdhci-8bit\0ti,j721e-sdhci-8bit";
    reg = <0x00 0x4f80000 0x00 0x260 0x00 0x4f88000 0x00 0x134>;
    interrupts = <0x00 0x03 0x04>;
    power-domains = <0x07 0x5b 0x01>;
    clock-names = "clk_ahb\0clk_xin";
    clocks = <0x08 0x5b 0x00 0x08 0x5b 0x03>;
    ti,otap-del-sel-legacy = <0x00>;
    ti,otap-del-sel-mmc-hs = <0x00>;
    ti,otap-del-sel-ddr52 = <0x06>;
    ti,otap-del-sel-hs200 = <0x08>;
    ti,otap-del-sel-hs400 = <0x05>;
    ti,itap-del-sel-legacy = <0x10>;
    ti,itap-del-sel-mmc-hs = <0x0a>;
    ti,strobe-sel = <0x77>;
    ti,clkbuf-sel = <0x07>;
    ti,trm-icp = <0x08>;
    bus-width = <0x08>;
    mmc-ddr-1_8v;
    mmc-hs200-1_8v;
    mmc-hs400-1_8v;
    dma-coherent;
    non-removable;
    ti,driver-strength-ohm = <0x32>;
    disable-wp;
    phandle = <0x90>;
    };

    mmc@4fb0000 {
    compatible = "ti,j7200-sdhci-4bit\0ti,j721e-sdhci-4bit";
    reg = <0x00 0x4fb0000 0x00 0x260 0x00 0x4fb8000 0x00 0x134>;
    interrupts = <0x00 0x04 0x04>;
    power-domains = <0x07 0x5c 0x01>;
    clock-names = "clk_ahb\0clk_xin";
    clocks = <0x08 0x5c 0x01 0x08 0x5c 0x02>;
    ti,otap-del-sel-legacy = <0x00>;
    ti,otap-del-sel-sd-hs = <0x00>;
    ti,otap-del-sel-sdr12 = <0x0f>;
    ti,otap-del-sel-sdr25 = <0x0f>;
    ti,otap-del-sel-sdr50 = <0x0c>;
    ti,otap-del-sel-sdr104 = <0x05>;
    ti,otap-del-sel-ddr50 = <0x0c>;
    ti,itap-del-sel-legacy = <0x00>;
    ti,itap-del-sel-sd-hs = <0x00>;
    ti,itap-del-sel-sdr12 = <0x00>;
    ti,itap-del-sel-sdr25 = <0x00>;
    ti,clkbuf-sel = <0x07>;
    ti,trm-icp = <0x08>;
    dma-coherent;
    pinctrl-0 = <0x28>;
    pinctrl-names = "default";
    vmmc-supply = <0x29>;
    vqmmc-supply = <0x2a>;
    ti,driver-strength-ohm = <0x32>;
    disable-wp;
    phandle = <0x91>;
    };

    wiz@5060000 {
    compatible = "ti,j721e-wiz-10g";
    #address-cells = <0x01>;
    #size-cells = <0x01>;
    power-domains = <0x07 0x124 0x01>;
    clocks = <0x08 0x124 0x0b 0x08 0x124 0x55 0x2b>;
    clock-names = "fck\0core_ref_clk\0ext_ref_clk";
    num-lanes = <0x04>;
    #reset-cells = <0x01>;
    ranges = <0x5060000 0x00 0x5060000 0x10000>;
    assigned-clocks = <0x08 0x124 0x55>;
    assigned-clock-parents = <0x08 0x124 0x59>;
    phandle = <0x2f>;

    pll0-refclk {
    clocks = <0x08 0x124 0x55 0x2b>;
    clock-output-names = "wiz0_pll0_refclk";
    #clock-cells = <0x00>;
    assigned-clocks = <0x2c>;
    assigned-clock-parents = <0x08 0x124 0x55>;
    phandle = <0x2c>;
    };

    pll1-refclk {
    clocks = <0x08 0x124 0x55 0x2b>;
    clock-output-names = "wiz0_pll1_refclk";
    #clock-cells = <0x00>;
    assigned-clocks = <0x2d>;
    assigned-clock-parents = <0x08 0x124 0x55>;
    phandle = <0x2d>;
    };

    refclk-dig {
    clocks = <0x08 0x124 0x55 0x2b>;
    clock-output-names = "wiz0_refclk_dig";
    #clock-cells = <0x00>;
    assigned-clocks = <0x2e>;
    assigned-clock-parents = <0x08 0x124 0x55>;
    phandle = <0x2e>;
    };

    cmn-refclk-dig-div {
    clocks = <0x2e>;
    #clock-cells = <0x00>;
    phandle = <0x92>;
    };

    serdes@5060000 {
    compatible = "ti,j721e-serdes-10g";
    reg = <0x5060000 0x10000>;
    reg-names = "torrent_phy";
    resets = <0x2f 0x00>;
    reset-names = "torrent_reset";
    clocks = <0x2c>;
    clock-names = "refclk";
    #address-cells = <0x01>;
    #size-cells = <0x00>;
    phandle = <0x93>;

    phy@0 {
    reg = <0x00>;
    cdns,num-lanes = <0x02>;
    #phy-cells = <0x00>;
    cdns,phy-type = <0x02>;
    resets = <0x2f 0x01 0x2f 0x02>;
    phandle = <0x34>;
    };

    phy@1 {
    reg = <0x02>;
    cdns,num-lanes = <0x01>;
    #phy-cells = <0x00>;
    cdns,phy-type = <0x09>;
    resets = <0x2f 0x03>;
    phandle = <0x94>;
    };
    };
    };

    pcie@2910000 {
    compatible = "ti,j7200-pcie-host\0ti,j721e-pcie-host";
    reg = <0x00 0x2910000 0x00 0x1000 0x00 0x2917000 0x00 0x400 0x00 0xd800000 0x00 0x800000 0x00 0x18000000 0x00 0x1000>;
    reg-names = "intd_cfg\0user_cfg\0reg\0cfg";
    interrupt-names = "link_state";
    interrupts = <0x00 0x14a 0x01>;
    device_type = "pci";
    ti,syscon-pcie-ctrl = <0x30 0x4074>;
    max-link-speed = <0x03>;
    num-lanes = <0x02>;
    power-domains = <0x07 0xf0 0x01>;
    clocks = <0x08 0xf0 0x06>;
    clock-names = "fck";
    #address-cells = <0x03>;
    #size-cells = <0x02>;
    bus-range = <0x00 0x0f>;
    cdns,no-bar-match-nbits = <0x40>;
    vendor-id = <0x104c>;
    device-id = <0xb00f>;
    msi-map = <0x00 0x31 0x00 0x10000>;
    dma-coherent;
    ranges = <0x1000000 0x00 0x18001000 0x00 0x18001000 0x00 0x10000 0x2000000 0x00 0x18011000 0x00 0x18011000 0x00 0x7fef000>;
    dma-ranges = <0x2000000 0x00 0x00 0x00 0x00 0x10000 0x00>;
    #interrupt-cells = <0x01>;
    interrupt-map-mask = <0x00 0x00 0x00 0x07>;
    interrupt-map = <0x00 0x00 0x00 0x01 0x32 0x00 0x00 0x00 0x00 0x02 0x32 0x00 0x00 0x00 0x00 0x03 0x32 0x00 0x00 0x00 0x00 0x04 0x32 0x00>;
    reset-gpios = <0x33 0x02 0x00>;
    phys = <0x34>;
    phy-names = "pcie-phy";
    phandle = <0x95>;

    interrupt-controller {
    interrupt-controller;
    #interrupt-cells = <0x02>;
    interrupt-parent = <0x01>;
    interrupts = <0x00 0x144 0x01>;
    phandle = <0x32>;
    };
    };

    pcie-ep@2910000 {
    compatible = "ti,j7200-pcie-ep\0ti,j721e-pcie-ep";
    reg = <0x00 0x2910000 0x00 0x1000 0x00 0x2917000 0x00 0x400 0x00 0xd800000 0x00 0x800000 0x00 0x18000000 0x00 0x8000000>;
    reg-names = "intd_cfg\0user_cfg\0reg\0mem";
    interrupt-names = "link_state";
    interrupts = <0x00 0x14a 0x01>;
    ti,syscon-pcie-ctrl = <0x30 0x4074>;
    max-link-speed = <0x03>;
    num-lanes = <0x02>;
    power-domains = <0x07 0xf0 0x01>;
    clocks = <0x08 0xf0 0x06>;
    clock-names = "fck";
    max-functions = [06];
    max-virtual-functions = [04 04 04 04 00 00];
    dma-coherent;
    phys = <0x34>;
    phy-names = "pcie-phy";
    status = "disabled";
    phandle = <0x96>;
    };

    cdns-usb@4104000 {
    compatible = "ti,j721e-usb";
    reg = <0x00 0x4104000 0x00 0x100>;
    dma-coherent;
    power-domains = <0x07 0x120 0x01>;
    clocks = <0x08 0x120 0x0c 0x08 0x120 0x03>;
    clock-names = "ref\0lpm";
    assigned-clocks = <0x08 0x120 0x0c>;
    assigned-clock-parents = <0x08 0x120 0x0d>;
    #address-cells = <0x02>;
    #size-cells = <0x02>;
    ranges;
    pinctrl-names = "default";
    pinctrl-0 = <0x35>;
    ti,vbus-divider;
    ti,usb2-only;
    phandle = <0x97>;

    usb@6000000 {
    compatible = "cdns,usb3";
    reg = <0x00 0x6000000 0x00 0x10000 0x00 0x6010000 0x00 0x10000 0x00 0x6020000 0x00 0x10000>;
    reg-names = "otg\0xhci\0dev";
    interrupts = <0x00 0x60 0x04 0x00 0x66 0x04 0x00 0x78 0x04>;
    interrupt-names = "host\0peripheral\0otg";
    maximum-speed = "high-speed";
    dr_mode = "otg";
    cdns,phyrst-a-enable;
    phandle = <0x98>;
    };
    };

    gpio@600000 {
    compatible = "ti,j721e-gpio\0ti,keystone-gpio";
    reg = <0x00 0x600000 0x00 0x100>;
    gpio-controller;
    #gpio-cells = <0x02>;
    interrupt-parent = <0x36>;
    interrupts = <0x91 0x92 0x93 0x94 0x95>;
    interrupt-controller;
    #interrupt-cells = <0x02>;
    #address-cells = <0x00>;
    ti,ngpio = <0x45>;
    ti,davinci-gpio-unbanked = <0x00>;
    power-domains = <0x07 0x69 0x01>;
    clocks = <0x08 0x69 0x00>;
    clock-names = "gpio";
    phandle = <0x46>;
    };

    gpio@610000 {
    compatible = "ti,j721e-gpio\0ti,keystone-gpio";
    reg = <0x00 0x610000 0x00 0x100>;
    gpio-controller;
    #gpio-cells = <0x02>;
    interrupt-parent = <0x36>;
    interrupts = <0x9a 0x9b 0x9c 0x9d 0x9e>;
    interrupt-controller;
    #interrupt-cells = <0x02>;
    #address-cells = <0x00>;
    ti,ngpio = <0x45>;
    ti,davinci-gpio-unbanked = <0x00>;
    power-domains = <0x07 0x6b 0x01>;
    clocks = <0x08 0x6b 0x00>;
    clock-names = "gpio";
    status = "disabled";
    phandle = <0x99>;
    };

    gpio@620000 {
    compatible = "ti,j721e-gpio\0ti,keystone-gpio";
    reg = <0x00 0x620000 0x00 0x100>;
    gpio-controller;
    #gpio-cells = <0x02>;
    interrupt-parent = <0x36>;
    interrupts = <0xa3 0xa4 0xa5 0xa6 0xa7>;
    interrupt-controller;
    #interrupt-cells = <0x02>;
    #address-cells = <0x00>;
    ti,ngpio = <0x45>;
    ti,davinci-gpio-unbanked = <0x00>;
    power-domains = <0x07 0x6d 0x01>;
    clocks = <0x08 0x6d 0x00>;
    clock-names = "gpio";
    status = "disabled";
    phandle = <0x9a>;
    };

    gpio@630000 {
    compatible = "ti,j721e-gpio\0ti,keystone-gpio";
    reg = <0x00 0x630000 0x00 0x100>;
    gpio-controller;
    #gpio-cells = <0x02>;
    interrupt-parent = <0x36>;
    interrupts = <0xac 0xad 0xae 0xaf 0xb0>;
    interrupt-controller;
    #interrupt-cells = <0x02>;
    #address-cells = <0x00>;
    ti,ngpio = <0x45>;
    ti,davinci-gpio-unbanked = <0x00>;
    power-domains = <0x07 0x6f 0x01>;
    clocks = <0x08 0x6f 0x00>;
    clock-names = "gpio";
    status = "disabled";
    phandle = <0x9b>;
    };

    r5fss@5c00000 {
    compatible = "ti,j7200-r5fss";
    ti,cluster-mode = <0x00>;
    #address-cells = <0x01>;
    #size-cells = <0x01>;
    ranges = <0x5c00000 0x00 0x5c00000 0x20000 0x5d00000 0x00 0x5d00000 0x20000>;
    power-domains = <0x07 0xf3 0x01>;
    phandle = <0x9c>;

    r5f@5c00000 {
    compatible = "ti,j7200-r5f";
    reg = <0x5c00000 0x10000 0x5c10000 0x10000>;
    reg-names = "atcm\0btcm";
    ti,sci = <0x09>;
    ti,sci-dev-id = <0xf5>;
    ti,sci-proc-ids = <0x06 0xff>;
    resets = <0x1c 0xf5 0x01>;
    firmware-name = "j7200-main-r5f0_0-fw";
    ti,atcm-enable = <0x01>;
    ti,btcm-enable = <0x01>;
    ti,loczrama = <0x01>;
    mboxes = <0x37 0x38>;
    memory-region = <0x39 0x3a 0x3b 0x3c>;
    phandle = <0x9d>;
    };

    r5f@5d00000 {
    compatible = "ti,j7200-r5f";
    reg = <0x5d00000 0x8000 0x5d10000 0x8000>;
    reg-names = "atcm\0btcm";
    ti,sci = <0x09>;
    ti,sci-dev-id = <0xf6>;
    ti,sci-proc-ids = <0x07 0xff>;
    resets = <0x1c 0xf6 0x01>;
    firmware-name = "j7200-main-r5f0_1-fw";
    ti,atcm-enable = <0x01>;
    ti,btcm-enable = <0x01>;
    ti,loczrama = <0x01>;
    mboxes = <0x37 0x3d>;
    memory-region = <0x3e 0x3f>;
    phandle = <0x9e>;
    };
    };

    timesync_router@a40000 {
    compatible = "pinctrl-single";
    reg = <0x00 0xa40000 0x00 0x800>;
    #address-cells = <0x01>;
    #size-cells = <0x00>;
    #pinctrl-cells = <0x01>;
    pinctrl-single,register-width = <0x20>;
    pinctrl-single,function-mask = <0x107ff>;
    status = "disabled";
    phandle = <0x9f>;
    };
    };

    thermal-zones {
    phandle = <0xa0>;

    mcu-thermal {
    polling-delay-passive = <0xfa>;
    polling-delay = <0x1f4>;
    thermal-sensors = <0x40 0x00>;
    phandle = <0xa1>;

    trips {

    wkup-crit {
    temperature = <0x1e848>;
    hysteresis = <0x7d0>;
    type = "critical";
    phandle = <0xa2>;
    };
    };
    };

    mpu-thermal {
    polling-delay-passive = <0xfa>;
    polling-delay = <0x1f4>;
    thermal-sensors = <0x40 0x01>;
    phandle = <0xa3>;

    trips {

    mpu-crit {
    temperature = <0x1e848>;
    hysteresis = <0x7d0>;
    type = "critical";
    phandle = <0xa4>;
    };
    };
    };

    main-thermal {
    polling-delay-passive = <0xfa>;
    polling-delay = <0x1f4>;
    thermal-sensors = <0x40 0x02>;
    phandle = <0xa5>;

    trips {

    c7x-crit {
    temperature = <0x1e848>;
    hysteresis = <0x7d0>;
    type = "critical";
    phandle = <0xa6>;
    };
    };
    };
    };

    serdes-refclk {
    #clock-cells = <0x00>;
    compatible = "fixed-clock";
    clock-frequency = <0x5f5e100>;
    phandle = <0x2b>;
    };

    memory@80000000 {
    device_type = "memory";
    reg = <0x00 0x80000000 0x00 0x80000000 0x08 0x80000000 0x00 0x80000000>;
    };

    reserved-memory {
    #address-cells = <0x02>;
    #size-cells = <0x02>;
    ranges;
    phandle = <0xa7>;

    optee@9e800000 {
    reg = <0x00 0x9e800000 0x00 0x1800000>;
    alignment = <0x1000>;
    no-map;
    phandle = <0xa8>;
    };

    r5f-dma-memory@a0000000 {
    compatible = "shared-dma-pool";
    reg = <0x00 0xa0000000 0x00 0x100000>;
    no-map;
    phandle = <0x1f>;
    };

    r5f-memory@a0100000 {
    compatible = "shared-dma-pool";
    reg = <0x00 0xa0100000 0x00 0xf00000>;
    no-map;
    phandle = <0x20>;
    };

    r5f-dma-memory@a1000000 {
    compatible = "shared-dma-pool";
    reg = <0x00 0xa1000000 0x00 0x100000>;
    no-map;
    phandle = <0x22>;
    };

    r5f-memory@a1100000 {
    compatible = "shared-dma-pool";
    reg = <0x00 0xa1100000 0x00 0xf00000>;
    no-map;
    phandle = <0x23>;
    };

    r5f-dma-memory@a2000000 {
    compatible = "shared-dma-pool";
    reg = <0x00 0xa2000000 0x00 0x100000>;
    no-map;
    phandle = <0x39>;
    };

    r5f-memory@a2100000 {
    compatible = "shared-dma-pool";
    reg = <0x00 0xa2100000 0x00 0xf00000>;
    no-map;
    phandle = <0x3a>;
    };

    r5f-dma-memory@a3000000 {
    compatible = "shared-dma-pool";
    reg = <0x00 0xa3000000 0x00 0x100000>;
    no-map;
    phandle = <0x3e>;
    };

    r5f-memory@a3100000 {
    compatible = "shared-dma-pool";
    reg = <0x00 0xa3100000 0x00 0xf00000>;
    no-map;
    phandle = <0x3f>;
    };

    ipc-memories@a4000000 {
    reg = <0x00 0xa4000000 0x00 0x800000>;
    alignment = <0x1000>;
    no-map;
    phandle = <0xa9>;
    };

    r5f-virtual-eth-queues@a5000000 {
    compatible = "shared-dma-pool";
    reg = <0x00 0xa5000000 0x00 0x200000>;
    no-map;
    phandle = <0x3b>;
    };

    r5f-virtual-eth-buffers@a5200000 {
    compatible = "shared-dma-pool";
    reg = <0x00 0xa5200000 0x00 0x1e00000>;
    no-map;
    phandle = <0x3c>;
    };
    };

    main_r5fss_cpsw5g_virt_mac0 {
    compatible = "ti,j721e-cpsw-virt-mac";
    dma-coherent;
    ti,psil-base = <0x4a00>;
    ti,remote-name = "mpu_1_0_ethswitch-device-0";
    dmas = <0x16 0xca00 0x16 0xca01 0x16 0xca02 0x16 0xca03 0x16 0xca04 0x16 0xca05 0x16 0xca06 0x16 0xca07 0x16 0x4a00>;
    dma-names = "tx0\0tx1\0tx2\0tx3\0tx4\0tx5\0tx6\0tx7\0rx";
    phandle = <0xaa>;

    virt_emac_port {
    ti,label = "virt-port";
    };
    };

    main-r5fss-cpsw9g-virt-mac1 {
    compatible = "ti,j721e-cpsw-virt-mac";
    dma-coherent;
    ti,psil-base = <0x4a00>;
    ti,remote-name = "mpu_1_0_ethmac-device-1";
    dmas = <0x16 0xca00 0x16 0xca01 0x16 0xca02 0x16 0xca03 0x16 0xca04 0x16 0xca05 0x16 0xca06 0x16 0xca07 0x16 0x4a00>;
    dma-names = "tx0\0tx1\0tx2\0tx3\0tx4\0tx5\0tx6\0tx7\0rx";
    phandle = <0xab>;

    virt_emac_port {
    ti,label = "virt-port";
    };
    };

    fixedregulator-evm12v0 {
    compatible = "regulator-fixed";
    regulator-name = "evm_12v0";
    regulator-min-microvolt = <0xb71b00>;
    regulator-max-microvolt = <0xb71b00>;
    regulator-always-on;
    regulator-boot-on;
    phandle = <0x41>;
    };

    fixedregulator-vsys3v3 {
    compatible = "regulator-fixed";
    regulator-name = "vsys_3v3";
    regulator-min-microvolt = <0x325aa0>;
    regulator-max-microvolt = <0x325aa0>;
    vin-supply = <0x41>;
    regulator-always-on;
    regulator-boot-on;
    phandle = <0x42>;
    };

    fixedregulator-vsys5v0 {
    compatible = "regulator-fixed";
    regulator-name = "vsys_5v0";
    regulator-min-microvolt = <0x4c4b40>;
    regulator-max-microvolt = <0x4c4b40>;
    vin-supply = <0x41>;
    regulator-always-on;
    regulator-boot-on;
    phandle = <0x45>;
    };

    fixedregulator-sd {
    compatible = "regulator-fixed";
    regulator-name = "vdd_mmc1";
    regulator-min-microvolt = <0x325aa0>;
    regulator-max-microvolt = <0x325aa0>;
    regulator-boot-on;
    enable-active-high;
    vin-supply = <0x42>;
    gpio = <0x43 0x02 0x00>;
    phandle = <0x29>;
    };

    gpio-regulator-TLV71033 {
    compatible = "regulator-gpio";
    regulator-name = "tlv71033";
    pinctrl-names = "default";
    pinctrl-0 = <0x44>;
    regulator-min-microvolt = <0x1b7740>;
    regulator-max-microvolt = <0x325aa0>;
    regulator-boot-on;
    vin-supply = <0x45>;
    gpios = <0x46 0x37 0x00>;
    states = <0x1b7740 0x00 0x325aa0 0x01>;
    phandle = <0x2a>;
    };

    __symbols__ {
    cluster0 = "/cpus/cpu-map/cluster0";
    cpu0 = "/cpus/cpu@0";
    cpu1 = "/cpus/cpu@1";
    L2_0 = "/l2-cache0";
    msmc_l3 = "/l3-cache0";
    psci = "/firmware/psci";
    a72_timer0 = "/timer-cl0-cpu0";
    pmu = "/pmu";
    cbass_main = "/bus@100000";
    cbass_mcu_wakeup = "/bus@100000/bus@28380000";
    dmsc = "/bus@100000/bus@28380000/dmsc@44083000";
    k3_pds = "/bus@100000/bus@28380000/dmsc@44083000/power-controller";
    k3_clks = "/bus@100000/bus@28380000/dmsc@44083000/clocks";
    k3_reset = "/bus@100000/bus@28380000/dmsc@44083000/reset-controller";
    mcu_conf = "/bus@100000/bus@28380000/syscon@40f00000";
    phy_gmii_sel = "/bus@100000/bus@28380000/syscon@40f00000/phy@4040";
    wkup_pmx0 = "/bus@100000/bus@28380000/pinctrl@4301c000";
    mcu_fss0_hpb0_pins_default = "/bus@100000/bus@28380000/pinctrl@4301c000/mcu-fss0-hpb0-pins-default";
    mcu_fss0_ospi0_pins_default = "/bus@100000/bus@28380000/pinctrl@4301c000/mcu-fss0-ospi0-pins-default";
    mcu_cpsw_pins_default = "/bus@100000/bus@28380000/pinctrl@4301c000/mcu-cpsw-pins-default";
    mcu_mdio_pins_default = "/bus@100000/bus@28380000/pinctrl@4301c000/mcu-mdio1-pins-default";
    mcu_mcan0_pins_default = "/bus@100000/bus@28380000/pinctrl@4301c000/mcu-mcan0-pins-default";
    mcu_mcan0_gpio_pins_default = "/bus@100000/bus@28380000/pinctrl@4301c000/mcu-mcan0-gpio-pins-default";
    mcu_mcan1_pins_default = "/bus@100000/bus@28380000/pinctrl@4301c000/mcu-mcan1-pins-default";
    mcu_mcan1_gpio_pins_default = "/bus@100000/bus@28380000/pinctrl@4301c000/mcu-mcan1-gpio-pins-default";
    mcu_ram = "/bus@100000/bus@28380000/sram@41c00000";
    wkup_uart0 = "/bus@100000/bus@28380000/serial@42300000";
    mcu_uart0 = "/bus@100000/bus@28380000/serial@40a00000";
    wkup_gpio_intr = "/bus@100000/bus@28380000/interrupt-controller2";
    wkup_gpio0 = "/bus@100000/bus@28380000/gpio@42110000";
    wkup_gpio1 = "/bus@100000/bus@28380000/gpio@42100000";
    mcu_navss = "/bus@100000/bus@28380000/bus@28380000";
    mcu_ringacc = "/bus@100000/bus@28380000/bus@28380000/ringacc@2b800000";
    mcu_udmap = "/bus@100000/bus@28380000/bus@28380000/dma-controller@285c0000";
    mcu_cpsw = "/bus@100000/bus@28380000/ethernet@46000000";
    cpsw_port1 = "/bus@100000/bus@28380000/ethernet@46000000/ethernet-ports/port@1";
    davinci_mdio = "/bus@100000/bus@28380000/ethernet@46000000/mdio@f00";
    phy0 = "/bus@100000/bus@28380000/ethernet@46000000/mdio@f00/ethernet-phy@0";
    mcu_i2c0 = "/bus@100000/bus@28380000/i2c@40b00000";
    mcu_i2c1 = "/bus@100000/bus@28380000/i2c@40b10000";
    wkup_i2c0 = "/bus@100000/bus@28380000/i2c@42120000";
    fss = "/bus@100000/bus@28380000/syscon@47000000";
    hbmc_mux = "/bus@100000/bus@28380000/syscon@47000000/hbmc-mux";
    hbmc = "/bus@100000/bus@28380000/syscon@47000000/hyperbus@47034000";
    ospi0 = "/bus@100000/bus@28380000/syscon@47000000/spi@47040000";
    tscadc0 = "/bus@100000/bus@28380000/tscadc@40200000";
    mcu_mcan0 = "/bus@100000/bus@28380000/can@40528000";
    mcu_mcan1 = "/bus@100000/bus@28380000/can@40568000";
    mcu_r5fss0 = "/bus@100000/bus@28380000/r5fss@41000000";
    mcu_r5fss0_core0 = "/bus@100000/bus@28380000/r5fss@41000000/r5f@41000000";
    mcu_r5fss0_core1 = "/bus@100000/bus@28380000/r5fss@41000000/r5f@41400000";
    mcu_crypto = "/bus@100000/bus@28380000/crypto@40900000";
    rng = "/bus@100000/bus@28380000/crypto@40900000/rng@40910000";
    wkup_vtm0 = "/bus@100000/bus@28380000/temperature-sensor@42040000";
    msmc_ram = "/bus@100000/sram@70000000";
    scm_conf = "/bus@100000/scm-conf@100000";
    serdes_ln_ctrl = "/bus@100000/scm-conf@100000/mux-controller@4080";
    cpsw0_phy_gmii_sel = "/bus@100000/scm-conf@100000/phy@4044";
    usb_serdes_mux = "/bus@100000/scm-conf@100000/mux-controller@4000";
    gic500 = "/bus@100000/interrupt-controller@1800000";
    gic_its = "/bus@100000/interrupt-controller@1800000/msi-controller@1820000";
    main_gpio_intr = "/bus@100000/interrupt-controller0";
    main_navss = "/bus@100000/bus@30000000";
    main_navss_intr = "/bus@100000/bus@30000000/interrupt-controller1";
    main_udmass_inta = "/bus@100000/bus@30000000/msi-controller@33d00000";
    secure_proxy_main = "/bus@100000/bus@30000000/mailbox@32c00000";
    hwspinlock = "/bus@100000/bus@30000000/spinlock@30e00000";
    mailbox0_cluster0 = "/bus@100000/bus@30000000/mailbox@31f80000";
    mbox_mcu_r5fss0_core0 = "/bus@100000/bus@30000000/mailbox@31f80000/mbox-mcu-r5fss0-core0";
    mbox_mcu_r5fss0_core1 = "/bus@100000/bus@30000000/mailbox@31f80000/mbox-mcu-r5fss0-core1";
    mailbox0_cluster1 = "/bus@100000/bus@30000000/mailbox@31f81000";
    mbox_main_r5fss0_core0 = "/bus@100000/bus@30000000/mailbox@31f81000/mbox-main-r5fss0-core0";
    mbox_main_r5fss0_core1 = "/bus@100000/bus@30000000/mailbox@31f81000/mbox-main-r5fss0-core1";
    mailbox0_cluster2 = "/bus@100000/bus@30000000/mailbox@31f82000";
    mailbox0_cluster3 = "/bus@100000/bus@30000000/mailbox@31f83000";
    mailbox0_cluster4 = "/bus@100000/bus@30000000/mailbox@31f84000";
    mailbox0_cluster5 = "/bus@100000/bus@30000000/mailbox@31f85000";
    mailbox0_cluster6 = "/bus@100000/bus@30000000/mailbox@31f86000";
    mailbox0_cluster7 = "/bus@100000/bus@30000000/mailbox@31f87000";
    mailbox0_cluster8 = "/bus@100000/bus@30000000/mailbox@31f88000";
    mailbox0_cluster9 = "/bus@100000/bus@30000000/mailbox@31f89000";
    mailbox0_cluster10 = "/bus@100000/bus@30000000/mailbox@31f8a000";
    mailbox0_cluster11 = "/bus@100000/bus@30000000/mailbox@31f8b000";
    main_ringacc = "/bus@100000/bus@30000000/ringacc@3c000000";
    main_udmap = "/bus@100000/bus@30000000/dma-controller@31150000";
    cpsw0 = "/bus@100000/ethernet@c000000";
    cpsw0_port1 = "/bus@100000/ethernet@c000000/ethernet-ports/port@1";
    cpsw0_port2 = "/bus@100000/ethernet@c000000/ethernet-ports/port@2";
    cpsw0_port3 = "/bus@100000/ethernet@c000000/ethernet-ports/port@3";
    cpsw0_port4 = "/bus@100000/ethernet@c000000/ethernet-ports/port@4";
    cpsw5g_mdio = "/bus@100000/ethernet@c000000/mdio@f00";
    main_pmx0 = "/bus@100000/pinctrl@11c000";
    main_i2c0_pins_default = "/bus@100000/pinctrl@11c000/main-i2c0-pins-default";
    main_i2c1_pins_default = "/bus@100000/pinctrl@11c000/main-i2c1-pins-default";
    main_mmc1_pins_default = "/bus@100000/pinctrl@11c000/main-mmc1-pins-default";
    main_usbss0_pins_default = "/bus@100000/pinctrl@11c000/main-usbss0-pins-default";
    vdd_sd_dv_pins_default = "/bus@100000/pinctrl@11c000/vdd-sd-dv-pins-default";
    main_uart0 = "/bus@100000/serial@2800000";
    main_uart1 = "/bus@100000/serial@2810000";
    main_uart2 = "/bus@100000/serial@2820000";
    main_uart3 = "/bus@100000/serial@2830000";
    main_uart4 = "/bus@100000/serial@2840000";
    main_uart5 = "/bus@100000/serial@2850000";
    main_uart6 = "/bus@100000/serial@2860000";
    main_uart7 = "/bus@100000/serial@2870000";
    main_uart8 = "/bus@100000/serial@2880000";
    main_uart9 = "/bus@100000/serial@2890000";
    main_i2c0 = "/bus@100000/i2c@2000000";
    exp_som = "/bus@100000/i2c@2000000/gpio@21";
    exp1 = "/bus@100000/i2c@2000000/gpio@20";
    exp2 = "/bus@100000/i2c@2000000/gpio@22";
    main_i2c1 = "/bus@100000/i2c@2010000";
    exp3 = "/bus@100000/i2c@2010000/gpio@20";
    main_i2c2 = "/bus@100000/i2c@2020000";
    main_i2c3 = "/bus@100000/i2c@2030000";
    main_i2c4 = "/bus@100000/i2c@2040000";
    main_i2c5 = "/bus@100000/i2c@2050000";
    main_i2c6 = "/bus@100000/i2c@2060000";
    main_rti0 = "/bus@100000/watchdog@2200000";
    main_rti1 = "/bus@100000/watchdog@2210000";
    main_sdhci0 = "/bus@100000/mmc@4f80000";
    main_sdhci1 = "/bus@100000/mmc@4fb0000";
    serdes_wiz0 = "/bus@100000/wiz@5060000";
    wiz0_pll0_refclk = "/bus@100000/wiz@5060000/pll0-refclk";
    wiz0_pll1_refclk = "/bus@100000/wiz@5060000/pll1-refclk";
    wiz0_refclk_dig = "/bus@100000/wiz@5060000/refclk-dig";
    wiz0_cmn_refclk_dig_div = "/bus@100000/wiz@5060000/cmn-refclk-dig-div";
    serdes0 = "/bus@100000/wiz@5060000/serdes@5060000";
    serdes0_pcie_link = "/bus@100000/wiz@5060000/serdes@5060000/phy@0";
    serdes0_qsgmii_link = "/bus@100000/wiz@5060000/serdes@5060000/phy@1";
    pcie1_rc = "/bus@100000/pcie@2910000";
    pcie1_intc = "/bus@100000/pcie@2910000/interrupt-controller";
    pcie1_ep = "/bus@100000/pcie-ep@2910000";
    usbss0 = "/bus@100000/cdns-usb@4104000";
    usb0 = "/bus@100000/cdns-usb@4104000/usb@6000000";
    main_gpio0 = "/bus@100000/gpio@600000";
    main_gpio2 = "/bus@100000/gpio@610000";
    main_gpio4 = "/bus@100000/gpio@620000";
    main_gpio6 = "/bus@100000/gpio@630000";
    main_r5fss0 = "/bus@100000/r5fss@5c00000";
    main_r5fss0_core0 = "/bus@100000/r5fss@5c00000/r5f@5c00000";
    main_r5fss0_core1 = "/bus@100000/r5fss@5c00000/r5f@5d00000";
    timesync_router = "/bus@100000/timesync_router@a40000";
    thermal_zones = "/thermal-zones";
    mcu_thermal = "/thermal-zones/mcu-thermal";
    wkup_crit = "/thermal-zones/mcu-thermal/trips/wkup-crit";
    mpu_thermal = "/thermal-zones/mpu-thermal";
    mpu_crit = "/thermal-zones/mpu-thermal/trips/mpu-crit";
    main_thermal = "/thermal-zones/main-thermal";
    c7x_crit = "/thermal-zones/main-thermal/trips/c7x-crit";
    serdes_refclk = "/serdes-refclk";
    reserved_memory = "/reserved-memory";
    secure_ddr = "/reserved-memory/optee@9e800000";
    mcu_r5fss0_core0_dma_memory_region = "/reserved-memory/r5f-dma-memory@a0000000";
    mcu_r5fss0_core0_memory_region = "/reserved-memory/r5f-memory@a0100000";
    mcu_r5fss0_core1_dma_memory_region = "/reserved-memory/r5f-dma-memory@a1000000";
    mcu_r5fss0_core1_memory_region = "/reserved-memory/r5f-memory@a1100000";
    main_r5fss0_core0_dma_memory_region = "/reserved-memory/r5f-dma-memory@a2000000";
    main_r5fss0_core0_memory_region = "/reserved-memory/r5f-memory@a2100000";
    main_r5fss0_core1_dma_memory_region = "/reserved-memory/r5f-dma-memory@a3000000";
    main_r5fss0_core1_memory_region = "/reserved-memory/r5f-memory@a3100000";
    rtos_ipc_memory_region = "/reserved-memory/ipc-memories@a4000000";
    main_r5fss0_core0_shared_memory_queue_region = "/reserved-memory/r5f-virtual-eth-queues@a5000000";
    main_r5fss0_core0_shared_memory_bufpool_region = "/reserved-memory/r5f-virtual-eth-buffers@a5200000";
    cpsw5g_virt_mac = "/main_r5fss_cpsw5g_virt_mac0";
    cpsw9g_virt_maconly = "/main-r5fss-cpsw9g-virt-mac1";
    evm_12v0 = "/fixedregulator-evm12v0";
    vsys_3v3 = "/fixedregulator-vsys3v3";
    vsys_5v0 = "/fixedregulator-vsys5v0";
    vdd_mmc1 = "/fixedregulator-sd";
    vdd_sd_dv = "/gpio-regulator-TLV71033";
    };
    };

  • It is a CAN transmitting issue, If I do not send any can data, I can receive without error for as long as I want. 
    The moment I transmit a packet using the cansend command or one of my applications I see the bus restart message 

  • I have tried this on two different EVM and processor card combinations and it is the same on both

  • David,

    Can you make sure that the internal loopback mode is working fine? If there are issues with Pinmux or transceiver configuration then they should be masked in internal loopback mode. You can try internal loopback mode by adding "loopback on" to your command.

    ip link set can0 type can bitrate 1000000 dbitrate 5000000 fd on loopback on

    Regards

    Karan

  • Hi, Karan,

    In looback mode when sending:

    cansend can0 123#DEADBEEF 

    I do not see the CAN interface restarting.

    David

  • Any further information on this? 
    Can you give me a portion of the EVM schematic the explains the connection between J31, J34 and the TCAN1042-Q1 transceiver

  • David

    In looback mode when sending:

    cansend can0 123#DEADBEEF 

    I do not see the CAN interface restarting.

    Good, so internal loopback work.

    Can you give me a portion of the EVM schematic the explains the connection between J31, J34 and the TCAN1042-Q1 transceiver

    You can find the schematics under the section "Design files" in this page - https://www.ti.com/tool/J721EXCPXEVM 

    Download the  Common Processor Board Design Files (Rev. D) from here.

    Regards

    Karan

  • I was looking around and found this support forum entry:

    https://e2e.ti.com/support/processors-group/processors/f/processors-forum/993148/dra821u-linux-multiple-mcan-can-fd-peripheral-support

    I checked the patch that was provided and found one of the same issues: 

    diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
    index 1ae987c59..6e6117527 100644
    --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
    +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
    @@ -103,7 +103,7 @@
    mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-pins-default {
    pinctrl-single,pins = <
    J721E_WKUP_IOPAD(0xc0, PIN_INPUT, 7) /* (B18) WKUP_GPIO0_0 */
    - J721E_WKUP_IOPAD(0x98, PIN_INPUT, 7) /* (C9) MCU_MDIO0_MDIO.WKUP_GPIO0_54 */
    + J721E_WKUP_IOPAD(0xA8, PIN_INPUT, 7) /* (C9) MCU_MDIO0_MDIO.WKUP_GPIO0_58 */
    >;

    I corrected the pin definition and rebuilt the DTB file, once rebooted I found I now had both can0 and can1 available. I cannot get any data from can0 but can1 is receiving on connector J31, however I still get the bus restart if attempt  to transmit anything on that interface using:

    cansend can1 123#DEADBEEF

    This issue is the final issue I need to resolve before I can evaluate the processor for or next project.

    This is a high priority item for me and my company

     

  • David

    -1-

    Is this the correct summary?

    1. CAN0 is MCU_MCAN0 and CAN1 is MCU_MCAN1 on your setup?

    2. Internal loopback - CAN0 and CAN1 both work fine

    3. Rx - CAN0 doesn't work but CAN1 does

    4. Tx - None works?

    -2-

    Can you share the patch you use on the J7200 EVM?

    Regards

    Karan

  • 1 Yes ..CAN0 is MCU_MCAN0 and CAN1 is MCU_MCAN1 on my setup

    2 Yes ...Internal loopback - CAN0 and CAN1 both work fine

    3 Yes ...I can RX on can1 (J31).  I cannot RX on can0 (J30)

    4 Yes ...can1 restarts the bus anytime I attempt a TX, can0 does not restart the bus but I see nothing on the J30 connector

    The patches I had to manually patch (git am failed to apply)  used are:

    From 8eac2b3f5be611fd26db19f4a2f98ae84ec7e43e Mon Sep 17 00:00:00 2001
    From: Karan Saxena <karan@ti.com>
    Date: Thu, 15 Apr 2021 18:21:19 +0530
    Subject: [PATCH 2/2] arm: dts: ti: k3-j7200-common-proc-board: Add support for
    mcu_mcan nodes

    Signed-off-by: Karan Saxena <karan@ti.com>
    ---
    .../boot/dts/ti/k3-j7200-common-proc-board.dts | 48 ++++++++++++++++++++++
    1 file changed, 48 insertions(+)

    diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
    index 3ac2dab..d37ebc5 100644
    --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
    +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
    @@ -92,6 +92,33 @@
    J721E_WKUP_IOPAD(0x0098, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */
    >;
    };
    +
    + mcu_mcan0_pins_default: mcu-mcan0-pins-default {
    + pinctrl-single,pins = <
    + J721E_WKUP_IOPAD(0xbc, PIN_INPUT, 0) /* (A17) MCU_MCAN0_RX */
    + J721E_WKUP_IOPAD(0xb8, PIN_OUTPUT, 0) /* (A16) MCU_MCAN0_TX */
    + >;
    + };
    +
    + mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-pins-default {
    + pinctrl-single,pins = <
    + J721E_WKUP_IOPAD(0xc0, PIN_INPUT, 7) /* (B18) WKUP_GPIO0_0 */
    + J721E_WKUP_IOPAD(0xa8, PIN_INPUT, 7) /* (B17) MCU_SPI0_D1.WKUP_GPIO0_58 */
    + >;
    + };
    +
    + mcu_mcan1_pins_default: mcu-mcan1-pins-default {
    + pinctrl-single,pins = <
    + J721E_WKUP_IOPAD(0xd4, PIN_INPUT, 0) /* (B16) WKUP_GPIO0_5.MCU_MCAN1_RX */
    + J721E_WKUP_IOPAD(0xd0, PIN_OUTPUT, 0) /* (D13) WKUP_GPIO0_4.MCU_MCAN1_TX */
    + >;
    + };
    +
    + mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-pins-default {
    + pinctrl-single,pins = <
    + J721E_WKUP_IOPAD(0xc8, PIN_INPUT, 7) /* (D14) WKUP_GPIO0_2 */
    + >;
    + };
    };

    &main_pmx0 {
    @@ -428,3 +455,24 @@
    num-lanes = <2>;
    status = "disabled";
    };
    +
    +&mcu_mcan0 {
    + status = "okay";
    + pinctrl-names = "default";
    + pinctrl-0 = <&mcu_mcan0_pins_default &mcu_mcan0_gpio_pins_default>;
    + stb-gpios = <&wkup_gpio0 58 GPIO_ACTIVE_HIGH>;
    + en-gpios = <&wkup_gpio0 0 GPIO_ACTIVE_HIGH>;
    + can-transceiver {
    + max-bitrate = <5000000>;
    + };
    +};
    +
    +&mcu_mcan1 {
    + status = "okay";
    + pinctrl-names = "default";
    + pinctrl-0 = <&mcu_mcan1_pins_default &mcu_mcan1_gpio_pins_default>;
    + stb-gpios = <&wkup_gpio0 2 GPIO_ACTIVE_LOW>;
    + can-transceiver {
    + max-bitrate = <5000000>;
    + };
    +};
    --
    2.7.4

    and 

    From c42e1b4174681fb0fbe9f2c949f344b3c1b834fc Mon Sep 17 00:00:00 2001
    From: Karan Saxena <karan@ti.com>
    Date: Thu, 15 Apr 2021 18:20:30 +0530
    Subject: [PATCH 1/2] arm: dts: ti: k3-j7200-mcu-wakeup: Add support for
    mcu_mcan nodes

    Signed-off-by: Karan Saxena <karan@ti.com>
    ---
    arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 28 +++++++++++++++++++++++++
    1 file changed, 28 insertions(+)

    diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
    index 79289b6..fe76d11 100644
    --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
    +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
    @@ -402,4 +402,32 @@
    compatible = "ti,am3359-adc";
    };
    };
    +
    + mcu_mcan0: can@40528000 {
    + compatible = "bosch,m_can";
    + reg = <0x00 0x40528000 0x00 0x200>,
    + <0x00 0x40500000 0x00 0x8000>;
    + reg-names = "m_can", "message_ram";
    + power-domains = <&k3_pds 172 TI_SCI_PD_EXCLUSIVE>;
    + clocks = <&k3_clks 172 2>, <&k3_clks 172 0>;
    + clock-names = "cclk", "hclk";
    + interrupts = <GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>;
    + interrupt-names = "int0", "int1";
    + bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>;
    + };
    +
    + mcu_mcan1: can@40568000 {
    + compatible = "bosch,m_can";
    + reg = <0x00 0x40568000 0x00 0x200>,
    + <0x00 0x40540000 0x00 0x8000>;
    + reg-names = "m_can", "message_ram";
    + power-domains = <&k3_pds 173 TI_SCI_PD_EXCLUSIVE>;
    + clocks = <&k3_clks 173 2>, <&k3_clks 173 0>;
    + clock-names = "cclk", "hclk";
    + interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>;
    + interrupt-names = "int0", "int1";
    + bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>;
    + };
    };
    --
    2.7.4

     

  • Are there any further things you need me to try. I have been poking around and I cannot move further on my own. 

  • Hi David,

    While Karan is out of office, I have checked with the team member who worked on this 2 years ago.

    After applying the patches Karan shared in the other E2E thread you found, it was confirmed MCAN0/1 were both working with SDK 7.3.

    Would it possible for you to install SDK 7.3 and just apply the 2 patches for enabling MCAN and updating pinmux?

    This is most likely pinmux conflict in DTS file.

    Regards,
    Stanley

  • I downloaded the SDK 7.3 and applied the patches using the "git am" command, but I still see the bus restart on using cansend.

    One thing to note, along the way I have got two different sets of patch files. The files have the same names so I am not sure which is the correct version. I used the ones found in a zip file called "8080.vcl_can_patches.zip" found in 

    https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1000106/dra821u-linux-enable-main-domain-mcan-ports-on-gesi-board/3721677#3721677

    Please let me know if this is the correct set of patches

  • I have confirmed that the patches applied were the same as the patches supplied in:
    https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1000106/dra821u-linux-enable-main-domain-mcan-ports-on-gesi-board/3721677#3721677
    and include the additional changes indicated in the same support document above.

  • Can you send me your built and working dtb file to try  on my system?

  • Here is the patch for MCU MCAN. The other thread is for main domain MCAN which is not the MCAN instance you are trying.

    8054.vcl_can_patches.zip

  • Can you confirm which SDK version the patches are for?

  • these are exactly the same files as the previous  8080.vcl_can_patches with the changes indicated in https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1000106/dra821u-linux-enable-main-domain-mcan-ports-on-gesi-board/3721677#3721677 , I have implement the new ( same) files and the issues is the same.
    Once again, do you have a built and tested DTB I can run on my platform for confirmation.

    We seem to be going round in circles

  • Just for clarification this is how I am setting up my can interfaces:
    /sbin/ip link set can0 down
    /sbin/ip link set can0 up type can bitrate 62500 restart-ms 100
    /sbin/ip link set can1 down
    /sbin/ip link set can1 up type can bitrate 62500 restart-ms 100

  • We don't currently have a working setup.

    We are trying to revive it with the patch shared with you.

  • Hi David,

    I was able to get a working setup for can1 to send and receive on J7200 on SDK 7.3 version using the patches shared in the following post: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/993148/dra821u-linux-multiple-mcan-can-fd-peripheral-support/3694572#3694572

    However, it does seem like can0 has trouble transmitting/receiving, which we are currently working on debugging. On the other hand, we do not see bus restart on cansend for can1.

    Here are details about the set up that can be used as reference to check if there is a difference in commands/output/hardware connections for connection to can1.

    Terminal output on EVM (left) and PC (right) looks like so:

    History of commands to produce this output on EVM is:

    can_history

    Connection looks like so:

    White(leftmost)=CAN_High

    Gray(middle)=CAN_Ground

    Purple(rightmost)=CAN_Low

    Regards,

    Takuma

  • Hi David,

    Just confirmed CAN0 also works with the patches from the E2E referenced in my previous post with SDK version 7.3.

    Issue was that I was connecting to the wrong port. CAN0 is the 4-pin header J30, and CAN1 is the 3-pin header J31.

    When testing on your EVM, can I get a confirmation that the connection looks like the following when using CAN0:

    White=CAN_High

    Gray=CAN_Ground

    Purple=CAN_Low

    Last pin is unconnected

    Regards,

    Takuma

  • Hi David,

    From our meeting last week, we saw that the patches did not apply well to the latest release. Attached are the revised patches that works with the latest PSDK Linux 8.5 release:

    psdk_8_5_j7200_mcu_mcan_enable.zip

    The zip file includes both the patch to see what the actual changes are to the device tree, as well as the compiled dtb file that can be used to quickly test if the device tree changes are functional.

    Regards,

    Takuma

  • Thanks, I will give them a test