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AM3352: IBIS Simulation Issue

Part Number: AM3352

Hi Experts,

Our customer is facing differential clock problem in AM3352BZCZA100 IBIS when doing ddr3 batch simulation. Attached are the errors he is facing while simulation.


Also, where can he find the timing model for DDR3 in processor?

Thank you and best regards,
Gerald

  • Hello Gerald,

    Thank you for the query.

    where can he find the timing model for DDR3 in processor?

    We do not have the timing model that you could use. We reference customers to the datasheet that provides the DDR design including layout guidelines.

    ur customer is facing differential clock problem in AM3352BZCZA100 IBIS when doing ddr3 batch simulation

    Please provide additional details what you mean by block simulation and the tool used.

    Regards,

    Sreenivasa

  • Hi Sreenivasa,

    Please see below for our customer feedback:
    "
    The link provided by you is not at all referring to my question.
    I have problem with controller(AM3352BZCZA100) IBIS which is having inconsistency in differential clocks.
    For your reference i have attached the picture of the error that is thrown by the software."

    Thank you and best regards,
    Gerald

  • Hello Gerald,

    Thank you for the inputs.

    Can you please ask the customer to provide more details on the simulations being performed and also the tool being used.

    Regards,

    Sreenivasa

  • Hi Sreenivasa,

    The customer is trying to perform the DDRx batch simulation between AM3352BZCZA100 and IS43TR16128DL-125KBLI in Hyperlynx tool.

    But the tool is indicating that there is some inconsistency in the differential clocks of the AM3352BZCZA100 ibis.

    please find the attached photo to figure out the error.

    I have asked the customer multiple time but this is all he provides:
    4760.attachments.zip

    Regards,

  • Hello Gerald,

    Thank you for the inputs.

    Below are the recommendations i received from the simulation team that customer could try

    There are a couple of things that I recommend:

     

    1. Confirm that the customer is using the latest IBIS model. I believe for AM3352 (ZCZ) it is sprm552c.ibs
    2. In the above IBIS model, the data strobe P and N are defined by separate IO models for the P (Selector_1) and N (Selector_6) respectively. These are both derivatives of the same base IO model BCSHTLTCSCDDVPBFZ_SSDHV, which is why the tool likely interprets these as non-differential. This is valid IBIS syntax. The customer should work with their EDA vendor to define these as differential nets within the tool.

     

    |*****************************************************************************************

    |     Usage INPUT#1.35/1.5V/1.8V#X#X#BCSHTLTCSCDDVPBFZ_SSDHV.PADP

    |           OUTPUT#1.35/1.5V/1.8V#X#X#BCSHTLTCSCDDVPBFZ_SSDHV.TX_P

    |     Base model BCSHTLTCSCDDVPBFZ_SSDHV

    |*****************************************************************************************

    [Model Selector] Selector_1

     

    |*****************************************************************************************

    |     Usage INPUT#1.35/1.5V/1.8V#X#X#BCSHTLTCSCDDVPBFZ_SSDHV.PADN

    |           OUTPUT#1.35/1.5V/1.8V#X#X#BCSHTLTCSCDDVPBFZ_SSDHV.TX_N

    |     Base model BCSHTLTCSCDDVPBFZ_SSDHV

    |*****************************************************************************************

    [Model Selector] Selector_6

    Regards,

    Sreenivasa

  • Hi Sreenivasa,

    Customer said: yes, i am using a correct ibis which is downloaded from Ti website.

    Best regards,

    Gerald

  • Hello Gerald,

    Thank you for the inputs. and good to know.

    Helow is the other suggestion that i received that customer might have to look into.

    n the above IBIS model, the data strobe P and N are defined by separate IO models for the P (Selector_1) and N (Selector_6) respectively. These are both derivatives of the same base IO model BCSHTLTCSCDDVPBFZ_SSDHV, which is why the tool likely interprets these as non-differential. This is valid IBIS syntax. The customer should work with their EDA vendor to define these as differential nets within the tool.

    Can you please request customer to share the tool version and provide some additional explanation on the batch simulation being done.

    I can check if the simulation expert.

    Regards,

    Sreenivasa

  • Hello Gerald,

    Please refer below additional inputs i received.

    I am not clear what is meant here by “batch simulation”. Is this non-interactive mode where the simulation runs are submitted to a machine?

    In general, the behavior of an EDA tool in non-interactive mode can be tool specific and I would recommend the customer checking with their EDA vendor for any unexpected behavior of the tool.

    Can you please request customer to share the tool version and provide some additional explanation on the batch simulation being done.

    Regards,

    Sreenivasa

  • Hi Sreenivasa,

    Please see below information from customer:

    1. DDR Bactch simulation is nothing but simulating the controller and DDR connections through a software to know proper level of transmission is happening without fail by using PCB board file.
    2. I am using Hyperlynx Vx2.6 by mentor graphics tool for simulaitng DDR batch simulation.
    Regards,
    Gerald
  • Hello Gerald,

    Thank you for the inputs.

    Please refer below inputs i received from the simulation expert

    There should be nothing wrong with using batch simulation but as I mentioned, it is recommended to follow-up with the specific EDA tool vendor which is Mentor Graphics in this case, to enable the tool to interpret the differential nets correctly.

    I have rerun the ibis checker 5 on the model sprm552c.ibs and there are only warning messages and zero errors. So the IBIS syntax is valid.

    Regards,

    Sreenivasa