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Hi TI Experts,
I have the below queries regarding the I2C interface:
Let me know your thoughts.
Hi Board designers,
Refer below inputs for the I2C interface related queries.
1. Need information on the number of I2C interfaces available
The device contains six multicontroller Inter-Integrated Circuit (I2C) controllers. Each I2C controller was designed to be compliant to the Philips I2C-bus specification version 2.1. However, the device IOs are not fully compliant to the I2C electrical specification.
Open Drain buffer type I2C interface - I2C0 and MCU_I2C0
These I2C interfaces are Open drain type IOs. These I2C interfaces are fail-safe IO terminals.
The rise and fall times of the I2C signals connected to these ports must not exceed a slew rate of 0.8 V/ns (or 8E+7 V/s). This limit is more restrictive than the minimum fall time limits defined in the I2C specification. Therefore, it may be necessary to add additional capacitance to the I2C signals to slow the rise and fall times such that they do not exceed a slew rate of 0.8 V/ns.
Refer below
Reference: AM64 SK schematics
LVCMOS buffer type I2C interface - I2C1, I2C2, I2C3 and MCU_I2C1
These I2C interfaces are LVCMOS IO types. LVCMOS IOs being used on these ports are connected such they emulate open-drain outputs.
2. Termination of I2C interfaces when used as I2C interface and not used as I2C interface.
Open Drain buffer type I2C interface - I2C0 and MCU_I2C0
Refer 6.4 Pin Connectivity Requirements in the device specific datasheet.
These interfaces are recommended to be terminated when configured as I2C or as GPIO. When the IO is configured as input and being driven by a push-pull input from power-up the termination can be depopulated
LVCMOS buffer type I2C interface - I2C1, I2C2, I2C3 and MCU_I2C1
When configured as I2C interface, pullups are recommended. Since these IOs are LVCMOS type, the pullups are recommended to be connected with the shortest stub. When configured as GPIO, based on the use case an external pull can be provided or the internal pulls can be used.
3. Any additional recommendations / Guidelines
Refer below section of the device specific datasheet.
7.7.1 I2C Open-Drain, and Fail-Safe (I2C OD FS) Electrical Characteristics
4. Any concerns on Interfacing SoC Non-Failsafe I2C to devices that are powered before the SoC- Ex PMIC
Are the attached PMIC IOs true open-drain I2C IOs? If so, are the pull-up resistors associated with this I2C port powered by the same power supply that is used to power SoC I2C Example I2C0 IOs? We should not have a fail-safe problem if the answer to both questions is yes.
Is there anything else connected to these I2C signals that could source a potential to the I2C0 pins before the IOs are powered?
We are only concerned with fail-safe if there is a possibility for the attached devices to apply a potential to the SoC IOs before they receive power. We do not have any fail-safe concern if that is not possible.
5. Any exception that are required to be considered when using the I2C interfaces.
Refer section 7.10.5.9 I2C of the data sheet.
Read through the Exceptions section for I2C1, I2C2, I2C3 and MCU_I2C1 + Exceptions section for I2C0 and MCU_I2C0
Note:
Refer below documents during the I2C interface design.
Hardware Design Guide for AM6442, AM6422, AM6412 and AM2434 Processors
https://www.ti.com/lit/an/sprad67a/sprad67a.pdf
AM64x and AM243x Schematic Design and Review Checklist
https://www.ti.com/lit/an/spracu5c/spracu5c.pdf
6.Can the I2C interface be used to interface with devices supporting SMBus or PMBus
The I2C module implemented in these processor families does not support SM Bus or PM Bus
Regards,
Lavanya M R.
Hi Board designers,
Refer below inputs for I2C pullup calculation
www.ti.com/.../slva689.pdf
The board designer is responsible for selecting a pull-up value that meets the rise time requirements for their specific system implementation.
The I2C signal trace capacitance will vary based on their PCB design which means the pull-up value may need to be adjusted to achieve the appropriate rise time. A large pull-up value will produce a slow rise time, that will be easy to pull below VIL max. A small pull-up value will produce a fast rise time, that may be difficult to pull below VIL max. The I2C standard defines a range for the expected rise and fall times. However, some of the devices being connected to the I2C signal may have their own requirements and characteristics.
For example, our I2C ports implemented with the “I2C OD FS” IO cells have a very restrictive maximum input slew rate when operating at 3.3V and this limit
needs to be considered when selecting a pull-up resistor value. Another example, our I2C ports implemented with the “LVCMOS” IO cells will violate the minimum fall time defined in the I2C standard when driving the signal low. Note: This last example is not a function of pull-up value and was only mentioned for completeness. The board designer must also consider the output drive strength of each device driving the I2C signal to ensure it is able to pull the signal low enough for it to be considered a valid logic low for each device connected to the signal. Some devices may not be able to pull the signal below the lowest VIL max of the attached devices if the pull-up value is too small.
Regards,
Sreenivasa