AM5728: No EP controller created at /sys/kernel/config/pci_ep/controllers

Hi Sujan,

Could you share dmesg logs as well?

Also, could you share output from "ls /sys/kernel/config/pci_ep"?

These examples still exist in 5.10 kernel with very similar instructions for the AM6x platforms, so most likely the instructions are the same or similar with minor changes. The boot logs and directory structure should help locate where the driver is failing or if there was a change in directory structure.

Regards,

Takuma

Hi Takuma,

Here is the output : 

root@am57xx-phycore-kit:~# ls /sys/kernel/config/pci_ep
controllers  functions

Also PFA, dmesg log along with execution of the commands until binding.

PS also note that I'm trying to use PCIe lane 2 i.e 51800000.pcie_ep

Thanks & Regards,
Sujan

sitara_dmesg.txt

Hi Sujan,

Thanks for the logs. If 51800000 is being used, could you try changing this line:

ln -s functions/pci_epf_test/func1 controllers/51000000.pcie_ep/

To this line:

ln -s functions/pci_epf_test/func1 controllers/51800000.pcie_ep/

And if this new command does not work, could you ls under /sys/kernel/config/pci_ep/controllers to see if any pcie_ep appears under there?

Regards,

Takuma

Hi Takuma,

As i mentioned earlier there is nothing inside /sys/kernel/config/pci_ep/controllers/ 

Also i tried : 

ln -s functions/pci_epf_test/func1 controllers/51800000.pcie_ep/ 

and got  

ln: controllers/51800000.pcie_ep/: No such file or directory

since 51800000.pcie_ep is not yet created at the location.

Thanks,
Sujan

Hi Sujan,

The 51800000.pcie_ep directory should already be created if PCIe EP was initialized correctly.

I do see that there is some error logs in the shared dmesg logs, which looks like serdes and/or refclk is not being initialized correctly... but I will need some time to see if these logs are expected or not as they are slightly different from AM6x platform which I have the most experience with.

In the meantime, could you also check:

ls /sys/class/pci_epc/

And see if an EP gets listed?

Additionally, could you share logs from:

zcat /proc/config.gz

Which should list kernel configuration.

Regards,

Takuma

Thank you for replying Takuma,

ls /sys/class/pci_epc/ returned nothing .

But here is the zcat log.

Regards,
Sujanzcat.log

Hi Sujan,

Thanks for sharing the kernel configuration. It looks like all of the correct kernel configuration is set... so it might be an issue with device tree then.

I am assuming AM5728 is using arch/arm/boot/dts/am572x-idk.dts b/arch/arm/boot/dts/am572x-idk.dts, but could you share this file as well?

Regards,

Takuma

Hi Takuma,

We are using a PHYTEC SOM, so we have not made any modifications to am572x-idk.dts, but to am57xx-phycore-common.dtsi. 

I am attaching the am57xx-phycore-common.dtsi.

Also i am attaching am57xx-pcm-948-common.dtsi, where we have disabled pcie1 as root complex.

Thanks & Regards,
Sujan

/*
 * Copyright (C) 2018 PHYTEC America, LLC. - https://www.phytec.com
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include "am57xx-commercial-grade.dtsi"

/ {
	aliases {
		rtc0 = &rtc;
		rtc1 = &tps659038_rtc;
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		ipu1_memory_region: ipu1-memory@95800000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0x95800000 0x0 0x2000000>;
			reusable;
			status = "okay";
		};

		dsp1_memory_region: dsp1-memory@97800000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0x97800000 0x0 0x4000000>;
			reusable;
			status = "okay";
		};

		ipu2_memory_region: ipu2-memory@9b800000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0x9b800000 0x0 0x3800000>;
			reusable;
			status = "okay";
		};

		cmem_block_mem_0: cmem_block_mem@a0000000 {
			reg = <0x0 0xa0000000 0x0 0x0c000000>;
			no-map;
			status = "okay";
		};
	};

	cmem {
		compatible = "ti,cmem";
		#address-cells = <1>;
		#size-cells = <0>;

		#pool-size-cells = <2>;

		status = "okay";

		cmem_block_0: cmem_block@0 {
			reg = <0>;
			memory-region = <&cmem_block_mem_0>;
			cmem-buf-pools = <1 0x0 0x0c000000>;
		};
	};

	vdd_3v3: fixedregulator-vdd_3v3 {
		compatible = "regulator-fixed";
		regulator-name = "vdd_3v3";
		vin-supply = <&regen1>;
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};

	aic_dvdd: fixedregulator-aic_dvdd {
		compatible = "regulator-fixed";
		regulator-name = "aic_dvdd_fixed";
		vin-supply = <&vdd_3v3>;
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
	};

	vtt_fixed: fixedregulator-vtt {
		/* TPS51200 */
		compatible = "regulator-fixed";
		regulator-name = "vtt_fixed";
		vin-supply = <&smps3_reg>;
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
		regulator-boot-on;
		enable-active-high;
		gpio = <&gpio4 8 GPIO_ACTIVE_HIGH>;
	};

	phytec_leds: leds {
		compatible = "gpio-leds";
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&leds_som_pins_default>;
		pinctrl-1 = <&leds_som_pins_sleep>;

		led@0 {
			label = "am57xx-phycore-som:red";
			gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>;
			linux,default-trigger = "heartbeat";
			default-state = "off";
		};

		led@1 {
			label = "am57xx-phycore-som:green";
			gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>;
			linux,default-trigger = "cpu0";
			default-state = "off";
		};
	};
};

&dra7_pmx_core {
	leds_som_pins_default: leds_som_pins_default {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3588, PIN_OUTPUT | MUX_MODE14)	/* (F5) vin2a_d8.gpio4_9 */
			DRA7XX_CORE_IOPAD(0x358c, PIN_OUTPUT | MUX_MODE14)	/* (E6) vin2a_d9.gpio4_10 */
		>;
	};

	leds_som_pins_sleep: leds_som_pins_sleep {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3588, PIN_INPUT_PULLDOWN | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x358c, PIN_INPUT_PULLDOWN | MUX_MODE15)
		>;
	};

	i2c1_pins_default: i2c1_pins_default {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3800, PIN_INPUT_PULLUP | MUX_MODE0)	/* (C21) i2c1_sda */
			DRA7XX_CORE_IOPAD(0x3804, PIN_INPUT_PULLUP | MUX_MODE0)	/* (C20) i2c1_scl */
		>;
	};

	i2c1_pins_sleep: i2c1_pins_sleep {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3800, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x3804, PIN_INPUT | MUX_MODE15)
		>;
	};

	mmc2_pins_sleep: mmc2_pins_sleep {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT | MUX_MODE15)
		>;
	};

	emac0_pins_default: emac0_pins_default {
		pinctrl-single,pins = <
			/* Slave 1 */
			DRA7XX_CORE_IOPAD(0x3650, PIN_OUTPUT | MUX_MODE0)	/* (W9) rgmii0_txc */
			DRA7XX_CORE_IOPAD(0x3654, PIN_OUTPUT | MUX_MODE0)	/* (V9) rgmii0_txctl */
			DRA7XX_CORE_IOPAD(0x3658, PIN_OUTPUT | MUX_MODE0)	/* (V7) rgmii0_txd3 */
			DRA7XX_CORE_IOPAD(0x365c, PIN_OUTPUT | MUX_MODE0)	/* (U7) rgmii0_txd2 */
			DRA7XX_CORE_IOPAD(0x3660, PIN_OUTPUT | MUX_MODE0)	/* (V6) rgmii0_txd1 */
			DRA7XX_CORE_IOPAD(0x3664, PIN_OUTPUT | MUX_MODE0)	/* (U6) rgmii0_txd0 */
			DRA7XX_CORE_IOPAD(0x3668, PIN_INPUT | MUX_MODE0)	/* (U5) rgmii0_rxc */
			DRA7XX_CORE_IOPAD(0x366c, PIN_INPUT | MUX_MODE0)	/* (V5) rgmii0_rxctl */
			DRA7XX_CORE_IOPAD(0x3670, PIN_INPUT | MUX_MODE0)	/* (V4) rgmii0_rxd3 */
			DRA7XX_CORE_IOPAD(0x3674, PIN_INPUT | MUX_MODE0)	/* (V3) rgmii0_rxd2 */
			DRA7XX_CORE_IOPAD(0x3678, PIN_INPUT | MUX_MODE0)	/* (Y2) rgmii0_rxd1 */
			DRA7XX_CORE_IOPAD(0x367c, PIN_INPUT | MUX_MODE0)	/* (W2) rgmii0_rxd0 */
		>;

	};

	emac0_pins_sleep: emac0_pins_sleep {
		pinctrl-single,pins = <
			/* Slave 1 */
			DRA7XX_CORE_IOPAD(0x3650, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x3654, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x3658, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x365c, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x3660, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x3664, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x3668, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x366c, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x3670, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x3674, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x3678, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x367c, PIN_INPUT | MUX_MODE15)
		>;
	};

	davinci_mdio_pins_default: davinci_mdio_pins_default {
		pinctrl-single,pins = <
			/* MDIO */
			DRA7XX_CORE_IOPAD(0x363c, PIN_OUTPUT_PULLUP | MUX_MODE0)	/* (V1) mdio_mclk */
			DRA7XX_CORE_IOPAD(0x3640, PIN_INPUT_PULLUP | MUX_MODE0)		/* (U4) mdio_d */
		>;
	};

	davinci_mdio_pins_sleep: davinci_mdio_pins_sleep {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x363c, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x3640, PIN_INPUT | MUX_MODE15)
		>;
	};

	tps659038_pins_default: tps659038_pins_default {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3818, PIN_INPUT_PULLUP | MUX_MODE14)	/* (AD17) Wakeup0.gpio1_0 */
		>;
	};

	mcspi1_pins_default: mcspi1_pins_default {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x37a4, PIN_INPUT | MUX_MODE0)         /* spi1_sclk */
			DRA7XX_CORE_IOPAD(0x37a8, PIN_INPUT | MUX_MODE0)         /* spi1_d1 */
			DRA7XX_CORE_IOPAD(0x37ac, PIN_INPUT | MUX_MODE0)         /* spi1_d0 */
			DRA7XX_CORE_IOPAD(0x37b0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* spi1_cs0 */
			DRA7XX_CORE_IOPAD(0x37b4, PIN_OUTPUT_PULLUP | MUX_MODE0) /* spi1_cs1 */
		>;
	};

	qspi1_pins_default: qspi1_pins_default {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3474, PIN_INPUT | MODE_SELECT | MUX_MODE1)	/* (R3) gpmc_a13.qspi1_rtclk */
			DRA7XX_CORE_IOPAD(0x3478, PIN_INPUT | MODE_SELECT | MUX_MODE1)	/* (T2) gpmc_a14.qspi1_d3 */
			DRA7XX_CORE_IOPAD(0x347c, PIN_INPUT | MODE_SELECT | MUX_MODE1)	/* (U2) gpmc_a15.qspi1_d2 */
			DRA7XX_CORE_IOPAD(0x3480, PIN_INPUT | MODE_SELECT | MUX_MODE1)	/* (U1) gpmc_a16.qspi1_d0 */
			DRA7XX_CORE_IOPAD(0x3484, PIN_INPUT | MODE_SELECT | MUX_MODE1)	/* (P3) gpmc_a17.qspi1_d1 */
			DRA7XX_CORE_IOPAD(0x3488, PIN_INPUT | MODE_SELECT | MUX_MODE1)	/* (R2) gpmc_a18.qspi1_sclk */
		>;
	};

	qspi1_legacy_pins: qspi1_legacy_pins {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3478, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1)	/* (T2) gpmc_a14.qspi1_d3 */
			DRA7XX_CORE_IOPAD(0x347c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1)	/* (U2) gpmc_a15.qspi1_d2 */
		>;
	};

	qspi1_cs0_pin: qspi1_cs0_pin {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x34b8, PIN_OUTPUT | MODE_SELECT | MUX_MODE1)	/* (P2) gpmc_cs2.qspi1_cs0 */
		>;
	};

	qspi1_cs1_pin: qspi1_cs1_pin {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x34bc, PIN_OUTPUT | MODE_SELECT | MUX_MODE1)	/* (P1) gpmc_cs3.qspi1_cs1 */
		>;
	};

	qspi1_cs2_pin: qspi1_cs2_pin {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x344c, PIN_OUTPUT | MODE_SELECT | MUX_MODE1)	/* (T7) gpmc_a3.qspi1_cs2 */
		>;
	};

	gpmc_nand_pins_default: gpmc_nand_pins_default {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3400, PIN_INPUT_SLEW | MUX_MODE0)			/* (M6) gpmc_ad0 */
			DRA7XX_CORE_IOPAD(0x3404, PIN_INPUT_SLEW | MUX_MODE0)			/* (M2) gpmc_ad1 */
			DRA7XX_CORE_IOPAD(0x3408, PIN_INPUT_SLEW | MUX_MODE0)			/* (L5) gpmc_ad2 */
			DRA7XX_CORE_IOPAD(0x340c, PIN_INPUT_SLEW | MUX_MODE0)			/* (M1) gpmc_ad3 */
			DRA7XX_CORE_IOPAD(0x3410, PIN_INPUT_SLEW | MUX_MODE0)			/* (L6) gpmc_ad4 */
			DRA7XX_CORE_IOPAD(0x3414, PIN_INPUT_SLEW | MUX_MODE0)			/* (L4) gpmc_ad5 */
			DRA7XX_CORE_IOPAD(0x3418, PIN_INPUT_SLEW | MUX_MODE0)			/* (L3) gpmc_ad6 */
			DRA7XX_CORE_IOPAD(0x341c, PIN_INPUT_SLEW | MUX_MODE0)			/* (L2) gpmc_ad7 */
			DRA7XX_CORE_IOPAD(0x34b4, PIN_OUTPUT_PULLUP | SLEWCONTROL | MUX_MODE0)	/* (T1) gpmc_cs0 */
			DRA7XX_CORE_IOPAD(0x34c4, PIN_OUTPUT | SLEWCONTROL | MUX_MODE0)		/* (N1) gpmc_advn_ale */
			DRA7XX_CORE_IOPAD(0x34c8, PIN_OUTPUT | SLEWCONTROL | MUX_MODE0)		/* (M5) gpmc_oen_ren */
			DRA7XX_CORE_IOPAD(0x34cc, PIN_OUTPUT | SLEWCONTROL | MUX_MODE0)		/* (M3) gpmc_wen */
			DRA7XX_CORE_IOPAD(0x34d0, PIN_OUTPUT | SLEWCONTROL | MUX_MODE0)		/* (N6) gpmc_ben0 */
			DRA7XX_CORE_IOPAD(0x34d8, PIN_INPUT_SLEW | MUX_MODE14)			/* (N2) gpmc_wait0.gpio2_28 */
			DRA7XX_CORE_IOPAD(0x356c, PIN_INPUT_PULLUP | MUX_MODE15)		/* (F3) vin2a_d1.off */
		>;
	};

	eeprom_wp_pin: eeprom_wp_pin {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3724, PIN_OUTPUT | MUX_MODE14)	/* mcasp3_aclkx.gpio5_13 */
		>;
	};
};

&dra7_iodelay_core {
	qspi1_iodelay_conf: qspi1_iodelay_conf {
		pinctrl-pin-array = <
			0x144 A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_GPMC_A13_IN */
			0x150 A_DELAY_PS(2575) G_DELAY_PS(966)	/* CFG_GPMC_A14_IN */
			0x15c A_DELAY_PS(2503) G_DELAY_PS(889)	/* CFG_GPMC_A15_IN */
			0x168 A_DELAY_PS(2528) G_DELAY_PS(1007)	/* CFG_GPMC_A16_IN */
			0x170 A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_GPMC_A16_OUT */
			0x174 A_DELAY_PS(2533) G_DELAY_PS(980)	/* CFG_GPMC_A17_IN */
			0x188 A_DELAY_PS(590) G_DELAY_PS(0)	/* CFG_GPMC_A18_OUT */
			0x218 A_DELAY_PS(114) G_DELAY_PS(0)	/* CFG_GPMC_A3_OUT */
			0x374 A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_GPMC_CS2_OUT */
			0x380 A_DELAY_PS(70) G_DELAY_PS(0)	/* CFG_GPMC_CS3_OUT */
		>;
	};
};

&i2c1 {
	status = "okay";
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&i2c1_pins_default>;
	pinctrl-1 = <&i2c1_pins_sleep>;
	clock-frequency = <400000>;

	tps659038: tps659038@58 {
		compatible = "ti,tps659038";
		reg = <0x58>;

		pinctrl-names = "default";
		pinctrl-0 = <&tps659038_pins_default>;

		interrupt-parent = <&gpio1>;
		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;

		#interrupt-cells = <2>;
		interrupt-controller;

		ti,system-power-controller;
		ti,palmas-override-powerhold;

		tps659038_pmic {
			compatible = "ti,tps659038-pmic";

			smps12-in-supply = <&vcc_3v3>;
			smps3-in-supply = <&vcc_3v3>;
			smps45-in-supply = <&vcc_3v3>;
			smps6-in-supply = <&vcc_3v3>;
			smps8-in-supply = <&vcc_3v3>;
			ldo1-in-supply = <&vcc_5v0>;
			ldo2-in-supply = <&vcc_5v0>;
			ldo3-in-supply = <&vcc_3v3>;
			ldo4-in-supply = <&vcc_3v3>;
			ldo9-in-supply = <&vcc_3v3>;
			ldoln-in-supply = <&vcc_3v3>;
			ldousb-in-supply = <&vcc_5v0>;

			regulators {
				smps12_reg: smps12 {
					/* VDD_MPU */
					regulator-name = "smps12";
					regulator-min-microvolt = <850000>;
					regulator-max-microvolt = <1250000>;
					regulator-always-on;
					regulator-boot-on;
				};

				smps3_reg: smps3 {
					/* VDD_DDR */
					regulator-name = "smps3";
					regulator-min-microvolt = <1350000>;
					regulator-max-microvolt = <1350000>;
					regulator-always-on;
					regulator-boot-on;
				};

				smps45_reg: smps45 {
					/* VDD_DSPEVE, VDD_IVA, VDD_GPU */
					regulator-name = "smps45";
					regulator-min-microvolt = <850000>;
					regulator-max-microvolt = <1150000>;
					regulator-always-on;
					regulator-boot-on;
				};

				smps6_reg: smps6 {
					/* VDD_CORE */
					regulator-name = "smps6";
					regulator-min-microvolt = <850000>;
					regulator-max-microvolt = <1030000>;
					regulator-always-on;
					regulator-boot-on;
				};

				/* SMPS7 unused */

				smps8_reg: smps8 {
					/* VDD_1V8 */
					regulator-name = "smps8";
					regulator-min-microvolt = <1800000>;
					regulator-max-microvolt = <1800000>;
					regulator-always-on;
					regulator-boot-on;
				};

				/* SMPS9 unused */

				ldo1_reg: ldo1 {
					/* VDD_SD / VDDSHV8  */
					regulator-name = "ldo1";
					regulator-min-microvolt = <1800000>;
					regulator-max-microvolt = <3300000>;
					regulator-always-on;
					regulator-boot-on;
				};

				ldo2_reg: ldo2 {
					/* VDD_SHV5 */
					regulator-name = "ldo2";
					regulator-min-microvolt = <3300000>;
					regulator-max-microvolt = <3300000>;
					regulator-always-on;
					regulator-boot-on;
				};

				ldo3_reg: ldo3 {
					/* VDDA_1V8_PHYA */
					regulator-name = "ldo3";
					regulator-min-microvolt = <1800000>;
					regulator-max-microvolt = <1800000>;
					regulator-always-on;
					regulator-boot-on;
				};

				ldo4_reg: ldo4 {
					/* VDDA_1V8_PHYB */
					regulator-name = "ldo4";
					regulator-min-microvolt = <1800000>;
					regulator-max-microvolt = <1800000>;
					regulator-always-on;
					regulator-boot-on;
				};

				ldo9_reg: ldo9 {
					/* VDD_RTC */
					regulator-name = "ldo9";
					regulator-min-microvolt = <1050000>;
					regulator-max-microvolt = <1050000>;
					regulator-always-on;
					regulator-boot-on;
				};

				ldoln_reg: ldoln {
					/* VDDA_1V8_PLL */
					regulator-name = "ldoln";
					regulator-min-microvolt = <1800000>;
					regulator-max-microvolt = <1800000>;
					regulator-always-on;
					regulator-boot-on;
				};

				ldousb_reg: ldousb {
					/* VDDA_3V_USB: VDDA_USBHS33 */
					regulator-name = "ldousb";
					regulator-min-microvolt = <3300000>;
					regulator-max-microvolt = <3300000>;
					regulator-boot-on;
				};

				regen1: regen1 {
					/* VDD_3V3_ON */
					regulator-name = "regen1";
					regulator-boot-on;
					regulator-always-on;
				};
			};
		};

		tps659038_pwr_button: tps659038_pwr_button {
			compatible = "ti,palmas-pwrbutton";
			interrupt-parent = <&tps659038>;
			interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
			wakeup-source;
			ti,palmas-long-press-seconds = <12>;
		};

		tps659038_rtc: tps659038_rtc {
			status = "okay";
			compatible = "ti,palmas-rtc";
			interrupt-parent = <&tps659038>;
			interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
			wakeup-source;
		};
	};

	i2c_eeprom: eeprom@50 {
		status = "okay";
		compatible = "atmel,24c32";
		pinctrl-names = "default";
		pinctrl-0 = <&eeprom_wp_pin>;
		wp-gpios = <&gpio5 13 GPIO_ACTIVE_HIGH>;
		reg = <0x50>;
		pagesize = <32>;
	};

	i2c_rtc: rtc@68 {
		status = "disabled";
		compatible = "microcrystal,rv4162";
		reg = <0x68>;
	};
};

&gpio4 {
	ti,no-reset-on-init;
	ti,no-idle-on-init;
};

&mcasp1 {
	compatible = "ti,dra7-mcasp1-audio";
	reg = <0x48460000 0x2000>,
	      <0x45800000 0x400000>;
	reg-names = "mpu", "dat";
};

&mac {
	status = "okay";
	slaves = <1>;
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&emac0_pins_default>;
	pinctrl-1 = <&emac0_pins_sleep>;
};

&davinci_mdio {
	status = "okay";
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&davinci_mdio_pins_default>;
	pinctrl-1 = <&davinci_mdio_pins_sleep>;

	phy0: ethernet-phy@1 {
		reg = <1>;
	};
};

&cpsw_emac0 {
	status = "okay";

	phy-handle = <&phy0>;
	phy-mode = "rgmii";
	dual_emac_res_vlan = <1>;
};

&cpsw_emac1 {
	status = "okay";
};

&mmc2 {
	status = "okay";
	vmmc-supply = <&vdd_3v3>;
	vqmmc-supply = <&vdd_3v3>;
	bus-width = <8>;
	non-removable;
	max-frequency = <96000000>;
	no-1-8-v;
};

&mcspi1 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&mcspi1_pins_default>;

	ti,pindir-d0-out-d1-in;
};

/* NOTE: support added for pcie2 in endpoint mode
 *       additionally, setting axi1 { status = "okay" };
 *       is necessary for any pcie2 use.
 *
 *       pcie2_rc/ep are incompatible with PCM-948
 */
&axi1 {
	pcie2_ep: pcie_ep@51800000 {
		compatible = "ti,dra7-pcie-ep";
		reg = <0x51800000 0x28>, <0x51802000 0x14c>,
		      <0x51801000 0x28>, <0x1000 0x10000000>;
		reg-names = "ep_dbics", "ti_conf", "ep_dbics2", "addr_space";
		interrupts = <0 355 0x4>;
		num-lanes = <1>;
		num-ib-windows = <4>;
		num-ob-windows = <16>;
		ti,hwmods = "pcie2";
		phys = <&pcie2_phy>;
		phy-names = "pcie-phy1";
		syscon-legacy-mode = <&scm_conf1 0x14 1>;
		status = "okay";
	};
};

&qspi {
	status = "okay";

	pinctrl-names = "default";
	pinctrl-0 = <&qspi1_pins_default &qspi1_iodelay_conf>;

	spi-max-frequency = <76800000>;

	/* .3 and older PCB has QSPI NOR populated on
	 * CS2, cannot support more than SPI-DIO mode,
	 * and requires internal pull-ups on D2/D3
	 */
	qspi_nor: m25p80@2 {
		status = "okay";

		pinctrl-names = "default";
		pinctrl-0 = <&qspi1_legacy_pins &qspi1_cs2_pin>;
		compatible = "n25q128a13", "jedec,spi-nor";

		reg = <2>;
		spi-max-frequency = <76800000>;
		spi-tx-bus-width = <1>;
		spi-rx-bus-width = <2>;
		#address-cells = <1>;
		#size-cells = <1>;

		/* MTD partition table.
		 * The ROM checks the first four physical blocks
		 * for a valid file to boot and the flash here is
		 * 64KiB block size.
		 */
		partition@0 {
			label = "QSPI.SPL";
			reg = <0x00000000 0x000040000>;
		};
		partition@1 {
			label = "QSPI.u-boot";
			reg = <0x00040000 0x00100000>;
		};
		partition@2 {
			label = "QSPI.u-boot-spl-os";
			reg = <0x00140000 0x00080000>;
		};
		partition@3 {
			label = "QSPI.u-boot-env";
			reg = <0x001c0000 0x00010000>;
		};
		partition@4 {
			label = "QSPI.u-boot-env.backup1";
			reg = <0x001d0000 0x0010000>;
		};
		partition@5 {
			label = "QSPI.kernel";
			reg = <0x001e0000 0x0800000>;
		};
		partition@6 {
			label = "QSPI.file-system";
			reg = <0x009e0000 0x0>;
		};
	};

	qspi_nor_cs0: m25p80@0 {
		status = "okay";

		pinctrl-names = "default";
		pinctrl-0 = <&qspi1_cs0_pin>;
		compatible = "n25q128a13", "jedec,spi-nor";

		reg = <0>;
		spi-max-frequency = <76800000>;
		spi-tx-bus-width = <1>;
		spi-rx-bus-width = <4>;
		#address-cells = <1>;
		#size-cells = <1>;

		/* MTD partition table.
		 * The ROM checks the first four physical blocks
		 * for a valid file to boot and the flash here is
		 * 64KiB block size.
		 */
		partition@0 {
			label = "QSPI.SPL";
			reg = <0x00000000 0x000040000>;
		};
		partition@1 {
			label = "QSPI.u-boot";
			reg = <0x00040000 0x00100000>;
		};
		partition@2 {
			label = "QSPI.u-boot-spl-os";
			reg = <0x00140000 0x00080000>;
		};
		partition@3 {
			label = "QSPI.u-boot-env";
			reg = <0x001c0000 0x00010000>;
		};
		partition@4 {
			label = "QSPI.u-boot-env.backup1";
			reg = <0x001d0000 0x0010000>;
		};
		partition@5 {
			label = "QSPI.kernel";
			reg = <0x001e0000 0x0800000>;
		};
		partition@6 {
			label = "QSPI.file-system";
			reg = <0x009e0000 0x0>;
		};
	};
};

&gpmc {
	status = "disabled";
	pinctrl-names = "default";
	pinctrl-0 = <&gpmc_nand_pins_default>;

	ranges = <0 0 0x08000000 0x01000000>;		/* minimum GPMC partition = 16MB */

	nand@0,0 {
		compatible = "ti,omap2-nand";
		reg = <0 0 4>;				/* device IO registers */
		interrupt-parent = <&gpmc>;
		interrupts = <0 IRQ_TYPE_NONE>,		/* fifoevent */
			<1 IRQ_TYPE_NONE>;		/* termcount */
		rb-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>;	/* gpmc_wait0 pin */

		/* Settings for Micron MT29F8G08ABACAWP 1GB NAND */
		ti,nand-ecc-opt = "bch16";
		ti,elm-id = <&elm>;
		nand-bus-width = <8>;
		gpmc,device-width = <1>;
		gpmc,sync-clk-ps = <0>;
		gpmc,cs-on-ns = <0>;
		gpmc,cs-rd-off-ns = <35>;
		gpmc,cs-wr-off-ns = <25>;
		gpmc,adv-on-ns = <0>;
		gpmc,adv-rd-off-ns = <35>;
		gpmc,adv-wr-off-ns = <25>;
		gpmc,we-on-ns = <0>;
		gpmc,we-off-ns = <15>;
		gpmc,oe-on-ns = <15>;
		gpmc,oe-off-ns = <30>;
		gpmc,access-ns = <35>;
		gpmc,wr-access-ns = <25>;
		gpmc,rd-cycle-ns = <35>;
		gpmc,wr-cycle-ns = <25>;
		gpmc,bus-turnaround-ns = <0>;
		gpmc,cycle2cycle-delay-ns = <0>;
		gpmc,clk-activation-ns = <0>;
		gpmc,wr-data-mux-bus-ns = <0>;

		/* MTD partition table for 1GB NAND */
		#address-cells = <1>;
		#size-cells = <1>;
		partition@0 {
			label = "NAND.SPL";
			reg = <0x00000000 0x00040000>;
		};
		partition@1 {
			label = "NAND.SPL.backup1";
			reg = <0x00040000 0x00040000>;
		};
		partition@2 {
			label = "NAND.SPL.backup2";
			reg = <0x00080000 0x00040000>;
		};
		partition@3 {
			label = "NAND.SPL.backup3";
			reg = <0x000C0000 0x00040000>;
		};
		partition@4 {
			label = "NAND.u-boot";
			reg = <0x00100000 0x00200000>;
		};
		partition@5 {
			label = "NAND.u-boot-env";
			reg = <0x00300000 0x00040000>;
		};
		partition@6 {
			label = "NAND.file-system";
			reg = <0x00340000 0>;
		};
	};
};

&mailbox3 {
	status = "okay";
	mbox_pru1_0: mbox_pru1_0 {
		status = "okay";
	};
	mbox_pru1_1: mbox_pru1_1 {
		status = "okay";
	};
};

&mailbox4 {
	status = "okay";
	mbox_pru2_0: mbox_pru2_0 {
		status = "okay";
	};
	mbox_pru2_1: mbox_pru2_1 {
		status = "okay";
	};
};

&ipu1 {
	status = "okay";
	memory-region = <&ipu1_memory_region>;
};

&ipu2 {
	status = "okay";
	memory-region = <&ipu2_memory_region>;
};

&dsp1 {
	status = "okay";
	memory-region = <&dsp1_memory_region>;
};

&pruss1 {
	status = "okay";
};

&pru1_0 {
	mboxes = <&mailbox3 &mbox_pru1_0>;
	status = "okay";
};

&pru1_1 {
	mboxes = <&mailbox3 &mbox_pru1_1>;
	status = "okay";
};

&pruss2 {
	status = "okay";
};

&pru2_0 {
	mboxes = <&mailbox4 &mbox_pru2_0>;
	status = "okay";
};

&pru2_1 {
	mboxes = <&mailbox4 &mbox_pru2_1>;
	status = "okay";
};

&pcie2_ep {
	status = "okay";
};

&axi1 {
	status = "okay";
};

&rtc {
	status = "okay";
};

/*
 * Copyright (C) 2015 PHYTEC America, LLC - www.phytec.com
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include "dra7-mmc-iodelay.dtsi"

/ {
	aliases {
		display0 = &lcd2;
		display1 = &hdmi0;

		sound0 = &rdk_audio;
		sound1 = &hdmi;
	};

	vcc_3v3: fixedregulator-vcc_3v3 {
		compatible = "regulator-fixed";
		regulator-name = "vcc_3v3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
		regulator-boot-on;
	};

	vcc_5v0: fixedregulator-vcc_5v0 {
		compatible = "regulator-fixed";
		regulator-name = "vcc_5v0";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		regulator-always-on;
		regulator-boot-on;
	};

	hdmi0: connector@0 {
		compatible = "hdmi-connector";
		status = "okay";
		label = "hdmi";

		type = "a";

		port {
			hdmi_connector_in: endpoint {
				remote-endpoint = <&tpd12s521_out>;
			};
		};
	};

	tpd12s521: encoder@0 {
		compatible = "ti,tpd12s521", "ti,tpd12s015";
		status = "okay";

		gpios = <0>,				/* CT_CP_HPD (optional) */
			<0>,				/* LS_OE (optional) */
			<&gpio7 12 GPIO_ACTIVE_HIGH>;	/* HPD */

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;

				tpd12s521_in: endpoint@0 {
					remote-endpoint = <&hdmi_out>;
				};
			};

			port@1 {
				reg = <1>;

				tpd12s521_out: endpoint@0 {
					remote-endpoint = <&hdmi_connector_in>;
				};
			};
		};
	};

	rdk_audio: sound {
		compatible = "simple-audio-card";
		status = "okay";
		simple-audio-card,name = "phyCORE-AM57xx-RDK";
		simple-audio-card,widgets =
			"Line", "Line Out",
			"Line", "Line In",
			"Microphone", "Mic Jack",
			"Headphone", "HP Jack";
		simple-audio-card,routing =
			"Line Out",	"LLOUT",
			"Line Out",	"RLOUT",

			"LINE1R",	"Line In",
			"LINE1R",	"Line In",

			"MIC3L",	"Mic Jack",
			"MIC3R",	"Mic Jack",
			"Mic Jack",	"Mic Bias",

			"HP Jack",	"HPLOUT",
			"HP Jack",	"HPROUT";
		simple-audio-card,format = "dsp_b";
		simple-audio-card,bitclock-master = <&sound_master>;
		simple-audio-card,frame-master = <&sound_master>;
		simple-audio-card,bitclock-inversion;

		simple-audio-card,cpu {
			sound-dai = <&mcasp1>;
		};

		sound_master: simple-audio-card,codec {
			sound-dai = <&tlv320aic3007>;
			clocks = <&clkout2_clk>;
		};
	};

	gpio_fan: gpio_fan {
		compatible = "gpio-fan";
		status = "okay";
		pinctrl-names = "default";
		pinctrl-0 = <&fan_pins_default>;

		gpios =  <&gpio7 5 GPIO_ACTIVE_HIGH>;
		gpio-fan,speed-map = <0    0
				      13000 1>;
		cooling-min-state = <0>;
		cooling-max-state = <1>;
		#cooling-cells = <2>;
	};

	/* For LVDS display at connector X25 */
	backlight: backlight {
		compatible = "pwm-backlight";
		status = "disabled";
	};

	lcd2: display {
		status = "disabled";
		pinctrl-names = "default";
		pinctrl-0 = <&lcd_pins &lcd_pins_iodelay_conf>;

		label = "lcd2";

		backlight = <&backlight>;
		enable-gpios = <&gpio8 23 GPIO_ACTIVE_LOW>;
	};

	/* For wilink8 interface at connector X26 */
	wlan_fixed: fixedregulator-wlan {
		compatible = "regulator-fixed";
		status = "disabled";

		pinctrl-names = "default";
		pinctrl-0 = <&wlan_pins_default>;

		regulator-name = "wlan_fixed";
		gpio = <&gpio1 24 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	bt_fixed: fixedregulator-bt {
		compatible = "regulator-fixed";
		status = "disabled";

		pinctrl-names = "default";
		pinctrl-0 = <&bt_pin_default>;

		regulator-name = "bt_fixed";
		gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>;
		enable-active-high;
		regulator-always-on;
	};

	user_io@0 {
               compatible = "mydevice,generic-uio,ui_pdrv";
               status = "okay";
               interrupt-parent = <&gpio1>;
               interrupts = <26 IRQ_TYPE_EDGE_RISING>;
               pinctrl-names = "default";
               pinctrl-0 = <&gpio1B_pins>;
       };

       user_io@1 {
               compatible = "mydevice,generic-uio,ui_pdrv";
               status = "okay";
               interrupt-parent = <&gpio1>;
               interrupts = <28 IRQ_TYPE_EDGE_RISING>;
               pinctrl-names = "default";
                       pinctrl-0 = <&gpio1A_pins>;
       };
};

&dra7_pmx_core {
	leds_cb_pins_default: leds_cb_pins_default {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3458, PIN_OUTPUT | MUX_MODE14)	/* (R5) gpmc_a6.gpio1_28 */
			DRA7XX_CORE_IOPAD(0x345c, PIN_OUTPUT | MUX_MODE14)	/* (P5) gpmc_a7.gpio1_29 */
		>;
	};

	leds_cb_pins_sleep: leds_cb_pins_sleep {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3458, PIN_INPUT_PULLDOWN | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x345c, PIN_INPUT_PULLDOWN | MUX_MODE15)
		>;
	};

	fan_pins_default: fan_pins_default {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3448, PIN_OUTPUT | MUX_MODE14)	/* (T6) gpmc_a2.gpio7_5 */
		>;
	};

	i2c2_pins: pinmux_i2c2_pins {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3808, PIN_INPUT | MUX_MODE1)	/* (C25) i2c2_sda.hdmi1_ddc_scl */
			DRA7XX_CORE_IOPAD(0x380c, PIN_INPUT | MUX_MODE1)	/* (F17) i2c2_scl.hdmi1_ddc_sda */
		>;
	};

	i2c4_pins_default: i2c4_pins_default {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3440, PIN_INPUT_PULLUP | MUX_MODE7)	/* (R6) gpmc_a0.i2c4_scl */
			DRA7XX_CORE_IOPAD(0x3444, PIN_INPUT_PULLUP | MUX_MODE7)	/* (T9) gpmc_a1.i2c4_sda */
		>;
	};

	i2c4_pins_sleep: i2c4_pins_sleep {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3440, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x3444, PIN_INPUT | MUX_MODE15)
		>;
	};

	uart3_pins_default: uart3_pins_default {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3648, PIN_INPUT_SLEW | MUX_MODE0)	/* (V2) uart3_rxd */
			DRA7XX_CORE_IOPAD(0x364c, PIN_INPUT_SLEW | MUX_MODE0)	/* (Y1) uart3_txd */
		>;
	};

	uart3_pins_sleep: uart3_pins_sleep {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3648, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x364c, PIN_INPUT | MUX_MODE15)
		>;
	};

	uart5_pins_default: uart5_pins_default {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x35dc, PIN_INPUT_SLEW | MUX_MODE2)	/* (F11) vout1_d0.uart5_rxd */
			DRA7XX_CORE_IOPAD(0x35e0, PIN_INPUT_SLEW | MUX_MODE2)	/* (G10) vout1_d1.uart5_txd */
		>;
	};

	uart5_pins_sleep: uart5_pins_sleep {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x35dc, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x35e0, PIN_INPUT | MUX_MODE15)
		>;
	};

//qnu

       uart6_pins_default: uart6_pins_default {
               pinctrl-single,pins = <
//                     0x50 (PIN_INPUT_SLEW | MUX_MODE8) /* gpmc_a4.uart6_rxd */
                       0x54 (PIN_INPUT | MUX_MODE14) /* gpmc_a5.uart6_txd */
//                     0x58 (PIN_INPUT_SLEW | MUX_MODE8) /* gpmc_a6.uart6_ctsn */
                       0x5c (PIN_INPUT | MUX_MODE14) /* gpmc_a7.uart6_rtsn */
               >;
       };

       uart6_pins_sleep: uart6_pins_sleep{
               pinctrl-single,pins = <
//                     0x50 (PIN_INPUT | MUX_MODE15)
                       0x54 (PIN_INPUT | MUX_MODE15)
//                     0x58 (PIN_INPUT | MUX_MODE15)
                       0x5c (PIN_INPUT | MUX_MODE15)
               >;
       };
               
       gpio1A_pins: pinmux_gpio1A_pins {
               pinctrl-single,pins = <
                         0x58 (PIN_INPUT_SLEW | MUX_MODE14) /* gpmc_a6.gpio1_28 */
               >;
       };

       gpio1B_pins: pinmux_gpio1B_pins {
                pinctrl-single,pins = <
                         0x50 (PIN_INPUT_SLEW | MUX_MODE14) /* gpmc_a4.gpio1_26 */
                >;
        };


       gpio1C_pins: pinmux_gpio1C_pins {
                pinctrl-single,pins = <
                         0x170 (PIN_INPUT_SLEW | MUX_MODE14) /* gpmc_a4.gpio4_3 */
                >;
        };

//qnu end

	uart10_pins_default: uart10_pins_default {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3570, PIN_INPUT_SLEW | MUX_MODE8)	/* (D1) vin2a_d2.uart10_rxd */
			DRA7XX_CORE_IOPAD(0x3574, PIN_INPUT_SLEW | MUX_MODE8)	/* (E2) vin2a_d3.uart10_txd */
			DRA7XX_CORE_IOPAD(0x3578, PIN_INPUT_SLEW | MUX_MODE8)	/* (D2) vin2a_d4.uart10_ctsn */
			DRA7XX_CORE_IOPAD(0x357c, PIN_INPUT_SLEW | MUX_MODE8)	/* (F4) vin2a_d5.uart10_rtsn */
		>;
	};

	uart10_pins_sleep: uart10_pins_sleep {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3570, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x3574, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x3578, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x357c, PIN_INPUT | MUX_MODE15)
		>;
	};


	mmc1_cd_wp_pins: mmc1_cd_wp_pins {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14)	/* (W7) mmc1_sdcd.gpio6_27 */
			DRA7XX_CORE_IOPAD(0x3770, PIN_INPUT | MUX_MODE14)	/* (Y9) mmc1_sdwp.gpio6_28 */
		>;
	};

	mmc1_pins_sleep: mmc1_pins_sleep {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x3770, PIN_INPUT | MUX_MODE15)
		>;
	};

	wlan_pins_default: wlan_pins_default {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x379c, PIN_OUTPUT_PULLDOWN | MUX_MODE14)	/* (AB8) mmc3_dat6.gpio1_24 */
			DRA7XX_CORE_IOPAD(0x37a0, PIN_INPUT_PULLDOWN | MUX_MODE14)	/* (AB5) mmc3_dat7.gpio1_25 */
		>;
	};

	bt_pin_default: bt_pin_default {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3794, PIN_OUTPUT_PULLDOWN | MUX_MODE14)	/* (AC8) mmc3_dat4.gpio1_22 */
		>;
	};

	bt_pin_sleep: bt_pin_sleep {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3794, PIN_INPUT_PULLUP | MUX_MODE15)
		>;
	};

	emac1_pins_default: emac1_pins_default {
		pinctrl-single,pins = <
			/* Slave 2 */
			DRA7XX_CORE_IOPAD(0x3598, PIN_OUTPUT | MUX_MODE3)	/* (D5) vin2a_d12.rgmii1_txc */
			DRA7XX_CORE_IOPAD(0x359c, PIN_OUTPUT | MUX_MODE3)	/* (C2) vin2a_d13.rgmii1_txct*/
			DRA7XX_CORE_IOPAD(0x35a0, PIN_OUTPUT | MUX_MODE3)	/* (C3) vin2a_d14.rgmii1_txd3*/
			DRA7XX_CORE_IOPAD(0x35a4, PIN_OUTPUT | MUX_MODE3)	/* (C4) vin2a_d15.rgmii1_txd2*/
			DRA7XX_CORE_IOPAD(0x35a8, PIN_OUTPUT | MUX_MODE3)	/* (B2) vin2a_d16.rgmii1_txd1*/
			DRA7XX_CORE_IOPAD(0x35ac, PIN_OUTPUT | MUX_MODE3)	/* (D6) vin2a_d17.rgmii1_txd0*/
			DRA7XX_CORE_IOPAD(0x35b0, PIN_INPUT | MUX_MODE3)	/* (C5) vin2a_d18.rgmii1_rxc */
			DRA7XX_CORE_IOPAD(0x35b4, PIN_INPUT | MUX_MODE3)	/* (A3) vin2a_d19.rgmii1_rxct*/
			DRA7XX_CORE_IOPAD(0x35b8, PIN_INPUT | MUX_MODE3)	/* (B3) vin2a_d20.rgmii1_rxd3*/
			DRA7XX_CORE_IOPAD(0x35bc, PIN_INPUT | MUX_MODE3)	/* (B4) vin2a_d21.rgmii1_rxd2*/
			DRA7XX_CORE_IOPAD(0x35c0, PIN_INPUT | MUX_MODE3)	/* (B5) vin2a_d22.rgmii1_rxd1*/
			DRA7XX_CORE_IOPAD(0x35c4, PIN_INPUT | MUX_MODE3)	/* (A4) vin2a_d23.rgmii1_rxd0*/
		>;

	};

	emac1_pins_sleep: emac1_pins_sleep {
		pinctrl-single,pins = <
			/* Slave 2 */
			DRA7XX_CORE_IOPAD(0x3598, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x359c, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x35a0, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x35a4, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x35a8, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x35ac, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x35b0, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x35b4, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x35b8, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x35bc, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x35c0, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x35c4, PIN_INPUT | MUX_MODE15)
		>;
	};

	hdmi_pins: pinmux_hdmi_pins {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x37b8, PIN_INPUT_PULLDOWN | MUX_MODE14)	/* (B21) spi1_cs2.gpio7_12 */
			DRA7XX_CORE_IOPAD(0x37bc, PIN_INPUT_SLEW | MUX_MODE6)		/* (B20) spi1_cs3.hdmi1_cec */
		>;
	};

	usb1_pins: pinmux_usb1_pins {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3680, PIN_INPUT_SLEW | MUX_MODE0)	/* (AB10) usb1_drvvbus */
			DRA7XX_CORE_IOPAD(0x362c, PIN_INPUT | MUX_MODE14)	/* (C9) vout1_d20.gpio8_20 */
		>;
	};

	usb2_pins_default: pinmux_usb2_pins_default {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3630, PIN_INPUT | MUX_MODE14)	/* (A9) vout1_d21.gpio8_21 */
			DRA7XX_CORE_IOPAD(0x3684, PIN_INPUT_SLEW | MUX_MODE0)	/* (AC10) usb2_drvvbus */
		>;
	};

	usb2_pins_sleep: pinmux_usb2_pins_sleep {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3630, PIN_INPUT | MUX_MODE14)
			DRA7XX_CORE_IOPAD(0x3684, PIN_INPUT_SLEW | MUX_MODE15)
		>;
	};

	extcon_pins_default:  extcon_pins_default {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x35d0, PIN_INPUT_PULLDOWN | MUX_MODE14)	/* (B11) vout1_fld.gpio4_21 */
			DRA7XX_CORE_IOPAD(0x35f4, PIN_INPUT | MUX_MODE14)		/* (F8) vout1_d6.gpio8_6 */
		>;
	};

	clkout2_pins_default: clkout2_pins_default {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3694, PIN_INPUT_PULLDOWN | MUX_MODE9)	/* (D18) xref_clk0.clkout2 */
		>;
	};

	clkout2_pins_sleep: clkout2_pins_sleep {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3694, PIN_INPUT | MUX_MODE15)
		>;
	};

	dcan1_pins: dcan1_pins {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0)	/* (G20) dcan1_tx */
			DRA7XX_CORE_IOPAD(0x37d4, PIN_INPUT_PULLUP | MUX_MODE0)		/* (G19) dcan1_rx */
		>;
	};

	dcan2_pins: dcan2_pins {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3688, PIN_OUTPUT_PULLUP | MUX_MODE2)	/* (E21) gpio6_14.dcan2_tx */
			DRA7XX_CORE_IOPAD(0x368c, PIN_INPUT_PULLUP | MUX_MODE2)		/* (F20) gpio6_15.dcan2_rx */
		>;
	};

	mcasp1_pins_default: mcasp1_pins_default {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x36a4, PIN_INPUT_PULLDOWN | MUX_MODE0)	/* (C14) mcasp1_aclkx */
			DRA7XX_CORE_IOPAD(0x36a8, PIN_INPUT_PULLDOWN | MUX_MODE0)	/* (D14) mcasp1_fsx */
			DRA7XX_CORE_IOPAD(0x36ec, PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* (G14) mcasp1_axr14 */
			DRA7XX_CORE_IOPAD(0x36f0, PIN_INPUT_PULLDOWN | MUX_MODE0)	/* (F14) mcasp1_axr15 */
		>;
	};

	mcasp1_pins_sleep: mcasp1_pins_sleep {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x36a4, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x36a8, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x36ec, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x36f0, PIN_INPUT | MUX_MODE15)
		>;
	};

	edt_ts_irq_pin: edt_ts_irq_pin {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3634, PIN_INPUT_PULLUP | MUX_MODE14)	/* (B9) vout1_d22.gpio8_22 */
		>;
	};

	stmpe_ts_irq_pin: stmpe_ts_irq_pin {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x36e8, PIN_INPUT | MUX_MODE14)	/* (A13) mcasp1_axr13.gpio6_4 */
		>;
	};

        lcd_pins: pinmux_lcd {
                pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3558, PIN_OUTPUT | MUX_MODE4 | SLEWCONTROL | MODE_SELECT)   /* (G2) vin2a_de0.vout2_de */
			DRA7XX_CORE_IOPAD(0x355c, PIN_OUTPUT | MUX_MODE4 | SLEWCONTROL | MODE_SELECT)   /* (H7) vin2a_fld0.vout2_clk */
			DRA7XX_CORE_IOPAD(0x3560, PIN_OUTPUT | MUX_MODE4 | SLEWCONTROL | MODE_SELECT)   /* (G1) vin2a_hsync0.vout2_hsync */
			DRA7XX_CORE_IOPAD(0x3564, PIN_OUTPUT | MUX_MODE4 | SLEWCONTROL | MODE_SELECT)   /* (G6) vin2a_vsync0.vout2_vsync */
			DRA7XX_CORE_IOPAD(0x3638, PIN_OUTPUT_PULLDOWN | MUX_MODE14)			/* (A10) vout1_d23.gpio8_23 */
			DRA7XX_CORE_IOPAD(0x36ac, PIN_OUTPUT | MUX_MODE6 | SLEWCONTROL | MODE_SELECT)   /* (B14) mcasp1_aclkr.vout2_d0 */
			DRA7XX_CORE_IOPAD(0x36b0, PIN_OUTPUT | MUX_MODE6 | SLEWCONTROL | MODE_SELECT)   /* (J14) mcasp1_fsr.vout2_d1 */
			DRA7XX_CORE_IOPAD(0x36bc, PIN_OUTPUT | MUX_MODE6 | SLEWCONTROL | MODE_SELECT)   /* (G13) mcasp1_axr2.vout2_d2 */
			DRA7XX_CORE_IOPAD(0x36c0, PIN_OUTPUT | MUX_MODE6 | SLEWCONTROL | MODE_SELECT)   /* (J11) mcasp1_axr3.vout2_d3 */
			DRA7XX_CORE_IOPAD(0x36c4, PIN_OUTPUT | MUX_MODE6 | SLEWCONTROL | MODE_SELECT)   /* (E12) mcasp1_axr4.vout2_d4 */
			DRA7XX_CORE_IOPAD(0x36c8, PIN_OUTPUT | MUX_MODE6 | SLEWCONTROL | MODE_SELECT)   /* (F13) mcasp1_axr5.vout2_d5 */
			DRA7XX_CORE_IOPAD(0x36cc, PIN_OUTPUT | MUX_MODE6 | SLEWCONTROL | MODE_SELECT)   /* (C12) mcasp1_axr6.vout2_d6 */
			DRA7XX_CORE_IOPAD(0x36d0, PIN_OUTPUT | MUX_MODE6 | SLEWCONTROL | MODE_SELECT)   /* (D12) mcasp1_axr7.vout2_d7 */
			DRA7XX_CORE_IOPAD(0x36fc, PIN_OUTPUT | MUX_MODE6 | SLEWCONTROL | MODE_SELECT)   /* (E15) mcasp2_aclkr.vout2_d8 */
			DRA7XX_CORE_IOPAD(0x3700, PIN_OUTPUT | MUX_MODE6 | SLEWCONTROL | MODE_SELECT)   /* (A20) mcasp2_fsr.vout2_d9 */
			DRA7XX_CORE_IOPAD(0x3704, PIN_OUTPUT | MUX_MODE6 | SLEWCONTROL | MODE_SELECT)   /* (B15) mcasp2_axr0.vout2_d10 */
			DRA7XX_CORE_IOPAD(0x3708, PIN_OUTPUT | MUX_MODE6 | SLEWCONTROL | MODE_SELECT)   /* (A15) mcasp2_axr1.vout2_d11 */
			DRA7XX_CORE_IOPAD(0x3714, PIN_OUTPUT | MUX_MODE6 | SLEWCONTROL | MODE_SELECT)   /* (D15) mcasp2_axr4.vout2_d12 */
			DRA7XX_CORE_IOPAD(0x3718, PIN_OUTPUT | MUX_MODE6 | SLEWCONTROL | MODE_SELECT)   /* (B16) mcasp2_axr5.vout2_d13 */
			DRA7XX_CORE_IOPAD(0x371c, PIN_OUTPUT | MUX_MODE6 | SLEWCONTROL | MODE_SELECT)   /* (B17) mcasp2_axr6.vout2_d14 */
			DRA7XX_CORE_IOPAD(0x3720, PIN_OUTPUT | MUX_MODE6 | SLEWCONTROL | MODE_SELECT)   /* (A17) mcasp2_axr7.vout2_d15 */
			DRA7XX_CORE_IOPAD(0x3734, PIN_OUTPUT | MUX_MODE6 | SLEWCONTROL | MODE_SELECT)   /* (C18) mcasp4_aclkx.vout2_d16 */
			DRA7XX_CORE_IOPAD(0x3738, PIN_OUTPUT | MUX_MODE6 | SLEWCONTROL | MODE_SELECT)   /* (A21) mcasp4_fsx.vout2_d17 */
			DRA7XX_CORE_IOPAD(0x373c, PIN_OUTPUT | MUX_MODE6 | SLEWCONTROL | MODE_SELECT)   /* (G16) mcasp4_axr0.vout2_d18 */
			DRA7XX_CORE_IOPAD(0x3740, PIN_OUTPUT | MUX_MODE6 | SLEWCONTROL | MODE_SELECT)   /* (D17) mcasp4_axr1.vout2_d19 */
			DRA7XX_CORE_IOPAD(0x3744, PIN_OUTPUT | MUX_MODE6 | SLEWCONTROL | MODE_SELECT)   /* (AA3) mcasp5_aclkx.vout2_d20 */
			DRA7XX_CORE_IOPAD(0x3748, PIN_OUTPUT | MUX_MODE6 | SLEWCONTROL | MODE_SELECT)   /* (AB9) mcasp5_fsx.vout2_d21 */
			DRA7XX_CORE_IOPAD(0x374c, PIN_OUTPUT | MUX_MODE6 | SLEWCONTROL | MODE_SELECT)   /* (AB3) mcasp5_axr0.vout2_d22 */
			DRA7XX_CORE_IOPAD(0x3750, PIN_OUTPUT | MUX_MODE6 | SLEWCONTROL | MODE_SELECT)   /* (AA4) mcasp5_axr1.vout2_d23 */
		>;
	};

	mmc3_pins_default: mmc3_pins_default {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x377c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)	/* (AD4) mmc3_clk */
			DRA7XX_CORE_IOPAD(0x3780, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)	/* (AC4) mmc3_cmd */
			DRA7XX_CORE_IOPAD(0x3784, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)	/* (AC7) mmc3_dat0 */
			DRA7XX_CORE_IOPAD(0x3788, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)	/* (AC6) mmc3_dat1 */
			DRA7XX_CORE_IOPAD(0x378c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)	/* (AC9) mmc3_dat2 */
			DRA7XX_CORE_IOPAD(0x3790, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)	/* (AC3) mmc3_dat3 */
		>;
	};

	mmc3_pins_sleep: mmc3_pins_sleep {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x377c, PIN_INPUT_PULLDOWN | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x3780, PIN_INPUT_PULLDOWN | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x3784, PIN_INPUT_PULLDOWN | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x3788, PIN_INPUT_PULLDOWN | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x378c, PIN_INPUT_PULLDOWN | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x3790, PIN_INPUT_PULLDOWN | MUX_MODE15)
		>;
	};

	pcie1_pins: pcie1_pins {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x35e8, PIN_INPUT | MUX_MODE14)		/* (G11) vout1_d3.gpio8_3 */
			DRA7XX_CORE_IOPAD(0x35ec, PIN_OUTPUT_PULLDOWN | MUX_MODE14)	/* (E9) vout1_d4.gpio8_4 */
			DRA7XX_CORE_IOPAD(0x35f0, PIN_INPUT | MUX_MODE14)		/* (F9) vout1_d5.gpio8_5 */
			DRA7XX_CORE_IOPAD(0x35f8, PIN_OUTPUT | MUX_MODE14)		/* (E7) vout1_d7.gpio8_7 */
		>;
	};

	i2c3_pins_default: pinmux_i2c3_default {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3774, PIN_INPUT_PULLUP | MUX_MODE2)	/* (AC5) gpio6_10.i2c3_sda */
			DRA7XX_CORE_IOPAD(0x3778, PIN_INPUT_PULLUP | MUX_MODE2)	/* (AB4) gpio6_11.i2c3_scl */
		>;
	};

	i2c3_pins_sleep: pinmux_i2c3_sleep {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3774, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x3778, PIN_INPUT | MUX_MODE15)
		>;
	};
};

&dra7_iodelay_core {
	lcd_pins_iodelay_conf: lcd_pins_iodelay_conf {
		pinctrl-pin-array = <
			0xb6c A_DELAY_PS(2000) G_DELAY_PS(229)	/* CFG_VIN2A_DE0_OUT */
			0xb78 A_DELAY_PS(0) G_DELAY_PS(697)	/* CFG_VIN2A_FLD0_OUT */
			0xb84 A_DELAY_PS(2516) G_DELAY_PS(0)	/* CFG_VIN2A_HSYNC0_OUT */
			0xb90 A_DELAY_PS(1937) G_DELAY_PS(406)	/* CFG_VIN2A_VSYNC0_OUT */
			0x3b0 A_DELAY_PS(3116) G_DELAY_PS(360)	/* CFG_MCASP1_ACLKR_OUT */
			0x488 A_DELAY_PS(1170) G_DELAY_PS(1000)	/* CFG_MCASP1_FSR_OUT */
			0x428 A_DELAY_PS(1321) G_DELAY_PS(1250)	/* CFG_MCASP1_AXR2_OUT */
			0x434 A_DELAY_PS(1275) G_DELAY_PS(1020)	/* CFG_MCASP1_AXR3_OUT */
			0x440 A_DELAY_PS(1392) G_DELAY_PS(1360)	/* CFG_MCASP1_AXR4_OUT */
			0x44c A_DELAY_PS(2364) G_DELAY_PS(240)	/* CFG_MCASP1_AXR5_OUT */
			0x458 A_DELAY_PS(1480) G_DELAY_PS(1090)	/* CFG_MCASP1_AXR6_OUT */
			0x464 A_DELAY_PS(1307) G_DELAY_PS(1180)	/* CFG_MCASP1_AXR7_OUT */

			0x4a0 A_DELAY_PS(2983) G_DELAY_PS(240)	/* CFG_MCASP2_ACLKR_OUT */
			0x4b8 A_DELAY_PS(1721) G_DELAY_PS(120)	/* CFG_MCASP2_AXR0_OUT */
			0x4c4 A_DELAY_PS(1067) G_DELAY_PS(840)	/* CFG_MCASP2_AXR1_OUT */
			0x4e8 A_DELAY_PS(1093) G_DELAY_PS(1040)	/* CFG_MCASP2_AXR4_OUT */
			0x4f4 A_DELAY_PS(1810) G_DELAY_PS(240)	/* CFG_MCASP2_AXR5_OUT */
			0x500 A_DELAY_PS(2844) G_DELAY_PS(240)	/* CFG_MCASP2_AXR6_OUT */
			0x50c A_DELAY_PS(1608) G_DELAY_PS(120)	/* CFG_MCASP2_AXR7_OUT */
			0x518 A_DELAY_PS(980) G_DELAY_PS(536)	/* CFG_MCASP2_FSR_OUT */

			0x560 A_DELAY_PS(1635) G_DELAY_PS(1240)	/* CFG_MCASP4_ACLKX_OUT */
			0x56c A_DELAY_PS(1569) G_DELAY_PS(120)	/* CFG_MCASP4_AXR0_OUT */
			0x578 A_DELAY_PS(798) G_DELAY_PS(600)	/* CFG_MCASP4_AXR1_OUT */
			0x584 A_DELAY_PS(893) G_DELAY_PS(540)	/* CFG_MCASP4_FSX_OUT */

			0x590 A_DELAY_PS(4400) G_DELAY_PS(1820)	/* CFG_MCASP5_ACLKX_OUT */
			0x59c A_DELAY_PS(4640) G_DELAY_PS(980)	/* CFG_MCASP5_AXR0_OUT */
			0x5a8 A_DELAY_PS(4200) G_DELAY_PS(1120)	/* CFG_MCASP5_AXR1_OUT */
			0x5b4 A_DELAY_PS(4330) G_DELAY_PS(1160)	/* CFG_MCASP5_FSX_OUT */
		>;
	};

	mmc3_iodelay_conf: mmc3_iodelay_conf {
		pinctrl-pin-array = <
			0x678 A_DELAY_PS(406) G_DELAY_PS(0)	/* CFG_MMC3_CLK_IN */
			0x680 A_DELAY_PS(659) G_DELAY_PS(0)	/* CFG_MMC3_CLK_OUT */
			0x684 A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_MMC3_CMD_IN */
			0x688 A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_MMC3_CMD_OEN */
			0x68c A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_MMC3_CMD_OUT */
			0x690 A_DELAY_PS(130) G_DELAY_PS(0)	/* CFG_MMC3_DAT0_IN */
			0x694 A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_MMC3_DAT0_OEN */
			0x698 A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_MMC3_DAT0_OUT */
			0x69c A_DELAY_PS(169) G_DELAY_PS(0)	/* CFG_MMC3_DAT1_IN */
			0x6a0 A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_MMC3_DAT1_OEN */
			0x6a4 A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_MMC3_DAT1_OUT */
			0x6a8 A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_MMC3_DAT2_IN */
			0x6ac A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_MMC3_DAT2_OEN */
			0x6b0 A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_MMC3_DAT2_OUT */
			0x6b4 A_DELAY_PS(457) G_DELAY_PS(0)	/* CFG_MMC3_DAT3_IN */
			0x6b8 A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_MMC3_DAT3_OEN */
			0x6bc A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_MMC3_DAT3_OUT */
		>;
	};
};

/*
&phytec_leds {
	pinctrl-0 = <&leds_som_pins_default &leds_cb_pins_default>;

	led@2 {
		label = "am57xx-pcm-948:usr1";
		gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
		linux,default-trigger = "gpio";
		default-state = "off";
	};

	led@3 {
		label = "am57xx-pcm-948:usr2";
		gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
		linux,default-trigger = "gpio";
		default-state = "off";
	};
};
*/

&tps659038 {
	tps659038_usb: tps659038_usb {
		status = "okay";
		compatible = "ti,palmas-usb-vid";
		pinctrl-names = "default";
		pinctrl-0 = <&extcon_pins_default>;
		id-gpio = <&gpio8 6 GPIO_ACTIVE_HIGH>;
		vbus-gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;

		ti,enable-vbus-detection;
		ti,enable-id-detection;
	};
};

&i2c3 {
	status = "okay";
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&i2c3_pins_default>;
	pinctrl-1 = <&i2c3_pins_sleep>;
	clock-frequency = <400000>;
};

&i2c4 {
	status = "okay";
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&i2c4_pins_default>;
	pinctrl-1 = <&i2c4_pins_sleep>;
	clock-frequency = <400000>;

	tlv320aic3007: tlv320aic3007@18 {
		#sound-dai-cells = <0>;
		compatible = "ti,tlv320aic3007";
		reg = <0x18>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&clkout2_pins_default>;
		pinctrl-1 = <&clkout2_pins_sleep>;
		status = "okay";
		ai3x-micbias-vg = <2>;
		adc-settle-ms = <40>;

		AVDD-supply = <&vdd_3v3>;
		IOVDD-supply = <&vdd_3v3>;
		DRVDD-supply = <&vdd_3v3>;
		DVDD-supply = <&aic_dvdd>;
	};

	ft5x06: ft5x06@38 {
		pinctrl-names = "default";
		pinctrl-0 = <&edt_ts_irq_pin>;
		interrupt-parent = <&gpio8>;
		interrupts = <22 0>;
		status = "disabled";
	};

	stmpe811: stmpe811@41 {
		status = "disabled";
		compatible = "st,stmpe811";
		pinctrl-names = "default";
		pinctrl-0 = <&stmpe_ts_irq_pin>;

		reg = <0x41>;
		id = <0>;
		blocks = <0x5>;
		irq-gpio = <&gpio6 4 IRQ_TYPE_LEVEL_LOW>;
		wakeup-source;

		stmpe_touchscreen {
			compatible = "st,stmpe-ts";
			st,sample-time = <4>;
			st,mod-12b = <1>;
			st,ref-sel = <0>;
			st,adc-freq = <1>;
			st,ave-ctrl = <1>;
			st,touch-det-delay = <2>;
			st,settling = <2>;
			st,fraction-z = <7>;
			st,i-drive = <1>;
		};
	};
};

&uart3 {
        status = "okay";
        pinctrl-names = "default";
        pinctrl-0 = <&uart3_pins_default>;

	interrupts-extended = <&crossbar_mpu GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH
			       &dra7_pmx_core 0x248>;
};

&uart5 {
        status = "okay";
        pinctrl-names = "default", "sleep";
        pinctrl-0 = <&uart5_pins_default>;
        pinctrl-1 = <&uart5_pins_sleep>;

	interrupts-extended = <&crossbar_mpu GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH
			       &dra7_pmx_core 0x1dc>;
};

&uart10 {
        status = "disabled";
        pinctrl-names = "default", "sleep";
        pinctrl-0 = <&uart10_pins_default>;
        pinctrl-1 = <&uart10_pins_sleep>;
};

&uart6 {
       status = "okay";
       pinctrl-names = "default", "sleep";
       pinctrl-0 = <&uart6_pins_default>;
//     pinctrl-1 = <&uart6_pins_sleep>;

//     interrupts-extended = <&crossbar_mpu GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH
//                            &dra7_pmx_core 0x50>;
};


&mac {
	slaves = <2>;
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&emac0_pins_default &emac1_pins_default>;
	pinctrl-1 = <&emac0_pins_sleep &emac1_pins_sleep>;
	dual_emac;
};

&davinci_mdio {
	phy1: ethernet-phy@2 {
		reg = <2>;

		rxc-skew-ps = <1860>;
	};
};

&cpsw_emac1 {
	status = "okay";

	phy-handle = <&phy1>;
	phy-mode = "rgmii";
	dual_emac_res_vlan = <2>;
};

&mmc1 {
	status = "okay";
	pinctrl-names = "default", "sleep", "hs";
	pinctrl-0 = <&mmc1_pins_default &mmc1_cd_wp_pins>;
	pinctrl-1 = <&mmc1_pins_sleep>;
	pinctrl-2 = <&mmc1_pins_hs &mmc1_cd_wp_pins>;
	vmmc-supply = <&ldo1_reg>;
	bus-width = <4>;
	cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; /* gpio 219 */
	wp-gpios = <&gpio6 28 GPIO_ACTIVE_HIGH>;
	max-frequency = <96000000>;
	no-1-8-v;
};

&mmc3 {
        status = "disabled";
	pinctrl-names = "default", "sleep", "hs", "sdr12", "sdr25", "sdr50";
        pinctrl-0 = <&mmc3_pins_default &mmc3_iodelay_conf>;
        pinctrl-1 = <&mmc3_pins_sleep>;
        pinctrl-2 = <&mmc3_pins_default &mmc3_iodelay_conf>;
        pinctrl-3 = <&mmc3_pins_default &mmc3_iodelay_conf>;
        pinctrl-4 = <&mmc3_pins_default &mmc3_iodelay_conf>;
        pinctrl-5 = <&mmc3_pins_default &mmc3_iodelay_conf>;
	bus-width = <4>;

	#address-cells = <1>;
	#size-cells = <0>;
	wlcore: wlcore@0 {
		status = "disabled";

		interrupt-parent = <&gpio1>;
		interrupts = <25 IRQ_TYPE_EDGE_RISING>;
	};
};

&dss {
	status = "okay";

	vdda_video-supply = <&ldoln_reg>;

	ports {
		#address-cells = <1>;
		#size-cells = <0>;
		lcd_port: port@1 {
			status = "disabled";

			reg = <1>;
		};
	};
};

&hdmi {
	status = "okay";

	vdda-supply = <&ldo4_reg>;
	pinctrl-names = "default";
	pinctrl-0 = <&hdmi_pins &i2c2_pins>;

	port {
		hdmi_out: endpoint {
			remote-endpoint = <&tpd12s521_in>;
		};
	};
};

&pcie2_phy {
	status = "okay";
};

&pcie1_rc {
	status = "disabled";
	pinctrl-names = "default";
	pinctrl-0 = <&pcie1_pins>;

/* FIXME (RR): pci-dra7xx driver ignores the GPIO_ACTIVE_ flags
 *             and only cares about pcie-reset-active-low */
	pcie-reset-active-low;
	pcie-clk-oe-gpio = <&gpio8 7 GPIO_ACTIVE_HIGH>;
	pcie-reset-gpio = <&gpio8 4 GPIO_ACTIVE_LOW>; /* PWRGD (X27-A11) */

	num-lanes = <2>;
	phys = <&pcie1_phy>, <&pcie2_phy>;
	phy-names = "pcie-phy0", "pcie-phy1";
	syscon-dual-lane = <&scm_conf_pcie 0x18 0x5>;
};

&sata {
	ports-implemented = <1>;
};

&usb2_phy1 {
       phy-supply = <&ldousb_reg>;
};

&usb2_phy2 {
       phy-supply = <&ldousb_reg>;
};

&usb1 {
	status = "okay";
	dr_mode = "host";
	pinctrl-names = "default";
	pinctrl-0 = <&usb1_pins>;
};

&omap_dwc3_2 {
	status = "okay";
	extcon = <&tps659038_usb>;
};

&usb2 {
	status = "okay";
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&usb2_pins_default>;
	pinctrl-1 = <&usb2_pins_sleep>;

	dr_mode = "otg";
};

&dcan1 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&dcan1_pins>;
};

&dcan2 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&dcan2_pins>;
};

&mcasp1 {
	#sound-dai-cells = <0>;
	status = "okay";
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&mcasp1_pins_default>;
	pinctrl-1 = <&mcasp1_pins_sleep>;

	op-mode = <0>;  /* MCASP_IIS_MODE */
	tdm-slots = <2>;
	/* mcasp1_axr14 = TX, mcasp1_axr15 = RX */
	serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
		0 0 0 0
		0 0 0 0
		0 0 0 0
		0 0 1 2
	>;
	tx-num-evt = <32>;
	rx-num-evt = <32>;
};

&mcspi1 {
	spidev1_0: spidev1@0 {
		compatible = "linux,spidev";

		reg = <0>;
		spi-max-frequency = <48000000>;
	};
};

&cpu_trips {
	cpu_alert1: cpu_alert1 {
		temperature = <40000>; /* millicelsius */
		hysteresis = <2000>; /* millicelsius */
		type = "active";
	};
};

&cpu_cooling_maps {
	map1 {
		trip = <&cpu_alert1>;
		cooling-device = <&gpio_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	};
};

Hi Sujan,

I could not find am57xx-phycore-common.dtsi so there would be a lot of speculation. If you have a contact at PHYTEC, it might be good to also contact them to see if they can help as well, since I think they will have the most knowledge on their device tree and might be able to give better suggestions.

With the current information I have, a couple of suggestions:

1. Since the error logs look to be serdes phy related, please make sure pcie2_phy is defined and status is not disabled. If PHYTEC is including TI's default device tree, I see that pcie2_phy is disabled: https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel/tree/arch/arm/boot/dts/dra7.dtsi?h=ti-lsk-linux-4.9.y#n1615.
2. There are a couple of layers of dts/dtsi files, but please search for all device tree files that have pcie2_ep and pcie2_rc, and make sure that pcie2_rc is disabled, and pcie2_ep is enabled. Similarly for pcie2_phy.

Regards,

Takuma

Hi Sujan,

I will give comments about the other related thread: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1283265/am5728-dra7-pcie-probe-of-51800000-pcie_ep-failed-with-error--22

It looks like phy is probed using the following logic in pci-dra7xx.c:

Driver assumes pcie-phy%d is populated starting from pcie-phy0, pcie-phy1, pcie-phy2, etc.... so the first phy-names should always be pcie-phy0 instead of pcie-phy1. The reason why the probe error disappears is most likely because the dra7xx_pcie_probe function returns before it could try to initialize PHY and PCIe.

Regards,

Takuma

Hi Takuma,

Thanks for providing this information, it clarified my doubt and will also help with debugging.

We will keep the phy-names = "pcie-phy0";  & proceed debugging with the help of you earlier suggestion 

Thank you,

Sujan

Hi Takuma, 

I tried enabling the pcie2_phy in both dra7.dtsi and am57xx-phycore-common.dtsi simultaneously, and i still got the probe error as mentioned in the other thread.

I also disabled pcie2_rc and enabled pcie2_ep everywhere inside dts directory, wherever it was present & still got probe error.

Can you specify which couple of layers where I need to modify dts/dtsi files too, I will try that.

And do you have any other suggestions, as to why the probe error is occurring ? So we can try to focus on debugging that.

Thanks,

Sujan

Hi Sujan,

With the pcie2_phy enabled, could you share the full dmesg logs? I would like to see if there are errors before the PCIe related logs with the changes.

As for the device tree modifications, I am not quite sure what PHYTEC has for their device tree structure, but as an example from what TI provides, dra7.dtsi is included by dra74.dtsi, which is further included by dra7-evm.dtsi that includes other dtsi files. Similarly, please check the device tree provided by PHYTEC to see if the serdes or PCIe nodes are not modified incorrectly. If you would like more specific suggestions for the PHYTEC board, my recommendation would be to try to get PHYTEC support, as the knowledge we have will be based off of the SDK and board specific device trees that TI provides.

Regards,

Takuma

Hi Takuma, 

Here is the dmesg log : 

root@am57xx-phycore-kit:~# dmesg | grep pci
[ 0.541618] dra7-pcie 51800000.pcie_ep: Linked as a consumer to phy-4a095000.pciephy.2
[ 0.541789] dra7-pcie 51800000.pcie_ep: GPIO lookup for consumer pcie-clk-oe
[ 0.541797] dra7-pcie 51800000.pcie_ep: using device tree for GPIO lookup
[ 0.541817] of_get_named_gpiod_flags: can't parse 'pcie-clk-oe-gpios' property of node '/ocp/axi@1/pcie_ep@51800000[0]'
[ 0.541832] of_get_named_gpiod_flags: can't parse 'pcie-clk-oe-gpio' property of node '/ocp/axi@1/pcie_ep@51800000[0]'
[ 0.541842] dra7-pcie 51800000.pcie_ep: using lookup tables for GPIO lookup
[ 0.541850] dra7-pcie 51800000.pcie_ep: No GPIO consumer pcie-clk-oe found
[ 0.541859] dra7-pcie 51800000.pcie_ep: GPIO lookup for consumer pcie-reset
[ 0.541865] dra7-pcie 51800000.pcie_ep: using device tree for GPIO lookup
[ 0.541880] of_get_named_gpiod_flags: can't parse 'pcie-reset-gpios' property of node '/ocp/axi@1/pcie_ep@51800000[0]'
[ 0.541893] of_get_named_gpiod_flags: can't parse 'pcie-reset-gpio' property of node '/ocp/axi@1/pcie_ep@51800000[0]'
[ 0.541901] dra7-pcie 51800000.pcie_ep: using lookup tables for GPIO lookup
[ 0.541908] dra7-pcie 51800000.pcie_ep: No GPIO consumer pcie-reset found
[ 0.542045] dra7-pcie 51800000.pcie_ep: Dropping the link to phy-4a095000.pciephy.2
[ 0.542087] dra7-pcie: probe of 51800000.pcie_ep failed with error -22

We are in contact with PHYTEC support, so any information would be very helpful.

Thanks & Regards,
Sujan

Hi Sujan,

Could you share the full dmesg log without "| grep pci", similar to the post from Nov 8?

For AM6x devices, I find that serdes driver usually does not have "pci" in the log messages, so I would like to see the full dmesg logs in case serdes related error logs are being left out by grepping for pci.

Regards,

Takuma

Hi Takuma,

Sorry I've not had access to board for awhile, But here are the logs : 

dmesg_after_pcie_phy.txt

Regards,
Sujan

Hi Sujan,

Thanks for sharing. It looks like there are no extra error messages that looks to be related to the PCIe issue. However, I was looking through some other related threads and came upon this thread that is trying to configure PCIe2 as RC: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/873372/am5728-pcie-gen1-mode-configuration

From this thread, one thing that seems unique for PCIe2 is: "disable omap_dwc3_1 node, because it also uses the serdes which pcir2_phy node points to."

So if dwc3_1 node, which I think is USB, is enabled somewhere in the unshared device trees, could you try adding the disabled status to this node? If dwc3_1 is already disabled, as an experiment, could you disable all USB related nodes, including omap_dwc3_2, usb1, usb2, etc?

Regards,

Takuma

Hi Takuma,

I tried disabling all the dwc nodes i could find, but the probe error still persists.

Here is dmesg:

root@am57xx-phycore-kit:~# dmesg
[    0.000000] Booting Linux on physical CPU 0x0
[    0.000000] Linux version 4.19.79-g8177f87071 (oe-user@oe-host) (gcc version 8.3.0 (GNU Toolchain for the A-profile Architecture 8.3-2019.03 (arm-rel-8.36))) #1 SMP PREEMPT Thu Oct 12 11:01:32 UTC 2023
[    0.000000] CPU: ARMv7 Processor [412fc0f2] revision 2 (ARMv7), cr=30c5387d
[    0.000000] CPU: div instructions available: patching division code
[    0.000000] CPU: PIPT / VIPT nonaliasing data cache, PIPT instruction cache
[    0.000000] OF: fdt: Machine model: PHYTEC phyCORE-AM5728 with 2GiB (banks) DDR3, Industrial Temp
[    0.000000] Memory policy: Data cache writealloc
[    0.000000] efi: Getting EFI parameters from FDT:
[    0.000000] efi: UEFI not found.
[    0.000000] Reserved memory: created CMA memory pool at 0x0000000095000000, size 8 MiB
[    0.000000] OF: reserved mem: initialized node dsp2-memory@95000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created CMA memory pool at 0x0000000095800000, size 32 MiB
[    0.000000] OF: reserved mem: initialized node ipu1-memory@95800000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created CMA memory pool at 0x0000000097800000, size 64 MiB
[    0.000000] OF: reserved mem: initialized node dsp1-memory@97800000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created CMA memory pool at 0x000000009b800000, size 56 MiB
[    0.000000] OF: reserved mem: initialized node ipu2-memory@9b800000, compatible id shared-dma-pool
[    0.000000] cma: Reserved 24 MiB at 0x00000000fd400000
[    0.000000] OMAP4: Map 0x00000000fed00000 to (ptrval) for dram barrier
[    0.000000] On node 0 totalpages: 470272
[    0.000000]   DMA zone: 1728 pages used for memmap
[    0.000000]   DMA zone: 0 pages reserved
[    0.000000]   DMA zone: 147456 pages, LIFO batch:31
[    0.000000]   HighMem zone: 322816 pages, LIFO batch:63
[    0.000000] DRA752 ES2.0
[    0.000000] random: get_random_bytes called from start_kernel+0xb4/0x470 with crng_init=0
[    0.000000] percpu: Embedded 15 pages/cpu s32396 r8192 d20852 u61440
[    0.000000] pcpu-alloc: s32396 r8192 d20852 u61440 alloc=15*4096
[    0.000000] pcpu-alloc: [0] 0 [0] 1
[    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 468544
[    0.000000] Kernel command line: console=ttyS2,115200n8 root=PARTUUID=1565eb9b-e4e5-eb47-983a-66e8efc33d6b rw rootfstype=ext4 rootwait
[    0.000000] Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
[    0.000000] Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
[    0.000000] Memory: 1657356K/1881088K available (10240K kernel code, 327K rwdata, 2760K rodata, 2048K init, 269K bss, 35316K reserved, 188416K cma-reserved, 1266688K highmem)
[    0.000000] Virtual kernel memory layout:
                   vector  : 0xffff0000 - 0xffff1000   (   4 kB)
                   fixmap  : 0xffc00000 - 0xfff00000   (3072 kB)
                   vmalloc : 0xf0800000 - 0xff800000   ( 240 MB)
                   lowmem  : 0xc0000000 - 0xf0000000   ( 768 MB)
                   pkmap   : 0xbfe00000 - 0xc0000000   (   2 MB)
                   modules : 0xbf000000 - 0xbfe00000   (  14 MB)
                     .text : 0x(ptrval) - 0x(ptrval)   (12256 kB)
                     .init : 0x(ptrval) - 0x(ptrval)   (2048 kB)
                     .data : 0x(ptrval) - 0x(ptrval)   ( 328 kB)
                      .bss : 0x(ptrval) - 0x(ptrval)   ( 270 kB)
[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1
[    0.000000] rcu: Preemptible hierarchical RCU implementation.
[    0.000000]  Tasks RCU enabled.
[    0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
[    0.000000] GIC: Using split EOI/Deactivate mode
[    0.000000] OMAP clockevent source: timer1 at 32786 Hz
[    0.000000] arch_timer: cp15 timer(s) running at 6.14MHz (phys).
[    0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x16af5adb9, max_idle_ns: 440795202250 ns
[    0.000005] sched_clock: 56 bits at 6MHz, resolution 162ns, wraps every 4398046511023ns
[    0.000018] Switching to timer-based delay loop, resolution 162ns
[    0.000324] clocksource: 32k_counter: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 58327039986419 ns
[    0.000334] OMAP clocksource: 32k_counter at 32768 Hz
[    0.000876] Console: colour dummy device 80x30
[    0.000920] Calibrating delay loop (skipped), value calculated using timer frequency.. 12.29 BogoMIPS (lpj=61475)
[    0.000937] pid_max: default: 32768 minimum: 301
[    0.001057] Mount-cache hash table entries: 2048 (order: 1, 8192 bytes)
[    0.001071] Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes)
[    0.001634] CPU: Testing write buffer coherency: ok
[    0.001672] CPU0: Spectre v2: using ICIALLU workaround
[    0.001881] /cpus/cpu@0 missing clock-frequency property
[    0.001901] /cpus/cpu@1 missing clock-frequency property
[    0.001914] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
[    0.059884] Setting up static identity map for 0x80200000 - 0x80200060
[    0.079889] rcu: Hierarchical SRCU implementation.
[    0.100083] EFI services will not be available.
[    0.119948] smp: Bringing up secondary CPUs ...
[    0.200327] CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
[    0.200333] CPU1: Spectre v2: using ICIALLU workaround
[    0.200454] smp: Brought up 1 node, 2 CPUs
[    0.200467] SMP: Total of 2 processors activated (24.59 BogoMIPS).
[    0.200476] CPU: All CPU(s) started in HYP mode.
[    0.200483] CPU: Virtualization extensions available.
[    0.201039] devtmpfs: initialized
[    0.222783] VFP support v0.3: implementor 41 architecture 4 part 30 variant f rev 0
[    0.223044] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
[    0.223062] futex hash table entries: 512 (order: 3, 32768 bytes)
[    0.226138] pinctrl core: initialized pinctrl subsystem
[    0.226658] DMI not present or invalid.
[    0.226935] NET: Registered protocol family 16
[    0.228070] DMA: preallocated 256 KiB pool for atomic coherent allocations
[    0.229142] omap_hwmod: l3_main_2 using broken dt data from ocp
[    0.438928] cpuidle: using governor ladder
[    0.438964] cpuidle: using governor menu
[    0.449360] gpio gpiochip0: (gpio-0-31): added GPIO chardev (254:0)
[    0.449427] gpiochip_setup_dev: registered GPIOs 0 to 31 on device: gpiochip0 (gpio-0-31)
[    0.449471] OMAP GPIO hardware version 0.1
[    0.450092] gpio gpiochip1: (gpio-32-63): added GPIO chardev (254:1)
[    0.450162] gpiochip_setup_dev: registered GPIOs 32 to 63 on device: gpiochip1 (gpio-32-63)
[    0.450814] gpio gpiochip2: (gpio-64-95): added GPIO chardev (254:2)
[    0.450886] gpiochip_setup_dev: registered GPIOs 64 to 95 on device: gpiochip2 (gpio-64-95)
[    0.451500] gpio gpiochip3: (gpio-96-127): added GPIO chardev (254:3)
[    0.451565] gpiochip_setup_dev: registered GPIOs 96 to 127 on device: gpiochip3 (gpio-96-127)
[    0.452195] gpio gpiochip4: (gpio-128-159): added GPIO chardev (254:4)
[    0.452259] gpiochip_setup_dev: registered GPIOs 128 to 159 on device: gpiochip4 (gpio-128-159)
[    0.452888] gpio gpiochip5: (gpio-160-191): added GPIO chardev (254:5)
[    0.452955] gpiochip_setup_dev: registered GPIOs 160 to 191 on device: gpiochip5 (gpio-160-191)
[    0.453596] gpio gpiochip6: (gpio-192-223): added GPIO chardev (254:6)
[    0.453670] gpiochip_setup_dev: registered GPIOs 192 to 223 on device: gpiochip6 (gpio-192-223)
[    0.454301] gpio gpiochip7: (gpio-224-255): added GPIO chardev (254:7)
[    0.454366] gpiochip_setup_dev: registered GPIOs 224 to 255 on device: gpiochip7 (gpio-224-255)
[    0.477731] No ATAGs?
[    0.477803] hw-breakpoint: found 5 (+1 reserved) breakpoint and 4 watchpoint registers.
[    0.477819] hw-breakpoint: maximum watchpoint size is 8 bytes.
[    0.478669] OMAP DMA hardware revision 0.0
[    0.489734] edma 43300000.edma: memcpy is disabled
[    0.493205] edma 43300000.edma: TI EDMA DMA engine driver
[    0.500393] omap-dma-engine 4a056000.dma-controller: OMAP DMA engine driver (LinkedList1/2/3 supported)
[    0.501005] of_get_named_gpiod_flags: can't parse 'gpio' property of node '/fixedregulator-vdd_3v3[0]'
[    0.501250] of_get_named_gpiod_flags: can't parse 'gpio' property of node '/fixedregulator-aic_dvdd[0]'
[    0.501515] of_get_named_gpiod_flags: parsed 'gpio' property of node '/fixedregulator-vtt[0]' - status (0)
[    0.501800] of_get_named_gpiod_flags: can't parse 'gpio' property of node '/fixedregulator-vcc_3v3[0]'
[    0.502039] of_get_named_gpiod_flags: can't parse 'gpio' property of node '/fixedregulator-vcc_5v0[0]'
[    0.504820] omap-iommu 40d01000.mmu: 40d01000.mmu registered
[    0.505000] omap-iommu 40d02000.mmu: 40d02000.mmu registered
[    0.505237] omap-iommu 58882000.mmu: 58882000.mmu registered
[    0.505471] omap-iommu 55082000.mmu: 55082000.mmu registered
[    0.505846] omap-iommu 41501000.mmu: 41501000.mmu registered
[    0.506020] omap-iommu 41502000.mmu: 41502000.mmu registered
[    0.506330] iommu: Adding device 58820000.ipu to group 1
[    0.506413] iommu: Adding device 55020000.ipu to group 2
[    0.506546] iommu: Adding device 40800000.dsp to group 0
[    0.506797] iommu: Adding device 41000000.dsp to group 3
[    0.508546] media: Linux media interface: v0.10
[    0.508584] videodev: Linux video capture interface: v2.00
[    0.508652] pps_core: LinuxPPS API ver. 1 registered
[    0.508661] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
[    0.508681] PTP clock support registered
[    0.508710] EDAC MC: Ver: 3.0.0
[    0.509257] omap-mailbox: probe of 4883c000.mailbox failed with error -22
[    0.509323] omap-mailbox: probe of 4883e000.mailbox failed with error -22
[    0.509546] omap-mailbox 48840000.mailbox: omap mailbox rev 0x400
[    0.509796] omap-mailbox 48842000.mailbox: omap mailbox rev 0x400
[    0.510169] Advanced Linux Sound Architecture Driver Initialized.
[    0.511023] clocksource: Switched to clocksource arch_sys_counter
[    0.519449] NET: Registered protocol family 2
[    0.520030] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 6144 bytes)
[    0.520060] TCP established hash table entries: 8192 (order: 3, 32768 bytes)
[    0.520124] TCP bind hash table entries: 8192 (order: 4, 65536 bytes)
[    0.520250] TCP: Hash tables configured (established 8192 bind 8192)
[    0.520321] UDP hash table entries: 512 (order: 2, 16384 bytes)
[    0.520356] UDP-Lite hash table entries: 512 (order: 2, 16384 bytes)
[    0.520548] NET: Registered protocol family 1
[    0.541059] RPC: Registered named UNIX socket transport module.
[    0.541070] RPC: Registered udp transport module.
[    0.541079] RPC: Registered tcp transport module.
[    0.541087] RPC: Registered tcp NFSv4.1 backchannel transport module.
[    0.541098] PCI: CLS 0 bytes, default 64
[    0.542139] hw perfevents: no interrupt-affinity property for /pmu, guessing.
[    0.542347] hw perfevents: enabled with armv7_cortex_a15 PMU driver, 7 counters available
[    0.543344] Initialise system trusted keyrings
[    0.543472] workingset: timestamp_bits=14 max_order=19 bucket_order=5
[    0.548418] squashfs: version 4.0 (2009/01/31) Phillip Lougher
[    0.558912] NFS: Registering the id_resolver key type
[    0.558932] Key type id_resolver registered
[    0.558942] Key type id_legacy registered
[    0.558979] ntfs: driver 2.1.32 [Flags: R/W].
[    0.559195] jffs2: version 2.2. (NAND) \xc2\xa9 2001-2006 Red Hat, Inc.
[    0.561118] NET: Registered protocol family 38
[    0.561131] Key type asymmetric registered
[    0.561141] Asymmetric key parser 'x509' registered
[    0.561188] bounce: pool size: 64 pages
[    0.561222] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 245)
[    0.561233] io scheduler noop registered
[    0.561242] io scheduler deadline registered
[    0.561339] io scheduler cfq registered (default)
[    0.561350] io scheduler mq-deadline registered
[    0.561359] io scheduler kyber registered
[    0.567200] pinctrl-single 4a003400.pinmux: 282 pins, size 1128
[    0.571298] dra7-pcie 51800000.pcie_ep: Linked as a consumer to phy-4a095000.pciephy.2
[    0.571470] dra7-pcie 51800000.pcie_ep: GPIO lookup for consumer pcie-clk-oe
[    0.571478] dra7-pcie 51800000.pcie_ep: using device tree for GPIO lookup
[    0.571497] of_get_named_gpiod_flags: can't parse 'pcie-clk-oe-gpios' property of node '/ocp/axi@1/pcie_ep@51800000[0]'
[    0.571512] of_get_named_gpiod_flags: can't parse 'pcie-clk-oe-gpio' property of node '/ocp/axi@1/pcie_ep@51800000[0]'
[    0.571520] dra7-pcie 51800000.pcie_ep: using lookup tables for GPIO lookup
[    0.571529] dra7-pcie 51800000.pcie_ep: No GPIO consumer pcie-clk-oe found
[    0.571538] dra7-pcie 51800000.pcie_ep: GPIO lookup for consumer pcie-reset
[    0.571544] dra7-pcie 51800000.pcie_ep: using device tree for GPIO lookup
[    0.571559] of_get_named_gpiod_flags: can't parse 'pcie-reset-gpios' property of node '/ocp/axi@1/pcie_ep@51800000[0]'
[    0.571573] of_get_named_gpiod_flags: can't parse 'pcie-reset-gpio' property of node '/ocp/axi@1/pcie_ep@51800000[0]'
[    0.571580] dra7-pcie 51800000.pcie_ep: using lookup tables for GPIO lookup
[    0.571587] dra7-pcie 51800000.pcie_ep: No GPIO consumer pcie-reset found
[    0.571724] dra7-pcie 51800000.pcie_ep: Dropping the link to phy-4a095000.pciephy.2
[    0.571766] dra7-pcie: probe of 51800000.pcie_ep failed with error -22
[    0.572680] pwm-backlight backlight: GPIO lookup for consumer enable
[    0.572688] pwm-backlight backlight: using device tree for GPIO lookup
[    0.572704] of_get_named_gpiod_flags: can't parse 'enable-gpios' property of node '/backlight[0]'
[    0.572717] of_get_named_gpiod_flags: can't parse 'enable-gpio' property of node '/backlight[0]'
[    0.572725] pwm-backlight backlight: using lookup tables for GPIO lookup
[    0.572732] pwm-backlight backlight: No GPIO consumer enable found
[    0.572750] pwm-backlight backlight: backlight supply power not found, using dummy regulator
[    0.572822] pwm-backlight backlight: Linked as a consumer to regulator.0
[    0.621567] Serial: 8250/16550 driver, 10 ports, IRQ sharing enabled
[    0.625221] console [ttyS2] disabled
[    0.625274] 48020000.serial: ttyS2 at MMIO 0x48020000 (irq = 44, base_baud = 3000000) is a 8250
[    1.550078] console [ttyS2] enabled
[    1.554610] 48066000.serial: ttyS4 at MMIO 0x48066000 (irq = 45, base_baud = 3000000) is a 8250
[    1.564299] 48068000.serial: ttyS5 at MMIO 0x48068000 (irq = 46, base_baud = 3000000) is a 8250
[    1.574016] 4ae2b000.serial: ttyS9 at MMIO 0x4ae2b000 (irq = 47, base_baud = 3000000) is a 8250
[    1.586112] tpd12s015 encoder@0: GPIO lookup for consumer (null)
[    1.586120] tpd12s015 encoder@0: using device tree for GPIO lookup
[    1.586137] of_get_named_gpiod_flags: can't parse 'gpios' property of node '/encoder@0[0]'
[    1.586151] of_get_named_gpiod_flags: can't parse 'gpio' property of node '/encoder@0[0]'
[    1.586160] tpd12s015 encoder@0: using lookup tables for GPIO lookup
[    1.586168] tpd12s015 encoder@0: No GPIO consumer (null) found
[    1.586176] tpd12s015 encoder@0: GPIO lookup for consumer (null)
[    1.586182] tpd12s015 encoder@0: using device tree for GPIO lookup
[    1.586195] of_get_named_gpiod_flags: can't parse 'gpios' property of node '/encoder@0[1]'
[    1.586208] of_get_named_gpiod_flags: can't parse 'gpio' property of node '/encoder@0[1]'
[    1.586216] tpd12s015 encoder@0: using lookup tables for GPIO lookup
[    1.586222] tpd12s015 encoder@0: No GPIO consumer (null) found
[    1.586230] tpd12s015 encoder@0: GPIO lookup for consumer (null)
[    1.586236] tpd12s015 encoder@0: using device tree for GPIO lookup
[    1.586262] of_get_named_gpiod_flags: parsed 'gpios' property of node '/encoder@0[2]' - status (0)
[    1.586299] gpio gpiochip6: Persistence not supported for GPIO 12
[    1.587119] connector-hdmi connector@0: GPIO lookup for consumer hpd
[    1.587127] connector-hdmi connector@0: using device tree for GPIO lookup
[    1.587145] of_get_named_gpiod_flags: can't parse 'hpd-gpios' property of node '/connector@0[0]'
[    1.587158] of_get_named_gpiod_flags: can't parse 'hpd-gpio' property of node '/connector@0[0]'
[    1.587166] connector-hdmi connector@0: using lookup tables for GPIO lookup
[    1.587174] connector-hdmi connector@0: No GPIO consumer hpd found
[    1.591257] ti-iodelay 4844a000.padconf: Set reg 0xb6c Delay(a: 2000 g: 229), Elements(C=4 F=4)0x29084
[    1.600615] ti-iodelay 4844a000.padconf: Set reg 0xb78 Delay(a: 0 g: 697), Elements(C=0 F=11)0x2900b
[    1.609821] ti-iodelay 4844a000.padconf: Set reg 0xb84 Delay(a: 2516 g: 0), Elements(C=5 F=1)0x290a1
[    1.619025] ti-iodelay 4844a000.padconf: Set reg 0xb90 Delay(a: 1937 g: 406), Elements(C=3 F=19)0x29073
[    1.628485] ti-iodelay 4844a000.padconf: Set reg 0x3b0 Delay(a: 3116 g: 360), Elements(C=6 F=10)0x290ca
[    1.637943] ti-iodelay 4844a000.padconf: Set reg 0x488 Delay(a: 1170 g: 1000), Elements(C=3 F=6)0x29066
[    1.647401] ti-iodelay 4844a000.padconf: Set reg 0x428 Delay(a: 1321 g: 1250), Elements(C=3 F=14)0x2906e
[    1.656944] ti-iodelay 4844a000.padconf: Set reg 0x434 Delay(a: 1275 g: 1020), Elements(C=3 F=9)0x29069
[    1.666405] ti-iodelay 4844a000.padconf: Set reg 0x440 Delay(a: 1392 g: 1360), Elements(C=3 F=18)0x29072
[    1.675949] ti-iodelay 4844a000.padconf: Set reg 0x44c Delay(a: 2364 g: 240), Elements(C=4 F=14)0x2908e
[    1.685405] ti-iodelay 4844a000.padconf: Set reg 0x458 Delay(a: 1480 g: 1090), Elements(C=3 F=16)0x29070
[    1.694949] ti-iodelay 4844a000.padconf: Set reg 0x464 Delay(a: 1307 g: 1180), Elements(C=3 F=13)0x2906d
[    1.704490] ti-iodelay 4844a000.padconf: Set reg 0x4a0 Delay(a: 2983 g: 240), Elements(C=6 F=4)0x290c4
[    1.713857] ti-iodelay 4844a000.padconf: Set reg 0x4b8 Delay(a: 1721 g: 120), Elements(C=3 F=8)0x29068
[    1.723230] ti-iodelay 4844a000.padconf: Set reg 0x4c4 Delay(a: 1067 g: 840), Elements(C=2 F=16)0x29050
[    1.732682] ti-iodelay 4844a000.padconf: Set reg 0x4e8 Delay(a: 1093 g: 1040), Elements(C=3 F=4)0x29064
[    1.742136] ti-iodelay 4844a000.padconf: Set reg 0x4f4 Delay(a: 1810 g: 240), Elements(C=3 F=13)0x2906d
[    1.751590] ti-iodelay 4844a000.padconf: Set reg 0x500 Delay(a: 2844 g: 240), Elements(C=5 F=14)0x290ae
[    1.761045] ti-iodelay 4844a000.padconf: Set reg 0x50c Delay(a: 1608 g: 120), Elements(C=3 F=5)0x29065
[    1.770398] ti-iodelay 4844a000.padconf: Set reg 0x518 Delay(a: 980 g: 536), Elements(C=1 F=22)0x29036
[    1.779764] ti-iodelay 4844a000.padconf: Set reg 0x560 Delay(a: 1635 g: 1240), Elements(C=4 F=9)0x29089
[    1.789219] ti-iodelay 4844a000.padconf: Set reg 0x56c Delay(a: 1569 g: 120), Elements(C=3 F=4)0x29064
[    1.798586] ti-iodelay 4844a000.padconf: Set reg 0x578 Delay(a: 798 g: 600), Elements(C=1 F=18)0x29032
[    1.807952] ti-iodelay 4844a000.padconf: Set reg 0x584 Delay(a: 893 g: 540), Elements(C=1 F=20)0x29034
[    1.817316] ti-iodelay 4844a000.padconf: Set reg 0x590 Delay(a: 4400 g: 1820), Elements(C=10 F=12)0x2914c
[    1.826943] ti-iodelay 4844a000.padconf: Set reg 0x59c Delay(a: 4640 g: 980), Elements(C=10 F=6)0x29146
[    1.836394] ti-iodelay 4844a000.padconf: Set reg 0x5a8 Delay(a: 4200 g: 1120), Elements(C=9 F=9)0x29129
[    1.845845] ti-iodelay 4844a000.padconf: Set reg 0x5b4 Delay(a: 4330 g: 1160), Elements(C=9 F=14)0x2912e
[    1.855458] panel-simple display: display supply power not found, using dummy regulator
[    1.863569] panel-simple display: Linked as a consumer to regulator.0
[    1.870044] panel-simple display: GPIO lookup for consumer enable
[    1.870050] panel-simple display: using device tree for GPIO lookup
[    1.870078] of_get_named_gpiod_flags: parsed 'enable-gpios' property of node '/display[0]' - status (0)
[    1.870112] gpio gpiochip7: Persistence not supported for GPIO 23
[    1.878285] brd: module loaded
[    1.887638] loop: module loaded
[    1.894474] spidev spi1.0: buggy DT: spidev listed directly in DT
[    1.900597] ------------[ cut here ]------------
[    1.905278] WARNING: CPU: 0 PID: 1 at drivers/spi/spidev.c:730 spidev_probe+0x1c8/0x1dc
[    1.913347] Modules linked in:
[    1.916424] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.19.79-g8177f87071 #1
[    1.923505] Hardware name: Generic DRA74X (Flattened Device Tree)
[    1.929624] Backtrace:
[    1.932095] [<c020ca34>] (dump_backtrace) from [<c020cd6c>] (show_stack+0x18/0x1c)
[    1.939702]  r7:c0e2ab28 r6:60000013 r5:00000000 r4:c124e51c
[    1.945393] [<c020cd54>] (show_stack) from [<c09fb3a0>] (dump_stack+0x90/0xa4)
[    1.952653] [<c09fb310>] (dump_stack) from [<c022e098>] (__warn+0xdc/0xf8)
[    1.959558]  r7:c0e2ab28 r6:00000009 r5:00000000 r4:00000000
[    1.965246] [<c022dfbc>] (__warn) from [<c022e0fc>] (warn_slowpath_null+0x48/0x50)
[    1.972851]  r9:c123a8a8 r8:00000000 r7:00000000 r6:c07458b8 r5:000002da r4:c0e2ab28
[    1.980635] [<c022e0b4>] (warn_slowpath_null) from [<c07458b8>] (spidev_probe+0x1c8/0x1dc)
[    1.988937]  r6:c123a898 r5:edc4e400 r4:edc4e400
[    1.993577] [<c07456f0>] (spidev_probe) from [<c0741c0c>] (spi_drv_probe+0x84/0xa8)
[    2.001267]  r9:c123a8a8 r8:00000000 r7:00000000 r6:c123a898 r5:00000000 r4:edc4e400
[    2.009049] [<c0741b88>] (spi_drv_probe) from [<c06d66f0>] (really_probe+0x204/0x2c0)
[    2.016912]  r7:00000000 r6:c128b5b8 r5:edc4e400 r4:c128b5b4
[    2.022600] [<c06d64ec>] (really_probe) from [<c06d6950>] (driver_probe_device+0x68/0x180)
[    2.030904]  r10:00000000 r9:c128b590 r8:00000001 r7:c06d6b60 r6:edc4e400 r5:c123a8a8
[    2.038766]  r4:edc4e400 r3:00000000
[    2.042359] [<c06d68e8>] (driver_probe_device) from [<c06d6c04>] (__device_attach_driver+0xa4/0xc8)
[    2.051446]  r9:c128b590 r8:00000001 r7:c06d6b60 r6:edc4e400 r5:ee88fbb4 r4:c123a8a8
[    2.059229] [<c06d6b60>] (__device_attach_driver) from [<c06d48a8>] (bus_for_each_drv+0x88/0xcc)
[    2.068052]  r7:c06d6b60 r6:ee88fbb4 r5:c1204c48 r4:00000000
[    2.073739] [<c06d4820>] (bus_for_each_drv) from [<c06d646c>] (__device_attach+0xd8/0x140)
[    2.082039]  r7:edc4e000 r6:edc4e434 r5:c1204c48 r4:edc4e400
[    2.087725] [<c06d6394>] (__device_attach) from [<c06d6c74>] (device_initial_probe+0x14/0x18)
[    2.096287]  r8:edc4e400 r7:edc4e000 r6:c123a2e8 r5:edc4e400 r4:edc4e408
[    2.103022] [<c06d6c60>] (device_initial_probe) from [<c06d57d4>] (bus_probe_device+0x8c/0x94)
[    2.111677] [<c06d5748>] (bus_probe_device) from [<c06d233c>] (device_add+0x37c/0x620)
[    2.119627]  r7:edc4e000 r6:00000000 r5:c1204c48 r4:edc4e408
[    2.125315] [<c06d1fc0>] (device_add) from [<c0742888>] (spi_add_device+0xa0/0x134)
[    2.133006]  r10:c0e2ac28 r9:00000000 r8:edc4e000 r7:eeaea210 r6:00000000 r5:edc4e000
[    2.140867]  r4:edc4e400
[    2.143415] [<c07427e8>] (spi_add_device) from [<c0742c58>] (of_register_spi_device+0x25c/0x394)
[    2.152240]  r7:00000001 r6:c1204c48 r5:eedaa970 r4:edc4e400
[    2.157927] [<c07429fc>] (of_register_spi_device) from [<c0743330>] (spi_register_controller+0x338/0x65c)
[    2.167539]  r9:c0e2a6bc r8:c1204c48 r7:eedaa9c0 r6:eedaa970 r5:00000000 r4:edc4e000
[    2.175321] [<c0742ff8>] (spi_register_controller) from [<c0743694>] (devm_spi_register_controller+0x40/0x78)
[    2.185279]  r10:c0e2ac28 r9:00000000 r8:00000000 r7:eeaea210 r6:edc4e000 r5:edc4e000
[    2.193141]  r4:edc354c0
[    2.195690] [<c0743654>] (devm_spi_register_controller) from [<c0747250>] (omap2_mcspi_probe+0x4b4/0x560)
[    2.205297]  r7:00000000 r6:edc4e000 r5:edc4e340 r4:edc4e000
[    2.210986] [<c0746d9c>] (omap2_mcspi_probe) from [<c06d86a0>] (platform_drv_probe+0x50/0xa0)
[    2.219551]  r10:00000000 r9:c123a900 r8:00000000 r7:00000000 r6:c123a900 r5:00000000
[    2.227412]  r4:eeaea210
[    2.229958] [<c06d8650>] (platform_drv_probe) from [<c06d66f0>] (really_probe+0x204/0x2c0)
[    2.238259]  r7:00000000 r6:c128b5b8 r5:eeaea210 r4:c128b5b4
[    2.243945] [<c06d64ec>] (really_probe) from [<c06d6950>] (driver_probe_device+0x68/0x180)
[    2.252248]  r10:c105efe0 r9:c104a834 r8:00000000 r7:c06d6a68 r6:eeaea244 r5:c123a900
[    2.260110]  r4:eeaea210 r3:00000000
[    2.263704] [<c06d68e8>] (driver_probe_device) from [<c06d6b5c>] (__driver_attach+0xf4/0xf8)
[    2.272179]  r9:c104a834 r8:00000000 r7:c06d6a68 r6:eeaea244 r5:c123a900 r4:eeaea210
[    2.279958] [<c06d6a68>] (__driver_attach) from [<c06d47bc>] (bus_for_each_dev+0x7c/0xbc)
[    2.288171]  r7:c06d6a68 r6:c123a900 r5:c1204c48 r4:eead4134
[    2.293860] [<c06d4740>] (bus_for_each_dev) from [<c06d6028>] (driver_attach+0x24/0x28)
[    2.301899]  r7:00000000 r6:ee3efe00 r5:c1236500 r4:c123a900
[    2.307587] [<c06d6004>] (driver_attach) from [<c06d5aa0>] (bus_add_driver+0x1c4/0x208)
[    2.315628] [<c06d58dc>] (bus_add_driver) from [<c06d752c>] (driver_register+0x7c/0x110)
[    2.323752]  r7:c102bdf4 r6:ffffe000 r5:c1204c48 r4:c123a900
[    2.329437] [<c06d74b0>] (driver_register) from [<c06d8604>] (__platform_driver_register+0x48/0x50)
[    2.338520]  r5:c1204c48 r4:c1251c40
[    2.342121] [<c06d85bc>] (__platform_driver_register) from [<c102be10>] (omap2_mcspi_driver_init+0x1c/0x20)
[    2.351911] [<c102bdf4>] (omap2_mcspi_driver_init) from [<c02025b8>] (do_one_initcall+0x84/0x1b0)
[    2.360828] [<c0202534>] (do_one_initcall) from [<c1000fe8>] (kernel_init_freeable+0x1c4/0x258)
[    2.369565]  r8:c104a854 r7:c10004f0 r6:c1251c40 r5:c1251c40 r4:00000007
[    2.376302] [<c1000e24>] (kernel_init_freeable) from [<c0a0f648>] (kernel_init+0x10/0x11c)
[    2.384602]  r10:00000000 r9:00000000 r8:00000000 r7:00000000 r6:00000000 r5:c0a0f638
[    2.392465]  r4:00000000
[    2.395011] [<c0a0f638>] (kernel_init) from [<c02010d8>] (ret_from_fork+0x14/0x3c)
[    2.402613] Exception stack(0xee88ffb0 to 0xee88fff8)
[    2.407689] ffa0:                                     00000000 00000000 00000000 00000000
[    2.415904] ffc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
[    2.424115] ffe0: 00000000 00000000 00000000 00000000 00000013 00000000
[    2.430757]  r5:c0a0f638 r4:00000000
[    2.434418] ---[ end trace 227e7fc4bd3e8f57 ]---
[    2.440019] mdio_bus fixed-0: GPIO lookup for consumer reset
[    2.440026] mdio_bus fixed-0: using lookup tables for GPIO lookup
[    2.440034] mdio_bus fixed-0: No GPIO consumer reset found
[    2.440059] libphy: Fixed MDIO Bus: probed
[    2.448111] mdio_bus 48485000.mdio: GPIO lookup for consumer reset
[    2.448119] mdio_bus 48485000.mdio: using device tree for GPIO lookup
[    2.448139] of_get_named_gpiod_flags: can't parse 'reset-gpios' property of node '/ocp/ethernet@48484000/mdio@48485000[0]'
[    2.448153] of_get_named_gpiod_flags: can't parse 'reset-gpio' property of node '/ocp/ethernet@48484000/mdio@48485000[0]'
[    2.448162] mdio_bus 48485000.mdio: using lookup tables for GPIO lookup
[    2.448170] mdio_bus 48485000.mdio: No GPIO consumer reset found
[    2.501061] davinci_mdio 48485000.mdio: davinci mdio revision 1.6, bus freq 1000000
[    2.508755] libphy: 48485000.mdio: probed
[    2.515082] of_get_named_gpiod_flags: can't parse 'reset-gpios' property of node '/ocp/ethernet@48484000/mdio@48485000/ethernet-phy@1[0]'
[    2.517580] of_get_named_gpiod_flags: can't parse 'reset-gpios' property of node '/ocp/ethernet@48484000/mdio@48485000/ethernet-phy@2[0]'
[    2.517752] davinci_mdio 48485000.mdio: phy[1]: device 48485000.mdio:01, driver Micrel KSZ9031 Gigabit PHY
[    2.527497] davinci_mdio 48485000.mdio: phy[2]: device 48485000.mdio:02, driver Micrel KSZ9031 Gigabit PHY
[    2.537753] cpsw 48484000.ethernet: Detected MACID = a8:10:87:8b:2a:f6
[    2.544376] cpsw 48484000.ethernet: initialized cpsw ale version 1.4
[    2.550759] cpsw 48484000.ethernet: ALE Table size 1024
[    2.556088] cpsw 48484000.ethernet: cpts: overflow check period 500 (jiffies)
[    2.564118] cpsw 48484000.ethernet: cpsw: Detected MACID = a8:10:87:8b:2a:f7
[    2.572491] i2c /dev entries driver
[    2.577617] gpio-fan gpio_fan: GPIO lookup for consumer alarm
[    2.577624] gpio-fan gpio_fan: using device tree for GPIO lookup
[    2.577641] of_get_named_gpiod_flags: can't parse 'alarm-gpios' property of node '/gpio_fan[0]'
[    2.577655] of_get_named_gpiod_flags: can't parse 'alarm-gpio' property of node '/gpio_fan[0]'
[    2.577664] gpio-fan gpio_fan: using lookup tables for GPIO lookup
[    2.577671] gpio-fan gpio_fan: No GPIO consumer alarm found
[    2.577685] gpio-fan gpio_fan: GPIO lookup for consumer (null)
[    2.577691] gpio-fan gpio_fan: using device tree for GPIO lookup
[    2.577716] of_get_named_gpiod_flags: parsed 'gpios' property of node '/gpio_fan[0]' - status (0)
[    2.577754] gpio gpiochip6: Persistence not supported for GPIO 5
[    2.577759] no flags found for (null)
[    2.577937] gpio-fan gpio_fan: GPIO fan initialized
[    2.585366] device-mapper: ioctl: 4.39.0-ioctl (2018-04-03) initialised: dm-devel@redhat.com
[    2.594903] cpu cpu0: dev_pm_opp_set_regulators: no regulator (vdd) found: -19
[    2.602718] sdhci: Secure Digital Host Controller Interface driver
[    2.608924] sdhci: Copyright(c) Pierre Ossman
[    2.614506] sdhci-pltfm: SDHCI platform and OF driver helper
[    2.621207] sdhci-omap 4809c000.mmc: GPIO lookup for consumer cd
[    2.621215] sdhci-omap 4809c000.mmc: using device tree for GPIO lookup
[    2.621242] of_get_named_gpiod_flags: parsed 'cd-gpios' property of node '/ocp/mmc@4809c000[0]' - status (0)
[    2.621277] gpio gpiochip5: Persistence not supported for GPIO 27
[    2.621289] omap_gpio 4805d000.gpio: Could not set line 27 debounce to 200000 microseconds (-22)
[    2.630114] sdhci-omap 4809c000.mmc: Got CD GPIO
[    2.634785] sdhci-omap 4809c000.mmc: GPIO lookup for consumer wp
[    2.634791] sdhci-omap 4809c000.mmc: using device tree for GPIO lookup
[    2.634816] of_get_named_gpiod_flags: parsed 'wp-gpios' property of node '/ocp/mmc@4809c000[0]' - status (0)
[    2.634828] gpio gpiochip5: Persistence not supported for GPIO 28
[    2.634837] sdhci-omap 4809c000.mmc: Got WP GPIO
[    2.639626] sdhci-omap 4809c000.mmc: Linked as a consumer to regulator.6
[    2.646412] sdhci-omap 4809c000.mmc: 4809c000.mmc supply vqmmc not found, using dummy regulator
[    2.655230] sdhci-omap 4809c000.mmc: Linked as a consumer to regulator.0
[    2.662038] sdhci-omap 4809c000.mmc: Dropping the link to regulator.0
[    2.668613] sdhci-omap 4809c000.mmc: Dropping the link to regulator.6
[    2.675468] sdhci-omap 480b4000.mmc: GPIO lookup for consumer wp
[    2.675477] sdhci-omap 480b4000.mmc: using device tree for GPIO lookup
[    2.675493] of_get_named_gpiod_flags: can't parse 'wp-gpios' property of node '/ocp/mmc@480b4000[0]'
[    2.675507] of_get_named_gpiod_flags: can't parse 'wp-gpio' property of node '/ocp/mmc@480b4000[0]'
[    2.675515] sdhci-omap 480b4000.mmc: using lookup tables for GPIO lookup
[    2.675522] sdhci-omap 480b4000.mmc: No GPIO consumer wp found
[    2.675644] sdhci-omap 480b4000.mmc: failed to set system capabilities
[    2.682721] ti-iodelay 4844a000.padconf: Set reg 0x678 Delay(a: 406 g: 0), Elements(C=0 F=11)0x2900b
[    2.691925] ti-iodelay 4844a000.padconf: Set reg 0x680 Delay(a: 659 g: 0), Elements(C=1 F=4)0x29024
[    2.701081] ti-iodelay 4844a000.padconf: Set reg 0x684 Delay(a: 0 g: 0), Elements(C=0 F=0)0x29000
[    2.710000] ti-iodelay 4844a000.padconf: Set reg 0x688 Delay(a: 0 g: 0), Elements(C=0 F=0)0x29000
[    2.718931] ti-iodelay 4844a000.padconf: Set reg 0x68c Delay(a: 0 g: 0), Elements(C=0 F=0)0x29000
[    2.727864] ti-iodelay 4844a000.padconf: Set reg 0x690 Delay(a: 130 g: 0), Elements(C=0 F=3)0x29003
[    2.736970] ti-iodelay 4844a000.padconf: Set reg 0x694 Delay(a: 0 g: 0), Elements(C=0 F=0)0x29000
[    2.745899] ti-iodelay 4844a000.padconf: Set reg 0x698 Delay(a: 0 g: 0), Elements(C=0 F=0)0x29000
[    2.754829] ti-iodelay 4844a000.padconf: Set reg 0x69c Delay(a: 169 g: 0), Elements(C=0 F=4)0x29004
[    2.763940] ti-iodelay 4844a000.padconf: Set reg 0x6a0 Delay(a: 0 g: 0), Elements(C=0 F=0)0x29000
[    2.772871] ti-iodelay 4844a000.padconf: Set reg 0x6a4 Delay(a: 0 g: 0), Elements(C=0 F=0)0x29000
[    2.781799] ti-iodelay 4844a000.padconf: Set reg 0x6a8 Delay(a: 0 g: 0), Elements(C=0 F=0)0x29000
[    2.790717] ti-iodelay 4844a000.padconf: Set reg 0x6ac Delay(a: 0 g: 0), Elements(C=0 F=0)0x29000
[    2.799647] ti-iodelay 4844a000.padconf: Set reg 0x6b0 Delay(a: 0 g: 0), Elements(C=0 F=0)0x29000
[    2.808575] ti-iodelay 4844a000.padconf: Set reg 0x6b4 Delay(a: 457 g: 0), Elements(C=0 F=13)0x2900d
[    2.817770] ti-iodelay 4844a000.padconf: Set reg 0x6b8 Delay(a: 0 g: 0), Elements(C=0 F=0)0x29000
[    2.826700] ti-iodelay 4844a000.padconf: Set reg 0x6bc Delay(a: 0 g: 0), Elements(C=0 F=0)0x29000
[    2.835713] sdhci-omap 480ad000.mmc: GPIO lookup for consumer cd
[    2.835720] sdhci-omap 480ad000.mmc: using device tree for GPIO lookup
[    2.835737] of_get_named_gpiod_flags: can't parse 'cd-gpios' property of node '/ocp/mmc@480ad000[0]'
[    2.835751] of_get_named_gpiod_flags: can't parse 'cd-gpio' property of node '/ocp/mmc@480ad000[0]'
[    2.835759] sdhci-omap 480ad000.mmc: using lookup tables for GPIO lookup
[    2.835767] sdhci-omap 480ad000.mmc: No GPIO consumer cd found
[    2.835775] sdhci-omap 480ad000.mmc: GPIO lookup for consumer wp
[    2.835781] sdhci-omap 480ad000.mmc: using device tree for GPIO lookup
[    2.835795] of_get_named_gpiod_flags: can't parse 'wp-gpios' property of node '/ocp/mmc@480ad000[0]'
[    2.835808] of_get_named_gpiod_flags: can't parse 'wp-gpio' property of node '/ocp/mmc@480ad000[0]'
[    2.835816] sdhci-omap 480ad000.mmc: using lookup tables for GPIO lookup
[    2.835823] sdhci-omap 480ad000.mmc: No GPIO consumer wp found
[    2.835936] sdhci-omap 480ad000.mmc: 480ad000.mmc supply vqmmc not found, using dummy regulator
[    2.844743] sdhci-omap 480ad000.mmc: Linked as a consumer to regulator.0
[    2.851541] sdhci-omap 480ad000.mmc: Dropping the link to regulator.0
[    2.858562] of_get_named_gpiod_flags: parsed 'gpios' property of node '/leds/led@0[0]' - status (0)
[    2.858577] gpio gpiochip3: Persistence not supported for GPIO 9
[    2.858582] no flags found for gpios
[    2.858688] of_get_named_gpiod_flags: parsed 'gpios' property of node '/leds/led@1[0]' - status (0)
[    2.858701] gpio gpiochip3: Persistence not supported for GPIO 10
[    2.858706] no flags found for gpios
[    2.859217] ledtrig-cpu: registered to indicate activity on CPUs
[    2.870996] NET: Registered protocol family 10
[    2.876449] Segment Routing with IPv6
[    2.880193] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
[    2.886650] NET: Registered protocol family 17
[    2.891378] Key type dns_resolver registered
[    2.895789] Registering SWP/SWPB emulation handler
[    2.900603] omap_voltage_late_init: Voltage driver support not added
[    2.907007] Power Management for TI OMAP4+ devices.
[    2.912625] Loading compiled-in X.509 certificates
[    2.942526] dmm 4e000000.dmm: workaround for errata i878 in use
[    2.950165] dmm 4e000000.dmm: initialized all PAT entries
[    2.956220] of_get_named_gpiod_flags: parsed 'gpio' property of node '/fixedregulator-wlan[0]' - status (0)
[    2.956654] of_get_named_gpiod_flags: parsed 'gpio' property of node '/fixedregulator-bt[0]' - status (0)
[    2.957979] palmas 0-0058: Irq flag is 0x00000008
[    2.994297] palmas 0-0058: Muxing GPIO 2f, PWM 0, LED 0
[    3.001246] SMPS12: supplied by regulator-dummy
[    3.007610] SMPS3: supplied by vcc_3v3
[    3.013211] SMPS45: supplied by regulator-dummy
[    3.019718] SMPS6: supplied by vcc_3v3
[    3.023880] smps6: Bringing 1050000uV into 1030000-1030000uV
[    3.031543] SMPS7: supplied by regulator-dummy
[    3.037510] SMPS8: supplied by vcc_3v3
[    3.041486] random: fast init done
[    3.046096] SMPS9: supplied by regulator-dummy
[    3.051299] LDO1: supplied by vcc_5v0
[    3.056957] LDO2: supplied by vcc_5v0
[    3.062480] LDO3: supplied by vcc_3v3
[    3.067980] LDO4: supplied by vcc_3v3
[    3.073519] LDO5: supplied by regulator-dummy
[    3.078657] LDO6: supplied by regulator-dummy
[    3.083778] LDO7: supplied by regulator-dummy
[    3.088892] LDO8: supplied by regulator-dummy
[    3.095010] LDO9: supplied by vcc_3v3
[    3.100690] LDOLN: supplied by vcc_3v3
[    3.106295] LDOUSB: supplied by vcc_5v0
[    3.114592] at24 0-0050: GPIO lookup for consumer wp
[    3.114600] at24 0-0050: using device tree for GPIO lookup
[    3.114629] of_get_named_gpiod_flags: parsed 'wp-gpios' property of node '/ocp/i2c@48070000/eeprom@50[0]' - status (0)
[    3.114679] gpio gpiochip4: Persistence not supported for GPIO 13
[    3.114978] at24 0-0050: 4096 byte 24c32 EEPROM, writable, 32 bytes/write
[    3.123696] rtc-m41t80 0-0068: char device (253:0)
[    3.123711] rtc-m41t80 0-0068: registered as rtc0
[    3.128506] omap_i2c 48070000.i2c: bus 0 rev0.12 at 400 kHz
[    3.135118] omap_i2c 48060000.i2c: bus 2 rev0.12 at 400 kHz
[    3.141789] omap_i2c 4807a000.i2c: bus 3 rev0.12 at 400 kHz
[    3.147929] omapdss_dss 58000000.dss: Linked as a consumer to regulator.29
[    3.155036] DSS: OMAP DSS rev 6.1
[    3.160088] omapdss_hdmi5 58040000.encoder: Linked as a consumer to regulator.23
[    3.167620] omapdss_hdmi5 58040000.encoder: Dropping the link to regulator.23
[    3.175391] tpd12s015 encoder@0: GPIO lookup for consumer (null)
[    3.175398] tpd12s015 encoder@0: using device tree for GPIO lookup
[    3.175415] of_get_named_gpiod_flags: can't parse 'gpios' property of node '/encoder@0[0]'
[    3.175428] of_get_named_gpiod_flags: can't parse 'gpio' property of node '/encoder@0[0]'
[    3.175437] tpd12s015 encoder@0: using lookup tables for GPIO lookup
[    3.175445] tpd12s015 encoder@0: No GPIO consumer (null) found
[    3.175453] tpd12s015 encoder@0: GPIO lookup for consumer (null)
[    3.175459] tpd12s015 encoder@0: using device tree for GPIO lookup
[    3.175472] of_get_named_gpiod_flags: can't parse 'gpios' property of node '/encoder@0[1]'
[    3.175485] of_get_named_gpiod_flags: can't parse 'gpio' property of node '/encoder@0[1]'
[    3.175493] tpd12s015 encoder@0: using lookup tables for GPIO lookup
[    3.175501] tpd12s015 encoder@0: No GPIO consumer (null) found
[    3.175508] tpd12s015 encoder@0: GPIO lookup for consumer (null)
[    3.175514] tpd12s015 encoder@0: using device tree for GPIO lookup
[    3.175538] of_get_named_gpiod_flags: parsed 'gpios' property of node '/encoder@0[2]' - status (0)
[    3.175552] gpio gpiochip6: Persistence not supported for GPIO 12
[    3.176224] sdhci-omap 4809c000.mmc: GPIO lookup for consumer cd
[    3.176231] sdhci-omap 4809c000.mmc: using device tree for GPIO lookup
[    3.176256] of_get_named_gpiod_flags: parsed 'cd-gpios' property of node '/ocp/mmc@4809c000[0]' - status (0)
[    3.176301] gpio gpiochip5: Persistence not supported for GPIO 27
[    3.176313] omap_gpio 4805d000.gpio: Could not set line 27 debounce to 200000 microseconds (-22)
[    3.185169] sdhci-omap 4809c000.mmc: Got CD GPIO
[    3.189813] sdhci-omap 4809c000.mmc: GPIO lookup for consumer wp
[    3.189819] sdhci-omap 4809c000.mmc: using device tree for GPIO lookup
[    3.189843] of_get_named_gpiod_flags: parsed 'wp-gpios' property of node '/ocp/mmc@4809c000[0]' - status (0)
[    3.189856] gpio gpiochip5: Persistence not supported for GPIO 28
[    3.189864] sdhci-omap 4809c000.mmc: Got WP GPIO
[    3.194665] sdhci-omap 4809c000.mmc: Linked as a consumer to regulator.6
[    3.201487] sdhci-omap 4809c000.mmc: 4809c000.mmc supply vqmmc not found, using dummy regulator
[    3.210271] sdhci-omap 4809c000.mmc: Linked as a consumer to regulator.0
[    3.217077] sdhci-omap 4809c000.mmc: Dropping the link to regulator.0
[    3.223819] sdhci-omap 4809c000.mmc: Linked as a consumer to regulator.20
[    3.230742] sdhci-omap 4809c000.mmc: no pinctrl state for ddr_3_3v mode
[    3.264534] mmc0: SDHCI controller on 4809c000.mmc [4809c000.mmc] using ADMA
[    3.272169] sdhci-omap 480b4000.mmc: GPIO lookup for consumer wp
[    3.272176] sdhci-omap 480b4000.mmc: using device tree for GPIO lookup
[    3.272192] of_get_named_gpiod_flags: can't parse 'wp-gpios' property of node '/ocp/mmc@480b4000[0]'
[    3.272206] of_get_named_gpiod_flags: can't parse 'wp-gpio' property of node '/ocp/mmc@480b4000[0]'
[    3.272214] sdhci-omap 480b4000.mmc: using lookup tables for GPIO lookup
[    3.272222] sdhci-omap 480b4000.mmc: No GPIO consumer wp found
[    3.272388] vdd_3v3: supplied by regen1
[    3.276520] sdhci-omap 480b4000.mmc: Linked as a consumer to regulator.1
[    3.283350] sdhci-omap 480b4000.mmc: Dropping the link to regulator.1
[    3.289891] sdhci-omap 480b4000.mmc: Linked as a consumer to regulator.1
[    3.321055] mmc1: SDHCI controller on 480b4000.mmc [480b4000.mmc] using ADMA
[    3.328836] ti-iodelay 4844a000.padconf: Set reg 0x678 Delay(a: 406 g: 0), Elements(C=0 F=11)0x2900b
[    3.338044] ti-iodelay 4844a000.padconf: Set reg 0x680 Delay(a: 659 g: 0), Elements(C=1 F=4)0x29024
[    3.347156] ti-iodelay 4844a000.padconf: Set reg 0x684 Delay(a: 0 g: 0), Elements(C=0 F=0)0x29000
[    3.356089] ti-iodelay 4844a000.padconf: Set reg 0x688 Delay(a: 0 g: 0), Elements(C=0 F=0)0x29000
[    3.365021] ti-iodelay 4844a000.padconf: Set reg 0x68c Delay(a: 0 g: 0), Elements(C=0 F=0)0x29000
[    3.373953] ti-iodelay 4844a000.padconf: Set reg 0x690 Delay(a: 130 g: 0), Elements(C=0 F=3)0x29003
[    3.383059] ti-iodelay 4844a000.padconf: Set reg 0x694 Delay(a: 0 g: 0), Elements(C=0 F=0)0x29000
[    3.391991] ti-iodelay 4844a000.padconf: Set reg 0x698 Delay(a: 0 g: 0), Elements(C=0 F=0)0x29000
[    3.400906] ti-iodelay 4844a000.padconf: Set reg 0x69c Delay(a: 169 g: 0), Elements(C=0 F=4)0x29004
[    3.410009] ti-iodelay 4844a000.padconf: Set reg 0x6a0 Delay(a: 0 g: 0), Elements(C=0 F=0)0x29000
[    3.418940] ti-iodelay 4844a000.padconf: Set reg 0x6a4 Delay(a: 0 g: 0), Elements(C=0 F=0)0x29000
[    3.427872] ti-iodelay 4844a000.padconf: Set reg 0x6a8 Delay(a: 0 g: 0), Elements(C=0 F=0)0x29000
[    3.436801] ti-iodelay 4844a000.padconf: Set reg 0x6ac Delay(a: 0 g: 0), Elements(C=0 F=0)0x29000
[    3.445731] ti-iodelay 4844a000.padconf: Set reg 0x6b0 Delay(a: 0 g: 0), Elements(C=0 F=0)0x29000
[    3.454668] ti-iodelay 4844a000.padconf: Set reg 0x6b4 Delay(a: 457 g: 0), Elements(C=0 F=13)0x2900d
[    3.463858] ti-iodelay 4844a000.padconf: Set reg 0x6b8 Delay(a: 0 g: 0), Elements(C=0 F=0)0x29000
[    3.472787] ti-iodelay 4844a000.padconf: Set reg 0x6bc Delay(a: 0 g: 0), Elements(C=0 F=0)0x29000
[    3.481808] sdhci-omap 480ad000.mmc: GPIO lookup for consumer cd
[    3.481815] sdhci-omap 480ad000.mmc: using device tree for GPIO lookup
[    3.481831] [   33.761068] vtt_fixed: supplied by smps3
of_get_named_gpiod_flags: can't parse 'cd-gpios' proper[   33.768909] aic_dvdd_fixed: disabling
ty of node '/ocp/mmc@480ad000[0]'
[    3.481846] of_get_named_gpiod_flags: can't parse 'cd-gpio' property of node '/ocp/mmc@480ad000[0]'
[    3.481854] sdhci-omap 480ad000.mmc: using lookup tables for GPIO lookup
[    3.481862] sdhci-omap 480ad000.mmc: No GPIO consumer cd found
[    3.481871] sdhci-omap 480ad000.mmc: GPIO lookup for consumer wp
[    3.481877] sdhci-omap 480ad000.mmc: using device tree for GPIO lookup
[    3.481891] of_get_named_gpiod_flags: can't parse 'wp-gpios' property of node '/ocp/mmc@480ad000[0]'
[    3.481903] of_get_named_gpiod_flags: can't parse 'wp-gpio' property of node '/ocp/mmc@480ad000[0]'
[    3.481911] sdhci-omap 480ad000.mmc: using lookup tables for GPIO lookup
[    3.481918] sdhci-omap 480ad000.mmc: No GPIO consumer wp found
[    3.482079] sdhci-omap 480ad000.mmc: 480ad000.mmc supply vqmmc not found, using dummy regulator
[    3.490867] sdhci-omap 480ad000.mmc: Linked as a consumer to regulator.0
[    3.497667] sdhci-omap 480ad000.mmc: Dropping the link to regulator.0
[    3.504233] sdhci-omap 480ad000.mmc: Linked as a consumer to regulator.11
[    3.511114] sdhci-omap 480ad000.mmc: no pinctrl state for sdr104 mode
[    3.517586] sdhci-omap 480ad000.mmc: no pinctrl state for ddr50 mode
[    3.523995] sdhci-omap 480ad000.mmc: no pinctrl state for hs200_1_8v mode
[    3.554153] mmc2: SDHCI controller on 480ad000.mmc [480ad000.mmc] using PIO
[    3.562151] omapdss_hdmi5 58040000.encoder: Linked as a consumer to regulator.23
[    3.570139] omapdss_dss 58000000.dss: bound 58001000.dispc (ops dispc_component_ops)
[    3.578338] omapdss_dss 58000000.dss: bound 58040000.encoder (ops hdmi5_component_ops)
[    3.594362] mmc1: new DDR MMC card at address 0001
[    3.599882] mmcblk1: mmc1:0001 Q2J55L 7.09 GiB
[    3.605186] mmcblk1boot0: mmc1:0001 Q2J55L partition 1 16.0 MiB
[    3.611788] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
[    3.619059] mmcblk1boot1: mmc1:0001 Q2J55L partition 2 16.0 MiB
[    3.625170] [drm] No driver support for vblank timestamp query.
[    3.631295] mmcblk1rpmb: mmc1:0001 Q2J55L partition 3 4.00 MiB, chardev (244:0)
[    3.641462] [drm] Enabling DMM ywrap scrolling
[    3.650363]  mmcblk1: p1 p2
[    3.654106] Console: switching to colour frame buffer device 100x30
[    3.666014] omapdrm omapdrm.0: fb0: omapdrm frame buffer device
[    3.674061] [drm] Initialized omapdrm 1.0.0 20110917 for omapdrm.0 on minor 0
[    3.682454] rtc-m41t80 0-0068: setting system clock to 2023-10-07 15:07:47 UTC (1696691267)
[    3.691790] ALSA device list:
[    3.694775]   No soundcards found.
[    4.694355] EXT4-fs (mmcblk1p2): recovery complete
[    4.700384] EXT4-fs (mmcblk1p2): mounted filesystem with ordered data mode. Opts: (null)
[    4.708571] VFS: Mounted root (ext4 filesystem) on device 179:2.
[    4.717392] devtmpfs: mounted
[    4.721760] Freeing unused kernel memory: 2048K
[    4.726464] Run /sbin/init as init process
[    4.869021] systemd[1]: systemd 239 running in system mode. (+PAM -AUDIT -SELINUX +IMA -APPARMOR +SMACK +SYSVINIT +UTMP -LIBCRYPTSETUP -GCRYPT -GNUTLS +ACL +XZ -LZ4 -SECCOMP +BLKID -ELFUTILS +KMOD -IDN2 -IDN -PCRE2 default-hierarchy=hybrid)
[    4.890843] systemd[1]: Detected architecture arm.
[    4.931606] systemd[1]: Set hostname to <am57xx-phycore-kit>.
[    5.063221] systemd[1]: File /lib/systemd/system/systemd-journald.service:36 configures an IP firewall (IPAddressDeny=any), but the local system does not support BPF/cgroup based firewalling.
[    5.081047] systemd[1]: Proceeding WITHOUT firewalling in effect! (This warning is only shown for the first loaded unit using IP firewalling.)
[    5.272730] random: systemd: uninitialized urandom read (16 bytes read)
[    5.282634] systemd[1]: Created slice system-serial\x2dgetty.slice.
[    5.311220] random: systemd: uninitialized urandom read (16 bytes read)
[    5.318300] systemd[1]: Listening on Journal Socket (/dev/log).
[    5.351130] random: systemd: uninitialized urandom read (16 bytes read)
[    5.357984] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
[    5.401158] systemd[1]: Reached target Swap.
[    5.431333] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
[    5.838656] EXT4-fs (mmcblk1p2): re-mounted. Opts: (null)
[    6.442245] systemd-journald[94]: Received request to flush runtime journal from PID 1
[    7.070358] omap-rproc 58820000.ipu: ignoring dependency for device, assuming no driver
[    7.121335] omap-rproc 58820000.ipu: ignoring dependency for device, assuming no driver
[    7.129423] omap-rproc 58820000.ipu: assigned reserved memory node ipu1-memory@95800000
[    7.191529] remoteproc remoteproc0: 58820000.ipu is available
[    7.219901] remoteproc remoteproc0: Direct firmware load for dra7-ipu1-fw.xem4 failed with error -2
[    7.233915] omap-rproc 55020000.ipu: ignoring dependency for device, assuming no driver
[    7.270218] remoteproc remoteproc0: powering up 58820000.ipu
[    7.326552] omap-rproc 55020000.ipu: ignoring dependency for device, assuming no driver
[    7.330760] remoteproc remoteproc0: Direct firmware load for dra7-ipu1-fw.xem4 failed with error -2
[    7.375291] omap-rproc 55020000.ipu: assigned reserved memory node ipu2-memory@9b800000
[    7.446461] remoteproc remoteproc0: request_firmware failed: -2
[    7.448885] remoteproc remoteproc1: 55020000.ipu is available
[    7.537278] remoteproc remoteproc1: Direct firmware load for dra7-ipu2-fw.xem4 failed with error -2
[    7.549989] omap-rproc 40800000.dsp: ignoring dependency for device, assuming no driver
[    7.575038] remoteproc remoteproc1: powering up 55020000.ipu
[    7.631369] omap-rproc 40800000.dsp: ignoring dependency for device, assuming no driver
[    7.662661] remoteproc remoteproc1: Direct firmware load for dra7-ipu2-fw.xem4 failed with error -2
[    7.685929] omap-rproc 40800000.dsp: assigned reserved memory node dsp1-memory@97800000
[    7.724176] remoteproc remoteproc1: request_firmware failed: -2
[    7.730604] ti-iodelay 4844a000.padconf: Set reg 0xbf4 Delay(a: 1996 g: 632), Elements(C=4 F=10)0x2908a
[    7.747102] omap_rng 48090000.rng: Random Number Generator ver. 20
[    7.753523] random: crng init done
[    7.767381] random: 7 urandom warning(s) missed due to ratelimiting
[    7.771428] remoteproc remoteproc2: 40800000.dsp is available
[    7.786803] Driver for 1-wire Dallas network protocol.
[    7.809493] ti-iodelay 4844a000.padconf: Set reg 0xc00 Delay(a: 2190 g: 790), Elements(C=4 F=18)0x29092
[    7.810064] omap-des 480a5000.des: OMAP DES hw accel rev: 2.2
[    7.865266] palmas-usb 48070000.i2c:tps659038@58:tps659038_usb: GPIO lookup for consumer id
[    7.865277] palmas-usb 48070000.i2c:tps659038@58:tps659038_usb: using device tree for GPIO lookup
[    7.865298] of_get_named_gpiod_flags: can't parse 'id-gpios' property of node '/ocp/i2c@48070000/tps659038@58/tps659038_usb[0]'
[    7.865327] of_get_named_gpiod_flags: parsed 'id-gpio' property of node '/ocp/i2c@48070000/tps659038@58/tps659038_usb[0]' - status (0)
[    7.865343] gpio gpiochip7: Persistence not supported for GPIO 6
[    7.865355] palmas-usb 48070000.i2c:tps659038@58:tps659038_usb: GPIO lookup for consumer vbus
[    7.865362] palmas-usb 48070000.i2c:tps659038@58:tps659038_usb: using device tree for GPIO lookup
[    7.865379] of_get_named_gpiod_flags: can't parse 'vbus-gpios' property of node '/ocp/i2c@48070000/tps659038@58/tps659038_usb[0]'
[    7.865403] of_get_named_gpiod_flags: parsed 'vbus-gpio' property of node '/ocp/i2c@48070000/tps659038@58/tps659038_usb[0]' - status (0)
[    7.865416] gpio gpiochip3: Persistence not supported for GPIO 21
[    7.865429] omap_gpio 48053000.gpio: Could not set line 6 debounce to 20000 microseconds (-22)
[    7.871161] ti-iodelay 4844a000.padconf: Set reg 0xc0c Delay(a: 2100 g: 604), Elements(C=4 F=13)0x2908d
[    7.887248] rtc rtc2: 48070000.i2c:tps659038@58:tps659038_rtc: dev (253:2)
[    7.887259] palmas-rtc 48070000.i2c:tps659038@58:tps659038_rtc: rtc core: registered 48070000.i2c:tps659038@58:tps659038_rtc as rtc2
[    7.887361] remoteproc remoteproc2: Direct firmware load for dra7-dsp1-fw.xe66 failed with error -2
[    7.911331] omap-rproc 41000000.dsp: ignoring dependency for device, assuming no driver
[    7.924462] omap-des 480a5000.des: will run requests pump with realtime priority
[    7.950856] omap-rproc 41000000.dsp: ignoring dependency for device, assuming no driver
[    7.974775] of_get_named_gpiod_flags: can't parse 'reset-gpios' property of node '/ocp/i2c@4807a000/tlv320aic3007@18[0]'
[    7.974792] of_get_named_gpiod_flags: can't parse 'gpio-reset' property of node '/ocp/i2c@4807a000/tlv320aic3007@18[0]'
[    7.974871] tlv320aic3x-codec 3-0018: Linked as a consumer to regulator.1
[    7.981772] omap_hdq 480b2000.1w: OMAP HDQ Hardware Rev 0.:. Driver in Interrupt mode
[    7.991896] ti-iodelay 4844a000.padconf: Set reg 0xc18 Delay(a: 2108 g: 286), Elements(C=4 F=8)0x29088
[    8.024704] remoteproc remoteproc2: powering up 40800000.dsp
[    8.030822] aic_dvdd_fixed: supplied by vdd_3v3
[    8.030964] tlv320aic3x-codec 3-0018: Linked as a consumer to regulator.2
[    8.033297] edt_ft5x06 3-0038: GPIO lookup for consumer reset
[    8.033305] edt_ft5x06 3-0038: using device tree for GPIO lookup
[    8.033325] of_get_named_gpiod_flags: can't parse 'reset-gpios' property of node '/ocp/i2c@4807a000/ft5x06@38[0]'
[    8.033339] of_get_named_gpiod_flags: can't parse 'reset-gpio' property of node '/ocp/i2c@4807a000/ft5x06@38[0]'
[    8.033354] edt_ft5x06 3-0038: using lookup tables for GPIO lookup
[    8.033368] edt_ft5x06 3-0038: No GPIO consumer reset found
[    8.033384] edt_ft5x06 3-0038: GPIO lookup for consumer wake
[    8.033393] edt_ft5x06 3-0038: using device tree for GPIO lookup
[    8.033409] of_get_named_gpiod_flags: can't parse 'wake-gpios' property of node '/ocp/i2c@4807a000/ft5x06@38[0]'
[    8.033424] of_get_named_gpiod_flags: can't parse 'wake-gpio' property of node '/ocp/i2c@4807a000/ft5x06@38[0]'
[    8.033438] edt_ft5x06 3-0038: using lookup tables for GPIO lookup
[    8.033453] edt_ft5x06 3-0038: No GPIO consumer wake found
[    8.034978] CAN device driver interface
[    8.035197] omap-rproc 41000000.dsp: assigned reserved memory node dsp2-memory@95000000
[    8.035290] remoteproc remoteproc3: 41000000.dsp is available
[    8.042074] c_can_platform 4ae3c000.can: c_can_platform device registered (regs=94474f89, irq=102)
[    8.080075] edt_ft5x06 3-0038: touchscreen probe failed
[    8.093206] ti-iodelay 4844a000.padconf: Set reg 0x96c Delay(a: 1854 g: 1624), Elements(C=4 F=22)0x29096
[    8.105551] edt_ft5x06: probe of 3-0038 failed with error -121
[    8.111999] remoteproc remoteproc2: Direct firmware load for dra7-dsp1-fw.xe66 failed with error -2
[    8.151516] ti-iodelay 4844a000.padconf: Set reg 0x978 Delay(a: 1906 g: 1520), Elements(C=4 F=21)0x29095
[    8.173552] remoteproc remoteproc2: request_firmware failed: -2
[    8.205358] w1_master_driver w1_bus_master1: Attaching one wire slave 01.000000000000 crc 3d
[    8.223305] remoteproc remoteproc3: Direct firmware load for dra7-dsp2-fw.xe66 failed with error -2
[    8.264420] ti-iodelay 4844a000.padconf: Set reg 0x984 Delay(a: 1807 g: 1437), Elements(C=4 F=17)0x29091
[    8.317412] w1_master_driver w1_bus_master1: Family 1 for 01.000000000000.3d is not registered.
[    8.333628] remoteproc remoteproc3: powering up 41000000.dsp
[    8.345168] ti-iodelay 4844a000.padconf: Set reg 0x990 Delay(a: 1996 g: 997), Elements(C=5 F=1)0x290a1
[    8.370773] c_can_platform 48480000.can: c_can_platform device registered (regs=c1effe49, irq=103)
[    8.373283] remoteproc remoteproc3: Direct firmware load for dra7-dsp2-fw.xe66 failed with error -2
[    8.398949] omap_rtc 48838000.rtc: char device (253:1)
[    8.398962] omap_rtc 48838000.rtc: registered as rtc1
[    8.407119] ti-iodelay 4844a000.padconf: Set reg 0xa2c Delay(a: 0 g: 0), Elements(C=0 F=0)0x29000
[    8.407132] ti-iodelay 4844a000.padconf: Set reg 0x24c Delay(a: 2154 g: 978), Elements(C=5 F=5)0x290a5
[    8.407147] ti-iodelay 4844a000.padconf: Set reg 0x258 Delay(a: 2185 g: 1152), Elements(C=5 F=9)0x290a9
[    8.407158] ti-iodelay 4844a000.padconf: Set reg 0x120 Delay(a: 2108 g: 823), Elements(C=4 F=17)0x29091
[    8.407168] ti-iodelay 4844a000.padconf: Set reg 0x12c Delay(a: 2068 g: 977), Elements(C=5 F=3)0x290a3
[    8.407575] mt9m111 2-0048: GPIO lookup for consumer reset
[    8.407581] mt9m111 2-0048: using device tree for GPIO lookup
[    8.407619] of_get_named_gpiod_flags: parsed 'reset-gpios' property of node '/ocp/i2c@48060000/mt9m111@48[0]' - status (0)
[    8.407636] gpio gpiochip7: Persistence not supported for GPIO 2
[    8.441220] mt9m111 2-0048: Failed to resume the sensor: -121
[    8.441309] mt9m111 2-0048: No MT9M111/MT9M112/MT9M131 chip detected register read ffffff87
[    8.441317] ------------[ cut here ]------------
[    8.441348] WARNING: CPU: 0 PID: 142 at drivers/media/i2c/mt9m111.c:924 mt9m111_s_power+0x194/0x22c [mt9m111]
[    8.441353] Modules linked in: rtc_omap c_can_platform(+) c_can can_dev edt_ft5x06 snd_soc_tlv320aic3x extcon_palmas rtc_palmas omap_hdq omap_des wire des_generic crypto_engine omap_crypto mt9m111(+) omap_rng omap_remoteproc virtio_rpmsg_bus rpmsg_core remoteproc sch_fq_codel
[    8.441495] CPU: 0 PID: 142 Comm: systemd-udevd Tainted: G        W         4.19.79-g8177f87071 #1
[    8.441504] Hardware name: Generic DRA74X (Flattened Device Tree)
[    8.441511] Backtrace:
[    8.441536] [<c020ca34>] (dump_backtrace) from [<c020cd6c>] (show_stack+0x18/0x1c)
[    8.441546]  r7:bf04d494 r6:600a0113 r5:00000000 r4:c124e51c
[    8.441571] [<c020cd54>] (show_stack) from [<c09fb3a0>] (dump_stack+0x90/0xa4)
[    8.441593] [<c09fb310>] (dump_stack) from [<c022e098>] (__warn+0xdc/0xf8)
[    8.441602]  r7:bf04d494 r6:00000009 r5:00000000 r4:00000000
[    8.441613] [<c022dfbc>] (__warn) from [<c022e0fc>] (warn_slowpath_null+0x48/0x50)
[    8.441635]  r9:00000000 r8:ed77d504 r7:bf04d040 r6:bf04bd4c r5:0000039c r4:bf04d494
[    8.441660] [<c022e0b4>] (warn_slowpath_null) from [<bf04bd4c>] (mt9m111_s_power+0x194/0x22c [mt9m111])
[    8.441668]  r6:00000000 r5:ed77d56c r4:ed77d440
[    8.441695] [<bf04bbb8>] (mt9m111_s_power [mt9m111]) from [<bf04c2ac>] (mt9m111_probe+0x488/0x544 [mt9m111])
[    8.441716]  r8:ed77d504 r7:bf04d040 r6:ed77d440 r5:c1204c48 r4:ed77d440
[    8.441741] [<bf04be24>] (mt9m111_probe [mt9m111]) from [<c079bea8>] (i2c_device_probe+0x24c/0x26c)
[    8.441766]  r10:00000018 r9:bf04e044 r8:00000000 r7:edd68000 r6:bf04e044 r5:bf04be24
[    8.441775]  r4:edd68020
[    8.441787] [<c079bc5c>] (i2c_device_probe) from [<c06d66f0>] (really_probe+0x204/0x2c0)
[    8.441796]  r9:bf04e044 r8:00000000 r7:00000000 r6:c128b5b8 r5:edd68020 r4:c128b5b4
[    8.441811] [<c06d64ec>] (really_probe) from [<c06d6950>] (driver_probe_device+0x68/0x180)
[    8.441835]  r10:c1204c48 r9:ecc4fa80 r8:00000000 r7:c06d6a68 r6:edd68054 r5:bf04e044
[    8.441842]  r4:edd68020 r3:00000000
[    8.441854] [<c06d68e8>] (driver_probe_device) from [<c06d6b5c>] (__driver_attach+0xf4/0xf8)
[    8.441862]  r9:ecc4fa80 r8:00000000 r7:c06d6a68 r6:edd68054 r5:bf04e044 r4:edd68020
[    8.441873] [<c06d6a68>] (__driver_attach) from [<c06d47bc>] (bus_for_each_dev+0x7c/0xbc)
[    8.441881]  r7:c06d6a68 r6:bf04e044 r5:c1204c48 r4:edd3eb34
[    8.441904] [<c06d4740>] (bus_for_each_dev) from [<c06d6028>] (driver_attach+0x24/0x28)
[    8.441921]  r7:00000000 r6:ed797b80 r5:c123f6ac r4:bf04e044
[    8.441941] [<c06d6004>] (driver_attach) from [<c06d5aa0>] (bus_add_driver+0x1c4/0x208)
[    8.441962] [<c06d58dc>] (bus_add_driver) from [<c06d752c>] (driver_register+0x7c/0x110)
[    8.441973]  r7:bf051000 r6:ffffe000 r5:c1204c48 r4:bf04e044
[    8.441983] [<c06d74b0>] (driver_register) from [<c079b968>] (i2c_register_driver+0x44/0x88)
[    8.441996]  r5:c1204c48 r4:bf04e028
[    8.442022] [<c079b924>] (i2c_register_driver) from [<bf05101c>] (mt9m111_i2c_driver_init+0x1c/0x1000 [mt9m111])
[    8.442032]  r5:c1204c48 r4:c1251c40
[    8.442062] [<bf051000>] (mt9m111_i2c_driver_init [mt9m111]) from [<c02025b8>] (do_one_initcall+0x84/0x1b0)
[    8.442082] [<c0202534>] (do_one_initcall) from [<c02bd68c>] (do_init_module+0x68/0x218)
[    8.442103]  r8:ed751f38 r7:bf04e0c0 r6:ecc4f940 r5:00000002 r4:bf04e0c0
[    8.442117] [<c02bd624>] (do_init_module) from [<c02bfba0>] (load_module+0x22c0/0x24d4)
[    8.442134]  r7:bf04e0c0 r6:ecc4fa40 r5:00000002 r4:00000002
[    8.442154] [<c02bd8e0>] (load_module) from [<c02bfff8>] (sys_finit_module+0xcc/0xe4)
[    8.442168]  r10:0000017b r9:ed750000 r8:c0201204 r7:00000007 r6:b6efcd5c r5:00000000
[    8.442173]  r4:c1204c48
[    8.442193] [<c02bff2c>] (sys_finit_module) from [<c0201000>] (ret_fast_syscall+0x0/0x4c)
[    8.442203] Exception stack(0xed751fa8 to 0xed751ff0)
[    8.442220] 1fa0:                   00549ef8 00000000 00000007 b6efcd5c 00000000 00020000
[    8.442230] 1fc0: 00549ef8 00000000 00000000 0000017b 0050c178 00000000 00000000 00000000
[    8.442239] 1fe0: bea64ca0 bea64c90 b6ef742d b6d8b1b0
[    8.442253]  r7:0000017b r6:00000000 r5:00000000 r4:00549ef8
[    8.442262] ---[ end trace 227e7fc4bd3e8f59 ]---
[    8.443336] remoteproc remoteproc3: request_firmware failed: -2
[    8.505637] vip 48990000.vip: loading firmware vpdma-1b8.bin
[    8.541394] vip 48990000.vip: VPDMA firmware loaded
[    8.550405] vpe 489d0000.vpe: loading firmware vpdma-1b8.bin
[    8.552110] net eth1: initializing cpsw version 1.15 (0)
[    8.571849] vpe 489d0000.vpe: Device registered as /dev/video0
[    8.660922] SCSI subsystem initialized
[    8.723266] Micrel KSZ9031 Gigabit PHY 48485000.mdio:02: attached PHY driver [Micrel KSZ9031 Gigabit PHY] (mii_bus:phy_addr=48485000.mdio:02, irq=POLL)
[    8.963928] libata version 3.00 loaded.
[    8.995964] phy phy-4a084000.phy.4: Linked as a consumer to regulator.30
[    9.195612] phy phy-4a085000.phy.5: Linked as a consumer to regulator.30
[    9.199034] omap_wdt: OMAP Watchdog Timer Rev 0x01: initial timeout 60 sec
[    9.217736] omap-sham 4b101000.sham: hw accel on OMAP rev 4.3
[    9.223690] omap-aes 4b500000.aes: OMAP AES hw accel rev: 3.3
[    9.242867] omap-aes 4b500000.aes: will run requests pump with realtime priority
[    9.316231] omap-aes 4b700000.aes: OMAP AES hw accel rev: 3.3
[    9.327678] omap-aes 4b700000.aes: will run requests pump with realtime priority
[    9.370671] ahci 4a140000.sata: controller can't do 64bit DMA, forcing 32bit
[    9.449884] omap-hdmi-audio omap-hdmi-audio.0.auto: snd-soc-dummy-dai <-> 58040000.encoder mapping ok
[    9.461880] ahci 4a140000.sata: forcing port_map 0x0 -> 0x1
[    9.504243] ahci 4a140000.sata: AHCI 0001.0300 32 slots 1 ports 3 Gbps 0x1 impl platform mode
[    9.537866] omap-hdmi-audio omap-hdmi-audio.0.auto: ASoC: no DMI vendor name!
[    9.563996] ahci 4a140000.sata: flags: ncq sntf pm led clo only pmp pio slum part ccc apst
[    9.661691] scsi host0: ahci
[    9.665088] ata1: SATA max UDMA/133 mmio [mem 0x4a140000-0x4a1410ff] port 0x100 irq 93
[    9.726238] of_get_named_gpiod_flags: can't parse 'simple-audio-card,hp-det-gpio' property of node '/sound[0]'
[    9.726259] of_get_named_gpiod_flags: can't parse 'simple-audio-card,mic-det-gpio' property of node '/sound[0]'
[    9.743232] asoc-simple-card sound: tlv320aic3x-hifi <-> 48460000.mcasp mapping ok
[    9.769796] IPv6: ADDRCONF(NETDEV_UP): eth1: link is not ready
[    9.836875] asoc-simple-card sound: ASoC: no DMI vendor name!
[    9.867690] net eth0: initializing cpsw version 1.15 (0)
[   10.022511] Micrel KSZ9031 Gigabit PHY 48485000.mdio:01: attached PHY driver [Micrel KSZ9031 Gigabit PHY] (mii_bus:phy_addr=48485000.mdio:01, irq=POLL)
[   10.037503] ata1: SATA link down (SStatus 0 SControl 300)
[   10.124562] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
[   11.745661] dwc3 488d0000.usb: Failed to get clk 'ref': -2
[   11.795462] OF: graph: no port node found in /ocp/ocp2scp@4a080000/phy@4a085000
[   11.887031] usbcore: registered new interface driver usbfs
[   11.898746] usbcore: registered new interface driver hub
[   11.908252] usbcore: registered new device driver usb
[   11.924902] xhci-hcd xhci-hcd.1.auto: xHCI Host Controller
[   11.930655] xhci-hcd xhci-hcd.1.auto: new USB bus registered, assigned bus number 1
[   11.939017] xhci-hcd xhci-hcd.1.auto: hcc params 0x0220f04c hci version 0x100 quirks 0x0000000002010010
[   11.948771] xhci-hcd xhci-hcd.1.auto: irq 197, io mem 0x488d0000
[   11.955437] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002, bcdDevice= 4.19
[   11.963956] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[   11.971396] usb usb1: Product: xHCI Host Controller
[   11.976300] usb usb1: Manufacturer: Linux 4.19.79-g8177f87071 xhci-hcd
[   11.982891] usb usb1: SerialNumber: xhci-hcd.1.auto
[   11.988514] hub 1-0:1.0: USB hub found
[   11.992358] hub 1-0:1.0: 1 port detected
[   11.996734] xhci-hcd xhci-hcd.1.auto: xHCI Host Controller
[   12.002291] xhci-hcd xhci-hcd.1.auto: new USB bus registered, assigned bus number 2
[   12.010173] xhci-hcd xhci-hcd.1.auto: Host supports USB 3.0 SuperSpeed
[   12.016853] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
[   12.025308] usb usb2: New USB device found, idVendor=1d6b, idProduct=0003, bcdDevice= 4.19
[   12.033645] usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[   12.041084] usb usb2: Product: xHCI Host Controller
[   12.045987] usb usb2: Manufacturer: Linux 4.19.79-g8177f87071 xhci-hcd
[   12.052728] usb usb2: SerialNumber: xhci-hcd.1.auto
[   12.058180] hub 2-0:1.0: USB hub found
[   12.062017] hub 2-0:1.0: 1 port detected
[   33.761068] vtt_fixed: supplied by smps3
[   33.768909] aic_dvdd_fixed: disabling
root@am57xx-phycore-kit:~#

Thanks & regards,
Sujan

Hi Sujan,

It is a bit strange that USB hub is still initialized in the logs. It might be that these are being enabled in U-Boot. Could you try checking U-Boot device tree and see if USB can be disabled there, and also check if PCIe/serdes is being configured there as well?

It might be that some Linux device tree changes to PCIe/serdes are conflicting with changes in U-Boot device tree. 

Regards,

Takuma

Hi Takuma, 

Where is u-boot device tree located at, I only know of kernel source.

Thanks,

Sujan 

Hi Sujan,

If using the TI Linux SDK, then the u-boot source would be located under board-support. For example:

/PSDK_LINUX/ti-processor-sdk-linux-am57xx-evm-08_02_01_00/board-support$ ls
extra-drivers
linux-5.10.100+gitAUTOINC+7a7a3af903-g7a7a3af903
prebuilt-images
u-boot-2021.01+gitAUTOINC+44a87e3ab8-g44a87e3ab8 <- u-boot source code

I assume PHYTEC either reuses this, and/or hosts their u-boot source code somewhere else online.

Regards,

Takuma

diff --git a/drivers/pci/controller/dwc/pci-dra7xx.c b/drivers/pci/controller/dwc/pci-dra7xx.c
index 54f139b4d6ad..369397df3a99 100644
--- a/drivers/pci/controller/dwc/pci-dra7xx.c
+++ b/drivers/pci/controller/dwc/pci-dra7xx.c
@@ -622,6 +622,7 @@ static const struct of_device_id of_dra7xx_pcie_match[] = {
  *
  * To avoid this issue set PCIE_SS1_AXI2OCP_LEGACY_MODE_ENABLE to 1.
  */
+/*
 static int dra7xx_pcie_unaligned_memaccess(struct device *dev)
 {
        int ret;
@@ -651,8 +652,8 @@ static int dra7xx_pcie_unaligned_memaccess(struct device *dev)
        of_node_put(args.np);
 
        return ret;
-}
-
+}*/
+/*
 static int dra7xx_pcie_configure_two_lane(struct device *dev,
                                          u32 b1co_mode_sel_mask)
 {
@@ -679,8 +680,8 @@ static int dra7xx_pcie_configure_two_lane(struct device *dev,
        regmap_update_bits(pcie_syscon, pcie_reg, mask, val);
 
        return 0;
-}
-
+}*/
+/*
 static int __init dra7xx_pcie_probe(struct platform_device *pdev)
 {
        u32 reg;
@@ -768,7 +769,7 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev)
        if (phy_count == 2) {
                ret = dra7xx_pcie_configure_two_lane(dev, b1co_mode_sel_mask);
                if (ret < 0)
-                       dra7xx->phy_count = 1; /* Fallback to x1 lane mode */
+                       dra7xx->phy_count = 1;          //    Fallback to x1 lane mode 
        }
 
        ret = dra7xx_pcie_enable_phy(dra7xx);
@@ -867,6 +868,244 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev)
        pm_runtime_disable(dev);
        dra7xx_pcie_disable_phy(dra7xx);
 
+err_link:
+       while (--i >= 0)
+               device_link_del(link[i]);
+
+       return ret;
+}*/
+
+static int dra7xx_pcie_ep_legacy_mode(struct device *dev)
+{
+        int ret;
+        struct device_node *np = dev->of_node;
+        struct regmap *regmap;
+        unsigned int reg;
+        unsigned int field;
+
+        regmap = syscon_regmap_lookup_by_phandle(np, "syscon-legacy-mode");
+        if (IS_ERR(regmap)) {
+                dev_dbg(dev, "can't get syscon-legacy-mode\n");
+                return -EINVAL;
+        }
+
+        if (of_property_read_u32_index(np, "syscon-legacy-mode", 1, &reg)) {
+                dev_err(dev, "couldn't get legacy mode register offset\n");
+                return -EINVAL;
+        }
+
+        if (of_property_read_u32_index(np, "syscon-legacy-mode", 2, &field)) {
+                dev_err(dev, "can't get bit field for setting legacy mode\n");
+                return -EINVAL;
+        }
+
+        ret = regmap_update_bits(regmap, reg, field, field);
+        if (ret)
+                dev_err(dev, "failed to set legacy mode\n");
+
+        return ret;
+}
+
+
+static int __init dra7xx_pcie_probe(struct platform_device *pdev)
+{
+       u32 reg;
+       u32 field;
+       int ret;
+       int irq;
+       int i;
+       int phy_count;
+       struct phy **phy;
+       struct device_link **link;
+       void __iomem *base;
+       struct resource *res;
+       struct dw_pcie *pci;
+       struct dra7xx_pcie *dra7xx;
+       struct device *dev = &pdev->dev;
+       struct device_node *np = dev->of_node;
+       struct regmap *regmap;
+       char name[10];
+       struct gpio_desc *reset, *clk_oe;
+       const struct of_device_id *match;
+       const struct dra7xx_pcie_of_data *data;
+       enum dw_pcie_device_mode mode;
+
+       match = of_match_device(of_match_ptr(of_dra7xx_pcie_match), dev);
+       if (!match)
+               return -EINVAL;
+
+       data = (struct dra7xx_pcie_of_data *)match->data;
+       mode = (enum dw_pcie_device_mode)data->mode;
+
+       dra7xx = devm_kzalloc(dev, sizeof(*dra7xx), GFP_KERNEL);
+       if (!dra7xx)
+               return -ENOMEM;
+
+       pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
+       if (!pci)
+               return -ENOMEM;
+
+       pci->dev = dev;
+       pci->ops = &dw_pcie_ops;
+
+       irq = platform_get_irq(pdev, 0);
+       if (irq < 0) {
+               dev_err(dev, "missing IRQ resource\n");
+               return -EINVAL;
+       }
+
+       res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ti_conf");
+       base = devm_ioremap_nocache(dev, res->start, resource_size(res));
+       if (!base)
+               return -ENOMEM;
+
+       phy_count = of_property_count_strings(np, "phy-names");
+       if (phy_count < 0) {
+               dev_err(dev, "unable to find the strings\n");
+               return phy_count;
+       }
+
+       phy = devm_kzalloc(dev, sizeof(*phy) * phy_count, GFP_KERNEL);
+       if (!phy)
+               return -ENOMEM;
+
+       link = devm_kzalloc(dev, sizeof(*link) * phy_count, GFP_KERNEL);
+       if (!link)
+               return -ENOMEM;
+
+       if (phy_count > 1) {
+               regmap = syscon_regmap_lookup_by_phandle(np,
+                                                        "syscon-dual-lane");
+               if (IS_ERR(regmap)) {
+                       dev_dbg(dev, "can't get syscon-dual-lane\n");
+                       return -EINVAL;
+               }
+
+               if (of_property_read_u32_index(np, "syscon-dual-lane", 1,
+                                              &reg)) {
+                       dev_err(dev,
+                               "couldn't get x2 lane mode register offset\n");
+                       return -EINVAL;
+               }
+
+               if (of_property_read_u32_index(np, "syscon-dual-lane", 2,
+                                              &field)) {
+                       dev_err(dev,
+                               "can't get bit field for setting x2 lane mode\n");
+                       return -EINVAL;
+               }
+
+               ret = regmap_update_bits(regmap, reg, field, field);
+               if (ret) {
+                       dev_err(dev, "failed to set x2 lane mode\n");
+                       return ret;
+               }
+       }
+
+       for (i = 0; i < phy_count; i++) {
+               snprintf(name, sizeof(name), "pcie-phy%d", i);
+               phy[i] = devm_phy_get(dev, name);
+               if (IS_ERR(phy[i]))
+                       return PTR_ERR(phy[i]);
+
+               link[i] = device_link_add(dev, &phy[i]->dev, DL_FLAG_STATELESS);
+               if (!link[i]) {
+                       ret = -EINVAL;
+                       goto err_link;
+               }
+       }
+
+       dra7xx->base = base;
+       dra7xx->phy = phy;
+       dra7xx->pci = pci;
+       dra7xx->phy_count = phy_count;
+
+       ret = dra7xx_pcie_enable_phy(dra7xx);
+       if (ret) {
+               dev_err(dev, "failed to enable phy\n");
+               return ret;
+       }
+
+       pm_runtime_enable(dev);
+       ret = pm_runtime_get_sync(dev);
+       if (ret < 0) {
+               dev_err(dev, "pm_runtime_get_sync failed\n");
+               goto err_get_sync;
+       }
+
+       reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
+       reg &= ~LTSSM_EN;
+       dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
+
+       platform_set_drvdata(pdev, dra7xx);
+
+       clk_oe = devm_gpiod_get_optional(dev, "pcie-clk-oe", GPIOD_OUT_HIGH);
+       if (IS_ERR(clk_oe)) {
+               ret = PTR_ERR(clk_oe);
+               dev_err(&pdev->dev, "clk_oe gpio request failed, ret %d\n", ret);
+               goto err_gpio;
+       }
+
+       if (of_property_read_bool(np, "pcie-reset-active-low"))
+               reset = devm_gpiod_get_optional(dev, "pcie-reset", GPIOD_OUT_LOW);
+       else
+               reset = devm_gpiod_get_optional(dev, "pcie-reset", GPIOD_OUT_HIGH);
+       if (IS_ERR(reset)) {
+               ret = PTR_ERR(reset);
+               dev_err(&pdev->dev, "gpio request failed, ret %d\n", ret);
+               goto err_gpio;
+       }
+
+       reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
+       reg &= ~LTSSM_EN;
+       dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
+
+       dra7xx->link_gen = of_pci_get_max_link_speed(np);
+       if (dra7xx->link_gen < 0 || dra7xx->link_gen > 2)
+               dra7xx->link_gen = 2;
+
+       switch (mode) {
+       case DW_PCIE_RC_TYPE:
+               dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_DEVICE_TYPE,
+                                  DEVICE_TYPE_RC);
+
+               ret = dra7xx_add_pcie_port(dra7xx, pdev);
+               if (ret < 0)
+                       goto err_gpio;
+               break;
+       case DW_PCIE_EP_TYPE:
+               dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_DEVICE_TYPE,
+                                  DEVICE_TYPE_EP);
+
+               ret = dra7xx_pcie_ep_legacy_mode(dev);
+               if (ret)
+                       goto err_gpio;
+
+               ret = dra7xx_add_pcie_ep(dra7xx, pdev);
+               if (ret < 0)
+                       goto err_gpio;
+               break;
+       default:
+               dev_err(dev, "INVALID device type %d\n", mode);
+       }
+       dra7xx->mode = mode;
+
+       ret = devm_request_irq(dev, irq, dra7xx_pcie_irq_handler,
+                              IRQF_SHARED, "dra7xx-pcie-main", dra7xx);
+       if (ret) {
+               dev_err(dev, "failed to request irq\n");
+               goto err_gpio;
+       }
+
+       return 0;
+
+err_gpio:
+       pm_runtime_put(dev);
+
+err_get_sync:
+       pm_runtime_disable(dev);
+       dra7xx_pcie_disable_phy(dra7xx);
+
 err_link:
        while (--i >= 0)
                device_link_del(link[i]);
@@ -874,6 +1113,7 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev)
        return ret;
 }
 
+
 #ifdef CONFIG_PM_SLEEP
 static int dra7xx_pcie_suspend(struct device *dev)

check this change 

my output is 

PHYTEC: BSP-Yocto-TISDK-AM57xx-PD20.1.2
am57xx-phycore-kit login: root
root@am57xx-phycore-kit:~# dmesg |g[ 33.762435] vtt_fixed: supplied by smps3
[ 33.766706] aic_dvdd_fixed: disabling
[ 33.770394] wlan_fixed: disabling
grep pci
[ 0.572879] dra7-pcie 51800000.pcie_ep: Linked as a consumer to phy-4a095000.pciephy.2
[ 0.573121] dra7-pcie 51800000.pcie_ep: GPIO lookup for consumer pcie-clk-oe
[ 0.573128] dra7-pcie 51800000.pcie_ep: using device tree for GPIO lookup
[ 0.573148] of_get_named_gpiod_flags: can't parse 'pcie-clk-oe-gpios' property of node '/ocp/axi@1/pcie_ep@51800000[0]'
[ 0.573163] of_get_named_gpiod_flags: can't parse 'pcie-clk-oe-gpio' property of node '/ocp/axi@1/pcie_ep@51800000[0]'
[ 0.573172] dra7-pcie 51800000.pcie_ep: using lookup tables for GPIO lookup
[ 0.573181] dra7-pcie 51800000.pcie_ep: No GPIO consumer pcie-clk-oe found
[ 0.573190] dra7-pcie 51800000.pcie_ep: GPIO lookup for consumer pcie-reset
[ 0.573197] dra7-pcie 51800000.pcie_ep: using device tree for GPIO lookup
[ 0.573211] of_get_named_gpiod_flags: can't parse 'pcie-reset-gpios' property of node '/ocp/axi@1/pcie_ep@51800000[0]'
[ 0.573224] of_get_named_gpiod_flags: can't parse 'pcie-reset-gpio' property of node '/ocp/axi@1/pcie_ep@51800000[0]'
[ 0.573232] dra7-pcie 51800000.pcie_ep: using lookup tables for GPIO lookup
[ 0.573239] dra7-pcie 51800000.pcie_ep: No GPIO consumer pcie-reset found
root@am57xx-phycore-kit:~# ls /sys/class/pci_epc/
51800000.pcie_ep
root@am57xx-phycore-kit:~#

Hi Satyam,

Thank you for posting the patch!

Sujan, could you try out this patch and see if it works for you?

Regards,

Takuma

Hi Satyam Kumar,

Thanks for replying.
I applied the patch file and now i got this

root@am57xx-phycore-kit:~# dmesg | grep pci
[    0.562839] dra7-pcie 51800000.pcie: probe deferral not supported
[    0.562956] dra7-pcie 51800000.pcie_ep: probe deferral not supported

Here is my git diff 

diff --git a/arch/arm/boot/dts/am57xx-pcm-948-common.dtsi b/arch/arm/boot/dts/am57xx-pcm-948-common.dtsi
index abc788769d7f..7b420404de33 100644
--- a/arch/arm/boot/dts/am57xx-pcm-948-common.dtsi
+++ b/arch/arm/boot/dts/am57xx-pcm-948-common.dtsi
@@ -171,6 +171,24 @@
 		enable-active-high;
 		regulator-always-on;
 	};
+
+	user_io@0 {
+               compatible = "mydevice,generic-uio,ui_pdrv";
+               status = "okay";
+               interrupt-parent = <&gpio1>;
+               interrupts = <26 IRQ_TYPE_EDGE_RISING>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&gpio1B_pins>;
+       };
+
+       user_io@1 {
+               compatible = "mydevice,generic-uio,ui_pdrv";
+               status = "okay";
+               interrupt-parent = <&gpio1>;
+               interrupts = <28 IRQ_TYPE_EDGE_RISING>;
+               pinctrl-names = "default";
+                       pinctrl-0 = <&gpio1A_pins>;
+       };
 };
 
 &dra7_pmx_core {
@@ -243,6 +261,47 @@
 		>;
 	};
 
+//qnu
+
+       uart6_pins_default: uart6_pins_default {
+               pinctrl-single,pins = <
+//                     0x50 (PIN_INPUT_SLEW | MUX_MODE8) /* gpmc_a4.uart6_rxd */
+                       0x54 (PIN_INPUT | MUX_MODE14) /* gpmc_a5.uart6_txd */
+//                     0x58 (PIN_INPUT_SLEW | MUX_MODE8) /* gpmc_a6.uart6_ctsn */
+                       0x5c (PIN_INPUT | MUX_MODE14) /* gpmc_a7.uart6_rtsn */
+               >;
+       };
+
+       uart6_pins_sleep: uart6_pins_sleep{
+               pinctrl-single,pins = <
+//                     0x50 (PIN_INPUT | MUX_MODE15)
+                       0x54 (PIN_INPUT | MUX_MODE15)
+//                     0x58 (PIN_INPUT | MUX_MODE15)
+                       0x5c (PIN_INPUT | MUX_MODE15)
+               >;
+       };
+               
+       gpio1A_pins: pinmux_gpio1A_pins {
+               pinctrl-single,pins = <
+                         0x58 (PIN_INPUT_SLEW | MUX_MODE14) /* gpmc_a6.gpio1_28 */
+               >;
+       };
+
+       gpio1B_pins: pinmux_gpio1B_pins {
+                pinctrl-single,pins = <
+                         0x50 (PIN_INPUT_SLEW | MUX_MODE14) /* gpmc_a4.gpio1_26 */
+                >;
+        };
+
+
+       gpio1C_pins: pinmux_gpio1C_pins {
+                pinctrl-single,pins = <
+                         0x170 (PIN_INPUT_SLEW | MUX_MODE14) /* gpmc_a4.gpio4_3 */
+                >;
+        };
+
+//qnu end
+
 	uart10_pins_default: uart10_pins_default {
 		pinctrl-single,pins = <
 			DRA7XX_CORE_IOPAD(0x3570, PIN_INPUT_SLEW | MUX_MODE8)	/* (D1) vin2a_d2.uart10_rxd */
@@ -569,6 +628,7 @@
 	};
 };
 
+/*
 &phytec_leds {
 	pinctrl-0 = <&leds_som_pins_default &leds_cb_pins_default>;
 
@@ -586,6 +646,7 @@
 		default-state = "off";
 	};
 };
+*/
 
 &tps659038 {
 	tps659038_usb: tps659038_usb {
@@ -694,6 +755,17 @@
         pinctrl-1 = <&uart10_pins_sleep>;
 };
 
+&uart6 {
+       status = "okay";
+       pinctrl-names = "default", "sleep";
+       pinctrl-0 = <&uart6_pins_default>;
+//     pinctrl-1 = <&uart6_pins_sleep>;
+
+//     interrupts-extended = <&crossbar_mpu GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH
+//                            &dra7_pmx_core 0x50>;
+};
+
+
 &mac {
 	slaves = <2>;
 	pinctrl-names = "default", "sleep";
@@ -788,7 +860,7 @@
 };
 
 &pcie1_rc {
-	status = "okay";
+	status = "disabled";
 	pinctrl-names = "default";
 	pinctrl-0 = <&pcie1_pins>;
 
diff --git a/arch/arm/boot/dts/am57xx-phycore-common.dtsi b/arch/arm/boot/dts/am57xx-phycore-common.dtsi
index 42d86989c56d..d21c07d3ba11 100644
--- a/arch/arm/boot/dts/am57xx-phycore-common.dtsi
+++ b/arch/arm/boot/dts/am57xx-phycore-common.dtsi
@@ -570,6 +570,7 @@
  *       pcie2_rc/ep are incompatible with PCM-948
  */
 &axi1 {
+	status = "okay";
 	pcie2_ep: pcie_ep@51800000 {
 		compatible = "ti,dra7-pcie-ep";
 		reg = <0x51800000 0x28>, <0x51802000 0x14c>,
@@ -581,7 +582,7 @@
 		num-ob-windows = <16>;
 		ti,hwmods = "pcie2";
 		phys = <&pcie2_phy>;
-		phy-names = "pcie-phy1";
+		phy-names = "pcie-phy0";
 		syscon-legacy-mode = <&scm_conf1 0x14 1>;
 		status = "okay";
 	};
diff --git a/drivers/pci/controller/dwc/pci-dra7xx.c b/drivers/pci/controller/dwc/pci-dra7xx.c
index 54f139b4d6ad..a56542d3c313 100644
--- a/drivers/pci/controller/dwc/pci-dra7xx.c
+++ b/drivers/pci/controller/dwc/pci-dra7xx.c
@@ -622,6 +622,8 @@ static const struct of_device_id of_dra7xx_pcie_match[] = {
  *
  * To avoid this issue set PCIE_SS1_AXI2OCP_LEGACY_MODE_ENABLE to 1.
  */
+ 
+ /*
 static int dra7xx_pcie_unaligned_memaccess(struct device *dev)
 {
 	int ret;
@@ -651,8 +653,8 @@ static int dra7xx_pcie_unaligned_memaccess(struct device *dev)
 	of_node_put(args.np);
 
 	return ret;
-}
-
+}*/
+/*
 static int dra7xx_pcie_configure_two_lane(struct device *dev,
 					  u32 b1co_mode_sel_mask)
 {
@@ -680,7 +682,8 @@ static int dra7xx_pcie_configure_two_lane(struct device *dev,
 
 	return 0;
 }
-
+*/
+/*
 static int __init dra7xx_pcie_probe(struct platform_device *pdev)
 {
 	u32 reg;
@@ -768,7 +771,7 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev)
 	if (phy_count == 2) {
 		ret = dra7xx_pcie_configure_two_lane(dev, b1co_mode_sel_mask);
 		if (ret < 0)
-			dra7xx->phy_count = 1; /* Fallback to x1 lane mode */
+			dra7xx->phy_count = 1; 
 	}
 
 	ret = dra7xx_pcie_enable_phy(dra7xx);
@@ -873,6 +876,245 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev)
 
 	return ret;
 }
+*/
+
+static int dra7xx_pcie_ep_legacy_mode(struct device *dev)
+{
+        int ret;
+        struct device_node *np = dev->of_node;
+        struct regmap *regmap;
+        unsigned int reg;
+        unsigned int field;
+
+        regmap = syscon_regmap_lookup_by_phandle(np, "syscon-legacy-mode");
+        if (IS_ERR(regmap)) {
+                dev_dbg(dev, "can't get syscon-legacy-mode\n");
+                return -EINVAL;
+        }
+
+        if (of_property_read_u32_index(np, "syscon-legacy-mode", 1, &reg)) {
+                dev_err(dev, "couldn't get legacy mode register offset\n");
+                return -EINVAL;
+        }
+
+        if (of_property_read_u32_index(np, "syscon-legacy-mode", 2, &field)) {
+                dev_err(dev, "can't get bit field for setting legacy mode\n");
+                return -EINVAL;
+        }
+
+        ret = regmap_update_bits(regmap, reg, field, field);
+        if (ret)
+                dev_err(dev, "failed to set legacy mode\n");
+
+        return ret;
+}
+
+
+static int __init dra7xx_pcie_probe(struct platform_device *pdev)
+{
+       u32 reg;
+       u32 field;
+       int ret;
+       int irq;
+       int i;
+       int phy_count;
+       struct phy **phy;
+       struct device_link **link;
+       void __iomem *base;
+       struct resource *res;
+       struct dw_pcie *pci;
+       struct dra7xx_pcie *dra7xx;
+       struct device *dev = &pdev->dev;
+       struct device_node *np = dev->of_node;
+       struct regmap *regmap;
+       char name[10];
+       struct gpio_desc *reset, *clk_oe;
+       const struct of_device_id *match;
+       const struct dra7xx_pcie_of_data *data;
+       enum dw_pcie_device_mode mode;
+
+       match = of_match_device(of_match_ptr(of_dra7xx_pcie_match), dev);
+       if (!match)
+               return -EINVAL;
+
+       data = (struct dra7xx_pcie_of_data *)match->data;
+       mode = (enum dw_pcie_device_mode)data->mode;
+
+       dra7xx = devm_kzalloc(dev, sizeof(*dra7xx), GFP_KERNEL);
+       if (!dra7xx)
+               return -ENOMEM;
+
+       pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
+       if (!pci)
+               return -ENOMEM;
+
+       pci->dev = dev;
+       pci->ops = &dw_pcie_ops;
+
+       irq = platform_get_irq(pdev, 0);
+       if (irq < 0) {
+               dev_err(dev, "missing IRQ resource\n");
+               return -EINVAL;
+       }
+
+       res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ti_conf");
+       base = devm_ioremap_nocache(dev, res->start, resource_size(res));
+       if (!base)
+               return -ENOMEM;
+
+       phy_count = of_property_count_strings(np, "phy-names");
+       if (phy_count < 0) {
+               dev_err(dev, "unable to find the strings\n");
+               return phy_count;
+       }
+
+       phy = devm_kzalloc(dev, sizeof(*phy) * phy_count, GFP_KERNEL);
+       if (!phy)
+               return -ENOMEM;
+
+       link = devm_kzalloc(dev, sizeof(*link) * phy_count, GFP_KERNEL);
+       if (!link)
+               return -ENOMEM;
+
+       if (phy_count > 1) {
+               regmap = syscon_regmap_lookup_by_phandle(np,
+                                                        "syscon-dual-lane");
+               if (IS_ERR(regmap)) {
+                       dev_dbg(dev, "can't get syscon-dual-lane\n");
+                       return -EINVAL;
+               }
+
+               if (of_property_read_u32_index(np, "syscon-dual-lane", 1,
+                                              &reg)) {
+                       dev_err(dev,
+                               "couldn't get x2 lane mode register offset\n");
+                       return -EINVAL;
+               }
+
+               if (of_property_read_u32_index(np, "syscon-dual-lane", 2,
+                                              &field)) {
+                       dev_err(dev,
+                               "can't get bit field for setting x2 lane mode\n");
+                       return -EINVAL;
+               }
+
+               ret = regmap_update_bits(regmap, reg, field, field);
+               if (ret) {
+                       dev_err(dev, "failed to set x2 lane mode\n");
+                       return ret;
+               }
+       }
+
+       for (i = 0; i < phy_count; i++) {
+               snprintf(name, sizeof(name), "pcie-phy%d", i);
+               phy[i] = devm_phy_get(dev, name);
+               if (IS_ERR(phy[i]))
+                       return PTR_ERR(phy[i]);
+
+               link[i] = device_link_add(dev, &phy[i]->dev, DL_FLAG_STATELESS);
+               if (!link[i]) {
+                       ret = -EINVAL;
+                       goto err_link;
+               }
+       }
+
+       dra7xx->base = base;
+       dra7xx->phy = phy;
+       dra7xx->pci = pci;
+       dra7xx->phy_count = phy_count;
+
+       ret = dra7xx_pcie_enable_phy(dra7xx);
+       if (ret) {
+               dev_err(dev, "failed to enable phy\n");
+               return ret;
+       }
+
+       pm_runtime_enable(dev);
+       ret = pm_runtime_get_sync(dev);
+       if (ret < 0) {
+               dev_err(dev, "pm_runtime_get_sync failed\n");
+               goto err_get_sync;
+       }
+
+       reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
+       reg &= ~LTSSM_EN;
+       dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
+
+       platform_set_drvdata(pdev, dra7xx);
+
+       clk_oe = devm_gpiod_get_optional(dev, "pcie-clk-oe", GPIOD_OUT_HIGH);
+       if (IS_ERR(clk_oe)) {
+               ret = PTR_ERR(clk_oe);
+               dev_err(&pdev->dev, "clk_oe gpio request failed, ret %d\n", ret);
+               goto err_gpio;
+       }
+
+       if (of_property_read_bool(np, "pcie-reset-active-low"))
+               reset = devm_gpiod_get_optional(dev, "pcie-reset", GPIOD_OUT_LOW);
+       else
+               reset = devm_gpiod_get_optional(dev, "pcie-reset", GPIOD_OUT_HIGH);
+       if (IS_ERR(reset)) {
+               ret = PTR_ERR(reset);
+               dev_err(&pdev->dev, "gpio request failed, ret %d\n", ret);
+               goto err_gpio;
+       }
+
+       reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
+       reg &= ~LTSSM_EN;
+       dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
+
+       dra7xx->link_gen = of_pci_get_max_link_speed(np);
+       if (dra7xx->link_gen < 0 || dra7xx->link_gen > 2)
+               dra7xx->link_gen = 2;
+
+       switch (mode) {
+       case DW_PCIE_RC_TYPE:
+               dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_DEVICE_TYPE,
+                                  DEVICE_TYPE_RC);
+
+               ret = dra7xx_add_pcie_port(dra7xx, pdev);
+               if (ret < 0)
+                       goto err_gpio;
+               break;
+       case DW_PCIE_EP_TYPE:
+               dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_DEVICE_TYPE,
+                                  DEVICE_TYPE_EP);
+
+               ret = dra7xx_pcie_ep_legacy_mode(dev);
+               if (ret)
+                       goto err_gpio;
+
+               ret = dra7xx_add_pcie_ep(dra7xx, pdev);
+               if (ret < 0)
+                       goto err_gpio;
+               break;
+       default:
+               dev_err(dev, "INVALID device type %d\n", mode);
+       }
+       dra7xx->mode = mode;
+
+       ret = devm_request_irq(dev, irq, dra7xx_pcie_irq_handler,
+                              IRQF_SHARED, "dra7xx-pcie-main", dra7xx);
+       if (ret) {
+               dev_err(dev, "failed to request irq\n");
+               goto err_gpio;
+       }
+
+       return 0;
+
+err_gpio:
+       pm_runtime_put(dev);
+
+err_get_sync:
+       pm_runtime_disable(dev);
+       dra7xx_pcie_disable_phy(dra7xx);
+
+err_link:
+        while (--i >= 0)
+                device_link_del(link[i]);
+                
+        return ret;
+}
 
 #ifdef CONFIG_PM_SLEEP
 static int dra7xx_pcie_suspend(struct device *dev)

Also here is the complete dmesg log : 

dmesg_after_patch.txt

Can you please share the device tree changes too ?

Thanks & Regards,
Sujan

Hi Sujan,

Can you confirm pcie2_phy is enabled, similar to this thread: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/595948/linux-am5728-how-to-configure-am5728-as-two-pcie-rc-single-lane-rcs. I did not see pcie2_phy enabled in the git diff.

Regards,

Takuma

Hi Takuma san,

I removed all our additional custom configurations & only enabled pcie2_ep with pcie2_phy node as u suggested along with driver changes by Satyam.

Now one of the probe deferral is gone but other one still persists. 

root@am57xx-phycore-kit:~# dmesg | grep pci
[    0.562373] dra7-pcie 51800000.pcie_ep: probe deferral not supported
root@am57xx-phycore-kit:~# 

PFA, my current diff & dmesg 

diff --git a/arch/arm/boot/dts/am57xx-pcm-948-common.dtsi b/arch/arm/boot/dts/am57xx-pcm-948-common.dtsi
index abc788769d7f..e3431293034a 100644
--- a/arch/arm/boot/dts/am57xx-pcm-948-common.dtsi
+++ b/arch/arm/boot/dts/am57xx-pcm-948-common.dtsi
@@ -788,7 +788,8 @@
 };
 
 &pcie1_rc {
-	status = "okay";
+	//status = "okay";
+	status = "disabled";
 	pinctrl-names = "default";
 	pinctrl-0 = <&pcie1_pins>;
 
diff --git a/arch/arm/boot/dts/am57xx-phycore-common.dtsi b/arch/arm/boot/dts/am57xx-phycore-common.dtsi
index 42d86989c56d..456d9ec6224a 100644
--- a/arch/arm/boot/dts/am57xx-phycore-common.dtsi
+++ b/arch/arm/boot/dts/am57xx-phycore-common.dtsi
@@ -569,7 +569,13 @@
  *
  *       pcie2_rc/ep are incompatible with PCM-948
  */
+
+&pcie2_phy{
+	status = "okay";
+};
+
 &axi1 {
+	status = "okay";
 	pcie2_ep: pcie_ep@51800000 {
 		compatible = "ti,dra7-pcie-ep";
 		reg = <0x51800000 0x28>, <0x51802000 0x14c>,
@@ -581,7 +587,7 @@
 		num-ob-windows = <16>;
 		ti,hwmods = "pcie2";
 		phys = <&pcie2_phy>;
-		phy-names = "pcie-phy1";
+		phy-names = "pcie-phy0";
 		syscon-legacy-mode = <&scm_conf1 0x14 1>;
 		status = "okay";
 	};
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 549319d419b2..b548dbbd443d 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -367,7 +367,7 @@
 			#address-cells = <1>;
 			ranges = <0x51800000 0x51800000 0x3000
 				  0x0	     0x30000000 0x10000000>;
-			status = "disabled";
+			//status = "disabled";
 			pcie2_rc: pcie@51800000 {
 				reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>;
 				reg-names = "rc_dbics", "ti_conf", "config";
@@ -389,6 +389,7 @@
 						<0 0 0 2 &pcie2_intc 2>,
 						<0 0 0 3 &pcie2_intc 3>,
 						<0 0 0 4 &pcie2_intc 4>;
+				status = "disabled";
 				pcie2_intc: interrupt-controller {
 					interrupt-controller;
 					#address-cells = <0>;
diff --git a/drivers/pci/controller/dwc/pci-dra7xx.c b/drivers/pci/controller/dwc/pci-dra7xx.c
index 54f139b4d6ad..a56542d3c313 100644
--- a/drivers/pci/controller/dwc/pci-dra7xx.c
+++ b/drivers/pci/controller/dwc/pci-dra7xx.c
@@ -622,6 +622,8 @@ static const struct of_device_id of_dra7xx_pcie_match[] = {
  *
  * To avoid this issue set PCIE_SS1_AXI2OCP_LEGACY_MODE_ENABLE to 1.
  */
+ 
+ /*
 static int dra7xx_pcie_unaligned_memaccess(struct device *dev)
 {
 	int ret;
@@ -651,8 +653,8 @@ static int dra7xx_pcie_unaligned_memaccess(struct device *dev)
 	of_node_put(args.np);
 
 	return ret;
-}
-
+}*/
+/*
 static int dra7xx_pcie_configure_two_lane(struct device *dev,
 					  u32 b1co_mode_sel_mask)
 {
@@ -680,7 +682,8 @@ static int dra7xx_pcie_configure_two_lane(struct device *dev,
 
 	return 0;
 }
-
+*/
+/*
 static int __init dra7xx_pcie_probe(struct platform_device *pdev)
 {
 	u32 reg;
@@ -768,7 +771,7 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev)
 	if (phy_count == 2) {
 		ret = dra7xx_pcie_configure_two_lane(dev, b1co_mode_sel_mask);
 		if (ret < 0)
-			dra7xx->phy_count = 1; /* Fallback to x1 lane mode */
+			dra7xx->phy_count = 1; 
 	}
 
 	ret = dra7xx_pcie_enable_phy(dra7xx);
@@ -873,6 +876,245 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev)
 
 	return ret;
 }
+*/
+
+static int dra7xx_pcie_ep_legacy_mode(struct device *dev)
+{
+        int ret;
+        struct device_node *np = dev->of_node;
+        struct regmap *regmap;
+        unsigned int reg;
+        unsigned int field;
+
+        regmap = syscon_regmap_lookup_by_phandle(np, "syscon-legacy-mode");
+        if (IS_ERR(regmap)) {
+                dev_dbg(dev, "can't get syscon-legacy-mode\n");
+                return -EINVAL;
+        }
+
+        if (of_property_read_u32_index(np, "syscon-legacy-mode", 1, &reg)) {
+                dev_err(dev, "couldn't get legacy mode register offset\n");
+                return -EINVAL;
+        }
+
+        if (of_property_read_u32_index(np, "syscon-legacy-mode", 2, &field)) {
+                dev_err(dev, "can't get bit field for setting legacy mode\n");
+                return -EINVAL;
+        }
+
+        ret = regmap_update_bits(regmap, reg, field, field);
+        if (ret)
+                dev_err(dev, "failed to set legacy mode\n");
+
+        return ret;
+}
+
+
+static int __init dra7xx_pcie_probe(struct platform_device *pdev)
+{
+       u32 reg;
+       u32 field;
+       int ret;
+       int irq;
+       int i;
+       int phy_count;
+       struct phy **phy;
+       struct device_link **link;
+       void __iomem *base;
+       struct resource *res;
+       struct dw_pcie *pci;
+       struct dra7xx_pcie *dra7xx;
+       struct device *dev = &pdev->dev;
+       struct device_node *np = dev->of_node;
+       struct regmap *regmap;
+       char name[10];
+       struct gpio_desc *reset, *clk_oe;
+       const struct of_device_id *match;
+       const struct dra7xx_pcie_of_data *data;
+       enum dw_pcie_device_mode mode;
+
+       match = of_match_device(of_match_ptr(of_dra7xx_pcie_match), dev);
+       if (!match)
+               return -EINVAL;
+
+       data = (struct dra7xx_pcie_of_data *)match->data;
+       mode = (enum dw_pcie_device_mode)data->mode;
+
+       dra7xx = devm_kzalloc(dev, sizeof(*dra7xx), GFP_KERNEL);
+       if (!dra7xx)
+               return -ENOMEM;
+
+       pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
+       if (!pci)
+               return -ENOMEM;
+
+       pci->dev = dev;
+       pci->ops = &dw_pcie_ops;
+
+       irq = platform_get_irq(pdev, 0);
+       if (irq < 0) {
+               dev_err(dev, "missing IRQ resource\n");
+               return -EINVAL;
+       }
+
+       res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ti_conf");
+       base = devm_ioremap_nocache(dev, res->start, resource_size(res));
+       if (!base)
+               return -ENOMEM;
+
+       phy_count = of_property_count_strings(np, "phy-names");
+       if (phy_count < 0) {
+               dev_err(dev, "unable to find the strings\n");
+               return phy_count;
+       }
+
+       phy = devm_kzalloc(dev, sizeof(*phy) * phy_count, GFP_KERNEL);
+       if (!phy)
+               return -ENOMEM;
+
+       link = devm_kzalloc(dev, sizeof(*link) * phy_count, GFP_KERNEL);
+       if (!link)
+               return -ENOMEM;
+
+       if (phy_count > 1) {
+               regmap = syscon_regmap_lookup_by_phandle(np,
+                                                        "syscon-dual-lane");
+               if (IS_ERR(regmap)) {
+                       dev_dbg(dev, "can't get syscon-dual-lane\n");
+                       return -EINVAL;
+               }
+
+               if (of_property_read_u32_index(np, "syscon-dual-lane", 1,
+                                              &reg)) {
+                       dev_err(dev,
+                               "couldn't get x2 lane mode register offset\n");
+                       return -EINVAL;
+               }
+
+               if (of_property_read_u32_index(np, "syscon-dual-lane", 2,
+                                              &field)) {
+                       dev_err(dev,
+                               "can't get bit field for setting x2 lane mode\n");
+                       return -EINVAL;
+               }
+
+               ret = regmap_update_bits(regmap, reg, field, field);
+               if (ret) {
+                       dev_err(dev, "failed to set x2 lane mode\n");
+                       return ret;
+               }
+       }
+
+       for (i = 0; i < phy_count; i++) {
+               snprintf(name, sizeof(name), "pcie-phy%d", i);
+               phy[i] = devm_phy_get(dev, name);
+               if (IS_ERR(phy[i]))
+                       return PTR_ERR(phy[i]);
+
+               link[i] = device_link_add(dev, &phy[i]->dev, DL_FLAG_STATELESS);
+               if (!link[i]) {
+                       ret = -EINVAL;
+                       goto err_link;
+               }
+       }
+
+       dra7xx->base = base;
+       dra7xx->phy = phy;
+       dra7xx->pci = pci;
+       dra7xx->phy_count = phy_count;
+
+       ret = dra7xx_pcie_enable_phy(dra7xx);
+       if (ret) {
+               dev_err(dev, "failed to enable phy\n");
+               return ret;
+       }
+
+       pm_runtime_enable(dev);
+       ret = pm_runtime_get_sync(dev);
+       if (ret < 0) {
+               dev_err(dev, "pm_runtime_get_sync failed\n");
+               goto err_get_sync;
+       }
+
+       reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
+       reg &= ~LTSSM_EN;
+       dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
+
+       platform_set_drvdata(pdev, dra7xx);
+
+       clk_oe = devm_gpiod_get_optional(dev, "pcie-clk-oe", GPIOD_OUT_HIGH);
+       if (IS_ERR(clk_oe)) {
+               ret = PTR_ERR(clk_oe);
+               dev_err(&pdev->dev, "clk_oe gpio request failed, ret %d\n", ret);
+               goto err_gpio;
+       }
+
+       if (of_property_read_bool(np, "pcie-reset-active-low"))
+               reset = devm_gpiod_get_optional(dev, "pcie-reset", GPIOD_OUT_LOW);
+       else
+               reset = devm_gpiod_get_optional(dev, "pcie-reset", GPIOD_OUT_HIGH);
+       if (IS_ERR(reset)) {
+               ret = PTR_ERR(reset);
+               dev_err(&pdev->dev, "gpio request failed, ret %d\n", ret);
+               goto err_gpio;
+       }
+
+       reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
+       reg &= ~LTSSM_EN;
+       dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
+
+       dra7xx->link_gen = of_pci_get_max_link_speed(np);
+       if (dra7xx->link_gen < 0 || dra7xx->link_gen > 2)
+               dra7xx->link_gen = 2;
+
+       switch (mode) {
+       case DW_PCIE_RC_TYPE:
+               dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_DEVICE_TYPE,
+                                  DEVICE_TYPE_RC);
+
+               ret = dra7xx_add_pcie_port(dra7xx, pdev);
+               if (ret < 0)
+                       goto err_gpio;
+               break;
+       case DW_PCIE_EP_TYPE:
+               dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_DEVICE_TYPE,
+                                  DEVICE_TYPE_EP);
+
+               ret = dra7xx_pcie_ep_legacy_mode(dev);
+               if (ret)
+                       goto err_gpio;
+
+               ret = dra7xx_add_pcie_ep(dra7xx, pdev);
+               if (ret < 0)
+                       goto err_gpio;
+               break;
+       default:
+               dev_err(dev, "INVALID device type %d\n", mode);
+       }
+       dra7xx->mode = mode;
+
+       ret = devm_request_irq(dev, irq, dra7xx_pcie_irq_handler,
+                              IRQF_SHARED, "dra7xx-pcie-main", dra7xx);
+       if (ret) {
+               dev_err(dev, "failed to request irq\n");
+               goto err_gpio;
+       }
+
+       return 0;
+
+err_gpio:
+       pm_runtime_put(dev);
+
+err_get_sync:
+       pm_runtime_disable(dev);
+       dra7xx_pcie_disable_phy(dra7xx);
+
+err_link:
+        while (--i >= 0)
+                device_link_del(link[i]);
+                
+        return ret;
+}
 
 #ifdef CONFIG_PM_SLEEP
 static int dra7xx_pcie_suspend(struct device *dev)

pcie_phy.txt

I think one of the probe deferral has gone i.e., pcie@51800000 is working, and just not being configured as an endpoint 

Thanks & Regards,
Sujan

Hi Sujan,

Could you also post the full pcie2_phy device tree node as well? In TI device tree, these were found here: https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel/tree/arch/arm/boot/dts/dra7-l4.dtsi?h=ti-linux-5.10.y#n347.

And as a separate experiment, if we configure PCIe2 as RC, does the probe deferral error message still come up?

Regards,

Takuma