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TMS320C6655: single DDR3 Layout constraint define

Daniel Hoasov Cohen
Intellectual 300 points
Part Number: TMS320C6655

Hi Experts,

I use TMS320C6655 with a single DDR3 4Gb (256M x 16). By using DDR3 Design Req for Keystone devices documentation, I noticed that I need to create 4 Net classes groups as below:

  • SLRATE0,1 and DDRRESETn are not mentioned above, should they be in the control group or not in any group at all?
    • Trace Width of 50-Ohm okay for them??
    • Is spacing of 2W for Reset and 1.25W for SLRATE0,1 okay for them?
    • Also, what trace Width and spacing that should I define for all Control groups if I'm not using Fly-by topology? (single DDR3 connected to DSP DDR controller)

  • For all other non-differential signals (such as Address, Data, CASn, RASn, etc.) should I add 50ohm to the nets (close to the DDR3 side)?

  • In the Data Net class, I noticed it's divided into Byte Lanes. But if I'm using only a single DDR3 (Data bus DDRA00-15 from DSP DDR controller to DDR3), do I need to separate the data net class into two classes, as described below or I can keep it a single Net class?

  • For the Address Net class, what is the Trace wide and Spacing that is required if I use only a single DDR3 without Fly-by topology?
  • 0
    Intellectual 300 points

    Also, VREFSSTL, what trace Width and spacing? add it to any Net class?

  • +1 in reply to Daniel Hoasov Cohen
    TI__Guru 51695 points

    DDRRESETn, SLRATE0, SLRATE1 are 'static' signals - thus don't need to be included with any other group.  Yes - 50-ohms is OK.  You can use less spacing for static-to-static spacing, but need to use regular spacing for dynamic-to-static spacing (else the static signal could pick-up noise).

    VREFSSTL is a power reference.  It is static - so not included in any group.  Since it is a voltage reference, certainly don't want it picking up any noise.

    The trace width is determine by the desired impedance and your PCB stack-up.  50-ohms for single ended signals, 100-ohm for differential signals.  Spacing between signal impacts the amount of coupling/cross-talk - and therefore has impact to timing margins.  I would start with 3W for signals within group, 4W to signals in other groups.

    Each DDR data group should be a single byte group (as recommended in application note).  So yes 2 classes for 16b data.