DRA821U-Q1: DRA821 PCI-E x4 LANE does not work.

lee jaewook

Prodigy 55 points

Part Number: DRA821U-Q1
Other Parts Discussed in Thread: DRA821

Tool/software:

Hi.

We connected the DRA821 PCI-e 4LANE to the PCI-e switch chip on our development board (custom board) as shown below.

However, only x1LANE is connected between DRA821 and PCI-e switch.

The attached file below contains Linux LSPCI information.

If you look at the lspci information of DRA821, it looks like it is set to 1lane. (But we have set it to 4LANE in DTS.)

and The PCI-E switch was downgraded and connected to 1LANE (This is evidence that the PCI-E switch is trying to operate in 4lane.)

DRA821_LSPCI.docx

When booting, I measured the waveform of each PCI-E LANE using a scope, but only LANE 0 showed the waveform.

There is no signal from other LANE (LANE1, 2, 3)

The attached file below is DTS information.

DRA821_PCI_DTS.docx

It's not clear. After all checks, it appears that there is a problem with the DRA821 settings.

Please review LSPCI log and DTS file why DRA821 and PCI-e switch cannot be connected via PCI-E 4LANE.

11 days ago

0 Takuma Fujiwara 11 days ago

TI__Mastermind 28812 points

Hi Lee,

In terms of configuring 4 lanes, I do not see any issues in the device tree section that was shared. So, could you share the full device tree so that I can see if there are conflicts between different peripherals?

On the other hand, I did notice one things that should be fixed about the shared device tree. I do not see the "reset-gpios" property defined for PCIe.

Please make sure that all of the properties in "required" section in the device tree binding is defined: https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel/tree/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml?h=ti-linux-6.1.y#n152. Not defining these can cause unexpected behavior depending on the PCIe device being connected to DRA821.

Regards,

Takuma

0 dohyeon kim 10 days ago in reply to Takuma Fujiwara

Prodigy 70 points

I set up "reset-gpios" additionally, but the symptoms are the same.

I wonder why Link capabilities on TI PCI bridge are set to "speed 8GT/s, width x1".
Please tell me how to set Link capabilities to "speed 8GT/s, width x4".

Regards,

Dohyeon

0 Jack Cha 10 days ago in reply to Takuma Fujiwara

Mastermind 7518 points

Hi Lee

Please share your dts file to find any conflict issue as Takuma suggested at first.

Regards, Jack

0 Takuma Fujiwara 10 days ago in reply to Jack Cha

TI__Mastermind 28812 points

Hi all,

Thank you for sharing the dts. Quick look, it did not seem like there are conflicts. However, I did overlook one thing last time that could be an issue.

For pcie1_ep node, can you set status to "disabled" instead of "disable"? I assume this should not cause issues (or if it does, then issue should make PCIe not initialize at all), but it is good to follow format nonetheless.

dohyeon kim said:
Please tell me how to set Link capabilities to "speed 8GT/s, width x4".

That is a good question. I reviewed our driver and found that we might be setting max_lanes to 2 in the driver. Could you try below patch which would increase max lane to 4?

0001-setting-max_lanes-for-DRA821-to-4.patch

Regards,

Takuma

0 dohyeon kim 9 days ago in reply to Takuma Fujiwara

Prodigy 70 points

After applying the patch, it was confirmed that it works as PCI 4lane.
Thank you for your help.

Regards,

Dohyeon

+1 Takuma Fujiwara 8 days ago in reply to dohyeon kim

TI__Mastermind 28812 points

Hi Dohyeon,

Awesome to hear! We will also make a patch in our SDK as well. Probably will not go into the next SDK, but should be integrated in the next, next SDK.

Regards,

Takuma

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DRA821U-Q1: DRA821 PCI-E x4 LANE does not work.