AM69: main_mdio association with cpsw

Hi, 

Emanuele Ghidoli said:

Can TI confirm this? Is it documented

Yes, your understanding is correct. 

Main cpsw0 is cpsw9g. 

Main cpsw1 is cpsw2g in main domain

You can find the mdio mapping to cpss instance from Sysconfig tool from ti.com (Pinmux selection) 

Best Regards, 

Sudheer

Hi Sudheer, thank you.

Is it possible to configure linux to communicate over MDIO0 pins (main_cpsw1 interface) to a phy connected (MAC) to main_cpsw0 interface?

I have enabled main_cpsw1, and main_cpsw1_mdio but the communication seems not to be working (while if I connect by wire the main_cpsi0_mdio pins it is working, but not possible on our design).

Emanuele

Hi,

thank you for the fast response.
I have already tried, but I will retry in the next days.

Best regards,

Emanuele

Hi, 

Sure, please share the log with us.

Along with the changes. 

Best Regards, 

Sudheer

Hi Sudheer,
I'm able to use gpio-mdio but I would like to use the mdio bus driver.

With the following dts excerpt I'm able to communicate with the phy (main_cpsw0_port2 using cpsw0_port2_phy4).

I have to enable main_cpsw1_port1 AND main_phy0 to let cpsw0_port2_phy4 working.

I do not want to enable hardware that is not present onboard. In particular I have an additional ethernet (eth2) which is not desirable.

Have you any suggestions?

&main_pmx0 {
	/* Aquila ETH_2 MDIO */
	pinctrl_main_mdio0: main-mdio0-default-pins {
		pinctrl-single,pins = <
			J784S4_IOPAD(0x0c0, PIN_OUTPUT, 6) /* (AD38) MCASP1_AXR0.MDIO0_MDC  */ /* AQUILA B90 */
			J784S4_IOPAD(0x0bc, PIN_INPUT, 6)  /* (AD33) MCASP1_AFSX.MDIO0_MDIO */ /* AQUILA B89 */
		>;
	};
};

&main_cpsw1 {
	status = "okay";
};

&main_cpsw1_port1 {
	status = "okay";
	phy-mode = "rgmii-rxid";
	phy-handle = <&main_phy0>;
};

/* Aquila ETH_2 MDIO */
&main_cpsw1_mdio {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_main_mdio0>;

	cpsw0_port2_phy4: ethernet-phy@4 {
		status = "okay";
		reg = <4>;
		device_type = "ethernet-phy";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_eth2_int>;
		interrupt-parent = <&main_gpio0>;
		interrupts = <44 IRQ_TYPE_EDGE_FALLING>;
	};

	main_phy0: ethernet-phy@0 {
		reg = <0>;
	};
};

&main_cpsw0 {
	status = "okay";
};

/* Aquila ETH_2 SGMII PHY */
&main_cpsw0_port2 {
	phy-mode = "sgmii";
	phys = <&cpsw0_phy_gmii_sel 2>, <&serdes1_sgmii_link>;
	phy-names = "mac", "serdes";
	phy-handle = <&cpsw0_port2_phy4>;
	status = "okay";
};

Best regards,

Emanuele

Hello Sudheer,
thank you.

I agree that I have to enable main_cpsw1 but I do not understand why I have to enable "main_cpsw1_port1" and "main_phy0: ethernet-phy@0".

Both this port and this phy are not physically present on our board and I would like to remove them from the device tree.

Emanuele

Hi,

if I disable main_cpsw1_port1 (keeping enable main_cpsw1and main_cpsw1_mdio) the cpsw0_port2_phy4 is not working.

I think that main_cpsw1 is leaved in a wrong status and main_cpsw1_mdio not really working:

[    6.094877] am65-cpsw-nuss c200000.ethernet: MDIO name: c200f00.mdio
[    6.106760] am65-cpsw-nuss c200000.ethernet: initializing am65 cpsw nuss version 0x6BA02102, 0
[    6.120311] am65-cpsw-nuss c200000.ethernet: No Ext. port are available

Thank you Sudheer.

Regards,

Emanuele

Hi Doredla Sudheer Kumar,
I think it works as a temporary solution.
Is TI willing to support it without adding a fake ethernet port and phy to the device tree?

Thank you and kind regards,
Emanuele

Hi,

Emanuele Ghidoli said:

Is TI willing to support it without adding a fake ethernet port and phy to the device tree?

No. These change will not come into SDK.

We recommend to use MDIO instance corresponding to CPSW instance. 

As your are using cross MDIO instance for CPSW so, you need to use in that way.

Best Regards,
Sudheer

Doredla Sudheer Kumar said:

No. These change will not come into SDK.

Doredla Sudheer Kumar: is this the final opinion on the topic from TI? We would need to have a more flexible solution than what you provide at the moment.

Hi,

fd said:

is this the final opinion on the topic from TI? We would need to have a more flexible solution than what you provide at the moment.

Above is a flexible solution, as your are using other CPSW instance MDIO instead of one using.

When you enable CPSW instance and not enable Ethernet port, Driver is failing as it something wrong driver is enabled but ports not enabled.
So, to avoid driver error we need to enable Port.

Best Regards,
Sudheer

Doredla Sudheer Kumar said:

Above is a flexible solution, as your are using other CPSW instance MDIO instead of one using.

I am asking for confirmation that you are not willing to implement a solution in which I am not forced to enable a not existing ethernet port to get access to this specific MDIO interface.

Hi,

fd said:

Above is a flexible solution, as your are using other CPSW instance MDIO instead of one using.

I am asking for confirmation that you are not willing to implement a solution in which I am not forced to enable a not existing ethernet port to get access to this specific MDIO interface.

No, This change will not come in SDK.

It is workaround when someone is using cross MDIO instance from CPSW instance.

Best Regards,
Sudheer