Tool/software:
Hello,
I am trying to use the external reference clock for serdes1 but if I check the clock configuration (see below) nothing changes from the default configuration.
&serdes1 { status = "okay"; assigned-clock-parents = <&serdes_refclk>, <&serdes_refclk>, <&serdes_refclk>; ...
I followed this documentation:
https://software-dl.ti.com/jacinto7/esd/processor-sdk-linux-am69/09_01_00_06/exports/docs/linux/Foundational_Components/Kernel/Kernel_Drivers/SERDES/SERDES.html#selecting-between-internal-and-external-reference-clock
This is the output of k3config dump clock (it does not change anything although I changed the device tree):
|------------------------------------------------------------------------------| | VERSION INFO | |------------------------------------------------------------------------------| | K3CONF | (version 0.3-nogit built Wed Mar 06 14:29:58 UTC 2024) | | SoC | J784S4 SR1.0 | | SYSFW | ABI: 3.1 (firmware version 0x0009 '9.2.4--v09.02.04 (Kool Koala))') | |------------------------------------------------------------------------------| |----------------------------------------------------------------------------------------------------------------------------------------------------| | Device ID | Clock ID | Clock Name | Status | Clock Frequency | |----------------------------------------------------------------------------------------------------------------------------------------------------| | 198 | 0 | DEV_A72SS0_ARM0_CLK_CLK | CLK_STATE_READY | 2000000001 | | 198 | 2 | DEV_A72SS0_ARM0_DIVH_CLK8_OBSCLK_OUT_CLK | CLK_STATE_READY | 0 | | 198 | 3 | DEV_A72SS0_ARM0_MSMC_CLK_CLK | CLK_STATE_READY | 1000000000 | | 198 | 4 | DEV_A72SS0_ARM0_PLL_CTRL_CLK_CLK | CLK_STATE_READY | 500000000 | | 202 | 0 | DEV_A72SS0_CORE0_ARM0_CLK_CLK | CLK_STATE_READY | 2000000001 | | 203 | 0 | DEV_A72SS0_CORE1_ARM0_CLK_CLK | CLK_STATE_READY | 2000000001 | | 204 | 0 | DEV_A72SS0_CORE2_ARM0_CLK_CLK | CLK_STATE_READY | 2000000001 | | 205 | 0 | DEV_A72SS0_CORE3_ARM0_CLK_CLK | CLK_STATE_READY | 2000000001 | | 200 | 0 | DEV_A72SS1_ARM1_CLK_CLK | CLK_STATE_READY | 2000000001 | | 200 | 2 | DEV_A72SS1_ARM1_DIVH_CLK8_OBSCLK_OUT_CLK | CLK_STATE_READY | 0 | | 200 | 6 | DEV_A72SS1_ARM1_PLL_CTRL_CLK_CLK | CLK_STATE_READY | 500000000 | | 206 | 0 | DEV_A72SS1_CORE0_ARM1_CLK_CLK | CLK_STATE_READY | 2000000001 | | 207 | 0 | DEV_A72SS1_CORE1_ARM1_CLK_CLK | CLK_STATE_READY | 2000000001 | | 208 | 0 | DEV_A72SS1_CORE2_ARM1_CLK_CLK | CLK_STATE_READY | 2000000001 | | 209 | 0 | DEV_A72SS1_CORE3_ARM1_CLK_CLK | CLK_STATE_READY | 2000000001 | | 186 | 0 | DEV_AGGR_ATB0_DBG_CLK | CLK_STATE_READY | 250000000 | | 2 | 0 | DEV_ATL0_ATL_CLK | CLK_STATE_READY | 294912000 | | 2 | 1 | DEV_ATL0_ATL_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT1_CLK | CLK_STATE_READY | 294912000 | | 2 | 2 | DEV_ATL0_ATL_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | 2 | 5 | DEV_ATL0_ATL_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT7_CLK | CLK_STATE_READY | 200000000 | | 2 | 6 | DEV_ATL0_ATL_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 2 | 7 | DEV_ATL0_ATL_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | 2 | 9 | DEV_ATL0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_READY | 0 | | 2 | 10 | DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_READY | 0 | | 2 | 11 | DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_READY | 0 | | 2 | 12 | DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_READY | 0 | | 2 | 13 | DEV_ATL0_ATL_IO_PORT_AWS | CLK_STATE_READY | 0 | | 2 | 14 | DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT | CLK_STATE_READY | 0 | | 2 | 15 | DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT | CLK_STATE_READY | 0 | | 2 | 16 | DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT_DUP0 | CLK_STATE_READY | 0 | | 2 | 17 | DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT_DUP0 | CLK_STATE_READY | 0 | | 2 | 18 | DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT_DUP0 | CLK_STATE_READY | 0 | | 2 | 26 | DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT_DUP0 | CLK_STATE_READY | 0 | | 2 | 27 | DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT_DUP0 | CLK_STATE_READY | 0 | | 2 | 28 | DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT | CLK_STATE_READY | 0 | | 2 | 29 | DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT | CLK_STATE_READY | 0 | | 2 | 30 | DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT | CLK_STATE_READY | 0 | | 2 | 38 | DEV_ATL0_ATL_IO_PORT_AWS_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 2 | 39 | DEV_ATL0_ATL_IO_PORT_AWS_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | 2 | 46 | DEV_ATL0_ATL_IO_PORT_AWS_1 | CLK_STATE_READY | 0 | | 2 | 47 | DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT | CLK_STATE_READY | 0 | | 2 | 48 | DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT | CLK_STATE_READY | 0 | | 2 | 49 | DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT_DUP0 | CLK_STATE_READY | 0 | | 2 | 50 | DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT_DUP0 | CLK_STATE_READY | 0 | | 2 | 51 | DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT_DUP0 | CLK_STATE_READY | 0 | | 2 | 59 | DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT_DUP0 | CLK_STATE_READY | 0 | | 2 | 60 | DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT_DUP0 | CLK_STATE_READY | 0 | | 2 | 61 | DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT | CLK_STATE_READY | 0 | | 2 | 62 | DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT | CLK_STATE_READY | 0 | | 2 | 63 | DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT | CLK_STATE_READY | 0 | | 2 | 71 | DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 2 | 72 | DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | 2 | 85 | DEV_ATL0_ATL_IO_PORT_AWS_2 | CLK_STATE_READY | 0 | | 2 | 86 | DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT | CLK_STATE_READY | 0 | | 2 | 87 | DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT | CLK_STATE_READY | 0 | | 2 | 88 | DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT_DUP0 | CLK_STATE_READY | 0 | | 2 | 89 | DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT_DUP0 | CLK_STATE_READY | 0 | | 2 | 90 | DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT_DUP0 | CLK_STATE_READY | 0 | | 2 | 98 | DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT_DUP0 | CLK_STATE_READY | 0 | | 2 | 99 | DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT_DUP0 | CLK_STATE_READY | 0 | | 2 | 100 | DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT | CLK_STATE_READY | 0 | | 2 | 101 | DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT | CLK_STATE_READY | 0 | | 2 | 102 | DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT | CLK_STATE_READY | 0 | | 2 | 110 | DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 2 | 111 | DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | 2 | 118 | DEV_ATL0_ATL_IO_PORT_AWS_3 | CLK_STATE_READY | 0 | | 2 | 119 | DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT | CLK_STATE_READY | 0 | | 2 | 120 | DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT | CLK_STATE_READY | 0 | | 2 | 121 | DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT_DUP0 | CLK_STATE_READY | 0 | | 2 | 122 | DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT_DUP0 | CLK_STATE_READY | 0 | | 2 | 123 | DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT_DUP0 | CLK_STATE_READY | 0 | | 2 | 131 | DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT_DUP0 | CLK_STATE_READY | 0 | | 2 | 132 | DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT_DUP0 | CLK_STATE_READY | 0 | | 2 | 133 | DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT | CLK_STATE_READY | 0 | | 2 | 134 | DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT | CLK_STATE_READY | 0 | | 2 | 135 | DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT | CLK_STATE_READY | 0 | | 2 | 143 | DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 2 | 144 | DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | 2 | 157 | DEV_ATL0_ATL_IO_PORT_BWS | CLK_STATE_READY | 0 | | 2 | 158 | DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_0_MCASP_AFSR_POUT | CLK_STATE_READY | 0 | | 2 | 159 | DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_1_MCASP_AFSR_POUT | CLK_STATE_READY | 0 | | 2 | 160 | DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_2_MCASP_AFSR_POUT | CLK_STATE_READY | 0 | | 2 | 161 | DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_3_MCASP_AFSR_POUT | CLK_STATE_READY | 0 | | 2 | 162 | DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_4_MCASP_AFSR_POUT | CLK_STATE_READY | 0 | | 2 | 170 | DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT | CLK_STATE_READY | 0 | | 2 | 171 | DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT | CLK_STATE_READY | 0 | | 2 | 172 | DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT | CLK_STATE_READY | 0 | | 2 | 173 | DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT | CLK_STATE_READY | 0 | | 2 | 174 | DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT | CLK_STATE_READY | 0 | | 2 | 182 | DEV_ATL0_ATL_IO_PORT_BWS_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 2 | 183 | DEV_ATL0_ATL_IO_PORT_BWS_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | 2 | 190 | DEV_ATL0_ATL_IO_PORT_BWS_1 | CLK_STATE_READY | 0 | | 2 | 191 | DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_0_MCASP_AFSR_POUT | CLK_STATE_READY | 0 | | 2 | 192 | DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_1_MCASP_AFSR_POUT | CLK_STATE_READY | 0 | | 2 | 193 | DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_2_MCASP_AFSR_POUT | CLK_STATE_READY | 0 | | 2 | 194 | DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_3_MCASP_AFSR_POUT | CLK_STATE_READY | 0 | | 2 | 195 | DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_4_MCASP_AFSR_POUT | CLK_STATE_READY | 0 | | 2 | 203 | DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT | CLK_STATE_READY | 0 | | 2 | 204 | DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT | CLK_STATE_READY | 0 | | 2 | 205 | DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT | CLK_STATE_READY | 0 | | 2 | 206 | DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT | CLK_STATE_READY | 0 | | 2 | 207 | DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT | CLK_STATE_READY | 0 | | 2 | 215 | DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 2 | 216 | DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | 2 | 229 | DEV_ATL0_ATL_IO_PORT_BWS_2 | CLK_STATE_READY | 0 | | 2 | 230 | DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_0_MCASP_AFSR_POUT | CLK_STATE_READY | 0 | | 2 | 231 | DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_1_MCASP_AFSR_POUT | CLK_STATE_READY | 0 | | 2 | 232 | DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_2_MCASP_AFSR_POUT | CLK_STATE_READY | 0 | | 2 | 233 | DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_3_MCASP_AFSR_POUT | CLK_STATE_READY | 0 | | 2 | 234 | DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_4_MCASP_AFSR_POUT | CLK_STATE_READY | 0 | | 2 | 242 | DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT | CLK_STATE_READY | 0 | | 2 | 243 | DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT | CLK_STATE_READY | 0 | | 2 | 244 | DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT | CLK_STATE_READY | 0 | | 2 | 245 | DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT | CLK_STATE_READY | 0 | | 2 | 246 | DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT | CLK_STATE_READY | 0 | | 2 | 254 | DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 2 | 255 | DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | 2 | 262 | DEV_ATL0_ATL_IO_PORT_BWS_3 | CLK_STATE_READY | 0 | | 2 | 263 | DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_0_MCASP_AFSR_POUT | CLK_STATE_READY | 0 | | 2 | 264 | DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_1_MCASP_AFSR_POUT | CLK_STATE_READY | 0 | | 2 | 265 | DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_2_MCASP_AFSR_POUT | CLK_STATE_READY | 0 | | 2 | 266 | DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_3_MCASP_AFSR_POUT | CLK_STATE_READY | 0 | | 2 | 267 | DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_4_MCASP_AFSR_POUT | CLK_STATE_READY | 0 | | 2 | 275 | DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT | CLK_STATE_READY | 0 | | 2 | 276 | DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT | CLK_STATE_READY | 0 | | 2 | 277 | DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT | CLK_STATE_READY | 0 | | 2 | 278 | DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT | CLK_STATE_READY | 0 | | 2 | 279 | DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT | CLK_STATE_READY | 0 | | 2 | 287 | DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 2 | 288 | DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | 2 | 301 | DEV_ATL0_VBUS_CLK | CLK_STATE_READY | 250000000 | | 157 | 0 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN | CLK_STATE_NOT_READY | 0 | | 157 | 1 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | 157 | 2 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | 157 | 3 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | 157 | 4 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | 157 | 5 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | 157 | 13 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | 157 | 14 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | 157 | 15 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | 157 | 16 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | 157 | 17 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | 157 | 25 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | 157 | 26 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | 157 | 27 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | 157 | 28 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | 157 | 29 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | 157 | 33 | DEV_BOARD0_AUDIO_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 157 | 34 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN | CLK_STATE_NOT_READY | 0 | | 157 | 35 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | 157 | 36 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | 157 | 37 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | 157 | 38 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | 157 | 39 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | 157 | 47 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | 157 | 48 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | 157 | 49 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | 157 | 50 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | 157 | 51 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | 157 | 59 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | 157 | 60 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | 157 | 61 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | 157 | 62 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | 157 | 63 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | 157 | 67 | DEV_BOARD0_AUDIO_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | 157 | 68 | DEV_BOARD0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | 157 | 69 | DEV_BOARD0_CSI0_RXCLKN_OUT | CLK_STATE_READY | 0 | | 157 | 70 | DEV_BOARD0_CSI0_RXCLKP_OUT | CLK_STATE_READY | 0 | | 157 | 71 | DEV_BOARD0_CSI0_TXCLKN_IN | CLK_STATE_READY | 0 | | 157 | 72 | DEV_BOARD0_CSI0_TXCLKP_IN | CLK_STATE_READY | 0 | | 157 | 73 | DEV_BOARD0_CSI1_RXCLKN_OUT | CLK_STATE_READY | 0 | | 157 | 74 | DEV_BOARD0_CSI1_RXCLKP_OUT | CLK_STATE_READY | 0 | | 157 | 75 | DEV_BOARD0_CSI1_TXCLKN_IN | CLK_STATE_READY | 0 | | 157 | 76 | DEV_BOARD0_CSI1_TXCLKP_IN | CLK_STATE_READY | 0 | | 157 | 77 | DEV_BOARD0_CSI2_RXCLKN_OUT | CLK_STATE_READY | 0 | | 157 | 78 | DEV_BOARD0_CSI2_RXCLKP_OUT | CLK_STATE_READY | 0 | | 157 | 95 | DEV_BOARD0_DSI0_TXCLKN_IN | CLK_STATE_READY | 0 | | 157 | 96 | DEV_BOARD0_DSI0_TXCLKP_IN | CLK_STATE_READY | 0 | | 157 | 97 | DEV_BOARD0_DSI1_TXCLKN_IN | CLK_STATE_READY | 0 | | 157 | 98 | DEV_BOARD0_DSI1_TXCLKP_IN | CLK_STATE_READY | 0 | | 157 | 99 | DEV_BOARD0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | 157 | 100 | DEV_BOARD0_GPMC0_CLKOUT_IN | CLK_STATE_READY | 0 | | 157 | 101 | DEV_BOARD0_GPMC0_CLK_OUT | CLK_STATE_READY | 0 | | 157 | 102 | DEV_BOARD0_GPMC0_FCLK_MUX_IN | CLK_STATE_READY | 133333333 | | 157 | 103 | DEV_BOARD0_HYP0_RXFLCLK_IN | CLK_STATE_READY | 0 | | 157 | 104 | DEV_BOARD0_HYP0_RXPMCLK_OUT | CLK_STATE_READY | 0 | | 157 | 105 | DEV_BOARD0_HYP0_TXFLCLK_OUT | CLK_STATE_READY | 0 | | 157 | 106 | DEV_BOARD0_HYP0_TXPMCLK_IN | CLK_STATE_READY | 0 | | 157 | 107 | DEV_BOARD0_HYP1_RXFLCLK_IN | CLK_STATE_READY | 0 | | 157 | 108 | DEV_BOARD0_HYP1_RXPMCLK_OUT | CLK_STATE_READY | 0 | | 157 | 109 | DEV_BOARD0_HYP1_TXFLCLK_OUT | CLK_STATE_READY | 0 | | 157 | 110 | DEV_BOARD0_HYP1_TXPMCLK_IN | CLK_STATE_READY | 0 | | 157 | 111 | DEV_BOARD0_I2C0_SCL_IN | CLK_STATE_READY | 0 | | 157 | 112 | DEV_BOARD0_I2C0_SCL_OUT | CLK_STATE_READY | 0 | | 157 | 113 | DEV_BOARD0_I2C1_SCL_IN | CLK_STATE_READY | 0 | | 157 | 114 | DEV_BOARD0_I2C1_SCL_OUT | CLK_STATE_READY | 0 | | 157 | 115 | DEV_BOARD0_I2C2_SCL_IN | CLK_STATE_READY | 0 | | 157 | 116 | DEV_BOARD0_I2C2_SCL_OUT | CLK_STATE_READY | 0 | | 157 | 117 | DEV_BOARD0_I2C3_SCL_IN | CLK_STATE_READY | 0 | | 157 | 118 | DEV_BOARD0_I2C3_SCL_OUT | CLK_STATE_READY | 0 | | 157 | 119 | DEV_BOARD0_I2C4_SCL_IN | CLK_STATE_READY | 0 | | 157 | 120 | DEV_BOARD0_I2C4_SCL_OUT | CLK_STATE_READY | 0 | | 157 | 121 | DEV_BOARD0_I2C5_SCL_IN | CLK_STATE_READY | 0 | | 157 | 122 | DEV_BOARD0_I2C5_SCL_OUT | CLK_STATE_READY | 0 | | 157 | 123 | DEV_BOARD0_I2C6_SCL_IN | CLK_STATE_READY | 0 | | 157 | 124 | DEV_BOARD0_I2C6_SCL_OUT | CLK_STATE_READY | 0 | | 157 | 125 | DEV_BOARD0_LED_CLK_OUT | CLK_STATE_READY | 0 | | 157 | 126 | DEV_BOARD0_MCAN0_RX_OUT | CLK_STATE_READY | 0 | | 157 | 127 | DEV_BOARD0_MCAN10_RX_OUT | CLK_STATE_READY | 0 | | 157 | 128 | DEV_BOARD0_MCAN11_RX_OUT | CLK_STATE_READY | 0 | | 157 | 129 | DEV_BOARD0_MCAN12_RX_OUT | CLK_STATE_READY | 0 | | 157 | 130 | DEV_BOARD0_MCAN13_RX_OUT | CLK_STATE_READY | 0 | | 157 | 131 | DEV_BOARD0_MCAN14_RX_OUT | CLK_STATE_READY | 0 | | 157 | 132 | DEV_BOARD0_MCAN15_RX_OUT | CLK_STATE_READY | 0 | | 157 | 133 | DEV_BOARD0_MCAN16_RX_OUT | CLK_STATE_READY | 0 | | 157 | 134 | DEV_BOARD0_MCAN17_RX_OUT | CLK_STATE_READY | 0 | | 157 | 135 | DEV_BOARD0_MCAN1_RX_OUT | CLK_STATE_READY | 0 | | 157 | 136 | DEV_BOARD0_MCAN2_RX_OUT | CLK_STATE_READY | 0 | | 157 | 137 | DEV_BOARD0_MCAN3_RX_OUT | CLK_STATE_READY | 0 | | 157 | 138 | DEV_BOARD0_MCAN4_RX_OUT | CLK_STATE_READY | 0 | | 157 | 139 | DEV_BOARD0_MCAN5_RX_OUT | CLK_STATE_READY | 0 | | 157 | 140 | DEV_BOARD0_MCAN6_RX_OUT | CLK_STATE_READY | 0 | | 157 | 141 | DEV_BOARD0_MCAN7_RX_OUT | CLK_STATE_READY | 0 | | 157 | 142 | DEV_BOARD0_MCAN8_RX_OUT | CLK_STATE_READY | 0 | | 157 | 143 | DEV_BOARD0_MCAN9_RX_OUT | CLK_STATE_READY | 0 | | 157 | 144 | DEV_BOARD0_MCASP0_ACLKR_IN | CLK_STATE_READY | 0 | | 157 | 145 | DEV_BOARD0_MCASP0_ACLKR_OUT | CLK_STATE_READY | 0 | | 157 | 146 | DEV_BOARD0_MCASP0_ACLKX_IN | CLK_STATE_READY | 0 | | 157 | 147 | DEV_BOARD0_MCASP0_ACLKX_OUT | CLK_STATE_READY | 0 | | 157 | 148 | DEV_BOARD0_MCASP0_AFSR_OUT | CLK_STATE_READY | 0 | | 157 | 149 | DEV_BOARD0_MCASP0_AFSX_OUT | CLK_STATE_READY | 0 | | 157 | 150 | DEV_BOARD0_MCASP1_ACLKR_IN | CLK_STATE_READY | 0 | | 157 | 151 | DEV_BOARD0_MCASP1_ACLKR_OUT | CLK_STATE_READY | 0 | | 157 | 152 | DEV_BOARD0_MCASP1_ACLKX_IN | CLK_STATE_READY | 0 | | 157 | 153 | DEV_BOARD0_MCASP1_ACLKX_OUT | CLK_STATE_READY | 0 | | 157 | 154 | DEV_BOARD0_MCASP1_AFSR_OUT | CLK_STATE_READY | 0 | | 157 | 155 | DEV_BOARD0_MCASP1_AFSX_OUT | CLK_STATE_READY | 0 | | 157 | 156 | DEV_BOARD0_MCASP2_ACLKR_IN | CLK_STATE_READY | 0 | | 157 | 157 | DEV_BOARD0_MCASP2_ACLKR_OUT | CLK_STATE_READY | 0 | | 157 | 158 | DEV_BOARD0_MCASP2_ACLKX_IN | CLK_STATE_READY | 0 | | 157 | 159 | DEV_BOARD0_MCASP2_ACLKX_OUT | CLK_STATE_READY | 0 | | 157 | 160 | DEV_BOARD0_MCASP2_AFSR_OUT | CLK_STATE_READY | 0 | | 157 | 161 | DEV_BOARD0_MCASP2_AFSX_OUT | CLK_STATE_READY | 0 | | 157 | 162 | DEV_BOARD0_MCASP3_ACLKR_IN | CLK_STATE_READY | 0 | | 157 | 163 | DEV_BOARD0_MCASP3_ACLKR_OUT | CLK_STATE_READY | 0 | | 157 | 164 | DEV_BOARD0_MCASP3_ACLKX_IN | CLK_STATE_READY | 0 | | 157 | 165 | DEV_BOARD0_MCASP3_ACLKX_OUT | CLK_STATE_READY | 0 | | 157 | 166 | DEV_BOARD0_MCASP3_AFSR_OUT | CLK_STATE_READY | 0 | | 157 | 167 | DEV_BOARD0_MCASP3_AFSX_OUT | CLK_STATE_READY | 0 | | 157 | 168 | DEV_BOARD0_MCASP4_ACLKR_IN | CLK_STATE_READY | 0 | | 157 | 169 | DEV_BOARD0_MCASP4_ACLKR_OUT | CLK_STATE_READY | 0 | | 157 | 170 | DEV_BOARD0_MCASP4_ACLKX_IN | CLK_STATE_READY | 0 | | 157 | 171 | DEV_BOARD0_MCASP4_ACLKX_OUT | CLK_STATE_READY | 0 | | 157 | 172 | DEV_BOARD0_MCASP4_AFSR_OUT | CLK_STATE_READY | 0 | | 157 | 173 | DEV_BOARD0_MCASP4_AFSX_OUT | CLK_STATE_READY | 0 | | 157 | 174 | DEV_BOARD0_MCU_CLKOUT0_IN | CLK_STATE_READY | 25000000 | | 157 | 175 | DEV_BOARD0_MCU_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT0_CLK5 | CLK_STATE_READY | 50000000 | | 157 | 176 | DEV_BOARD0_MCU_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT0_CLK10 | CLK_STATE_READY | 25000000 | | 157 | 177 | DEV_BOARD0_MCU_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | 157 | 178 | DEV_BOARD0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 157 | 179 | DEV_BOARD0_MCU_HYPERBUS0_CK_IN | CLK_STATE_READY | 0 | | 157 | 180 | DEV_BOARD0_MCU_HYPERBUS0_CKN_IN | CLK_STATE_READY | 0 | | 157 | 181 | DEV_BOARD0_MCU_I2C0_SCL_IN | CLK_STATE_READY | 0 | | 157 | 182 | DEV_BOARD0_MCU_I2C0_SCL_OUT | CLK_STATE_READY | 0 | | 157 | 183 | DEV_BOARD0_MCU_I2C1_SCL_IN | CLK_STATE_READY | 0 | | 157 | 184 | DEV_BOARD0_MCU_I2C1_SCL_OUT | CLK_STATE_READY | 0 | | 157 | 185 | DEV_BOARD0_MCU_I3C0_SCL_IN | CLK_STATE_READY | 0 | | 157 | 186 | DEV_BOARD0_MCU_I3C0_SCL_OUT | CLK_STATE_READY | 0 | | 157 | 187 | DEV_BOARD0_MCU_I3C0_SDA_OUT | CLK_STATE_READY | 0 | | 157 | 188 | DEV_BOARD0_MCU_MCAN0_RX_OUT | CLK_STATE_READY | 0 | | 157 | 189 | DEV_BOARD0_MCU_MCAN1_RX_OUT | CLK_STATE_READY | 0 | | 157 | 190 | DEV_BOARD0_MCU_MDIO0_MDC_IN | CLK_STATE_READY | 0 | | 157 | 191 | DEV_BOARD0_MCU_OBSCLK0_IN | CLK_STATE_READY | 1000000000 | | 157 | 192 | DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_MCU_OBSCLK_DIV_OUT0 | CLK_STATE_READY | 1000000000 | | 157 | 193 | DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 24000000 | | 157 | 224 | DEV_BOARD0_MCU_OSPI0_CLK_IN | CLK_STATE_READY | 0 | | 157 | 225 | DEV_BOARD0_MCU_OSPI0_DQS_OUT | CLK_STATE_READY | 0 | | 157 | 226 | DEV_BOARD0_MCU_OSPI0_LBCLKO_IN | CLK_STATE_READY | 0 | | 157 | 227 | DEV_BOARD0_MCU_OSPI0_LBCLKO_OUT | CLK_STATE_READY | 0 | | 157 | 228 | DEV_BOARD0_MCU_OSPI1_CLK_IN | CLK_STATE_READY | 0 | | 157 | 229 | DEV_BOARD0_MCU_OSPI1_DQS_OUT | CLK_STATE_READY | 0 | | 157 | 230 | DEV_BOARD0_MCU_OSPI1_LBCLKO_IN | CLK_STATE_READY | 0 | | 157 | 231 | DEV_BOARD0_MCU_OSPI1_LBCLKO_OUT | CLK_STATE_READY | 0 | | 157 | 232 | DEV_BOARD0_MCU_RGMII1_RXC_OUT | CLK_STATE_READY | 0 | | 157 | 233 | DEV_BOARD0_MCU_RGMII1_TXC_IN | CLK_STATE_READY | 0 | | 157 | 234 | DEV_BOARD0_MCU_RMII1_REF_CLK_OUT | CLK_STATE_READY | 0 | | 157 | 235 | DEV_BOARD0_MCU_SPI0_CLK_IN | CLK_STATE_READY | 0 | | 157 | 236 | DEV_BOARD0_MCU_SPI0_CLK_OUT | CLK_STATE_READY | 0 | | 157 | 237 | DEV_BOARD0_MCU_SPI1_CLK_IN | CLK_STATE_READY | 0 | | 157 | 238 | DEV_BOARD0_MCU_SPI1_CLK_OUT | CLK_STATE_READY | 0 | | 157 | 239 | DEV_BOARD0_MCU_SYSCLKOUT0_IN | CLK_STATE_READY | 250000000 | | 157 | 240 | DEV_BOARD0_MDIO0_MDC_IN | CLK_STATE_READY | 0 | | 157 | 241 | DEV_BOARD0_MDIO1_MDC_IN | CLK_STATE_READY | 0 | | 157 | 243 | DEV_BOARD0_MMC1_CLKLB_IN | CLK_STATE_READY | 0 | | 157 | 244 | DEV_BOARD0_MMC1_CLKLB_OUT | CLK_STATE_READY | 0 | | 157 | 245 | DEV_BOARD0_MMC1_CLK_IN | CLK_STATE_READY | 0 | | 157 | 246 | DEV_BOARD0_MMC1_CLK_OUT | CLK_STATE_READY | 0 | | 157 | 247 | DEV_BOARD0_OBSCLK0_IN | CLK_STATE_READY | 500000000 | | 157 | 248 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK | CLK_STATE_READY | 500000000 | | 157 | 249 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT0_CLK | CLK_STATE_READY | 192000000 | | 157 | 250 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK | CLK_STATE_READY | 600000000 | | 157 | 251 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT0_CLK | CLK_STATE_READY | 250000000 | | 157 | 252 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK | CLK_STATE_READY | 196608000 | | 157 | 253 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_5_HSDIVOUT0_CLK | CLK_STATE_READY | 400000000 | | 157 | 254 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_6_HSDIVOUT0_CLK | CLK_STATE_READY | 800000000 | | 157 | 255 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_26_HSDIVOUT0_CLK | CLK_STATE_READY | 1066500000 | | 157 | 256 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_27_HSDIVOUT0_CLK | CLK_STATE_READY | 1066500000 | | 157 | 257 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_28_HSDIVOUT0_CLK | CLK_STATE_READY | 1066500000 | | 157 | 260 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_12_HSDIVOUT0_CLK | CLK_STATE_READY | 1066500000 | | 157 | 261 | DEV_BOARD0_OBSCLK0_IN_PARENT_OBSCLK1_MUX_OUT0 | CLK_STATE_NOT_READY | 0 | | 157 | 262 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV2_16FFT_MAIN_14_HSDIVOUT0_CLK | CLK_STATE_READY | 1000000000 | | 157 | 264 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK | CLK_STATE_READY | 594000000 | | 157 | 265 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT0_CLK | CLK_STATE_READY | 594000000 | | 157 | 267 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_19_HSDIVOUT0_CLK | CLK_STATE_READY | 600000000 | | 157 | 268 | DEV_BOARD0_OBSCLK0_IN_PARENT_UFSHCI2P1SS_16FFC_MAIN_0_UFSHCI_MPHY_TX_REF_SYMBOLCLK | CLK_STATE_NOT_READY | 0 | | 157 | 269 | DEV_BOARD0_OBSCLK0_IN_PARENT_UFSHCI2P1SS_16FFC_MAIN_0_UFSHCI_MPHY_M31_VCO_19P2M_CLK | CLK_STATE_NOT_READY | 0 | | 157 | 270 | DEV_BOARD0_OBSCLK0_IN_PARENT_UFSHCI2P1SS_16FFC_MAIN_0_UFSHCI_MPHY_M31_VCO_26M_CLK | CLK_STATE_NOT_READY | 0 | | 157 | 273 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_25_HSDIVOUT0_CLK | CLK_STATE_READY | 480000000 | | 157 | 274 | DEV_BOARD0_OBSCLK0_IN_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | 157 | 275 | DEV_BOARD0_OBSCLK0_IN_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | 157 | 276 | DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_LPXOSC_CLKOUT | CLK_STATE_READY | 32768 | | 157 | 277 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK_DUP0 | CLK_STATE_READY | 500000000 | | 157 | 278 | DEV_BOARD0_OBSCLK0_IN_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 157 | 279 | DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 24000000 | | 157 | 280 | DEV_BOARD0_OBSCLK1_IN | CLK_STATE_READY | 500000000 | | 157 | 281 | DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK | CLK_STATE_READY | 500000000 | | 157 | 282 | DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT0_CLK | CLK_STATE_READY | 192000000 | | 157 | 283 | DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK | CLK_STATE_READY | 600000000 | | 157 | 284 | DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT0_CLK | CLK_STATE_READY | 250000000 | | 157 | 285 | DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK | CLK_STATE_READY | 196608000 | | 157 | 286 | DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV1_16FFT_MAIN_5_HSDIVOUT0_CLK | CLK_STATE_READY | 400000000 | | 157 | 287 | DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV0_16FFT_MAIN_6_HSDIVOUT0_CLK | CLK_STATE_READY | 800000000 | | 157 | 288 | DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV0_16FFT_MAIN_26_HSDIVOUT0_CLK | CLK_STATE_READY | 1066500000 | | 157 | 289 | DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV0_16FFT_MAIN_27_HSDIVOUT0_CLK | CLK_STATE_READY | 1066500000 | | 157 | 290 | DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV0_16FFT_MAIN_28_HSDIVOUT0_CLK | CLK_STATE_READY | 1066500000 | | 157 | 293 | DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV0_16FFT_MAIN_12_HSDIVOUT0_CLK | CLK_STATE_READY | 1066500000 | | 157 | 294 | DEV_BOARD0_OBSCLK1_IN_PARENT_OBSCLK1_MUX_OUT0 | CLK_STATE_NOT_READY | 0 | | 157 | 295 | DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV2_16FFT_MAIN_14_HSDIVOUT0_CLK | CLK_STATE_READY | 1000000000 | | 157 | 297 | DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK | CLK_STATE_READY | 594000000 | | 157 | 298 | DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT0_CLK | CLK_STATE_READY | 594000000 | | 157 | 300 | DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV1_16FFT_MAIN_19_HSDIVOUT0_CLK | CLK_STATE_READY | 600000000 | | 157 | 301 | DEV_BOARD0_OBSCLK1_IN_PARENT_UFSHCI2P1SS_16FFC_MAIN_0_UFSHCI_MPHY_TX_REF_SYMBOLCLK | CLK_STATE_NOT_READY | 0 | | 157 | 302 | DEV_BOARD0_OBSCLK1_IN_PARENT_UFSHCI2P1SS_16FFC_MAIN_0_UFSHCI_MPHY_M31_VCO_19P2M_CLK | CLK_STATE_NOT_READY | 0 | | 157 | 303 | DEV_BOARD0_OBSCLK1_IN_PARENT_UFSHCI2P1SS_16FFC_MAIN_0_UFSHCI_MPHY_M31_VCO_26M_CLK | CLK_STATE_NOT_READY | 0 | | 157 | 306 | DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV1_16FFT_MAIN_25_HSDIVOUT0_CLK | CLK_STATE_READY | 480000000 | | 157 | 307 | DEV_BOARD0_OBSCLK1_IN_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | 157 | 308 | DEV_BOARD0_OBSCLK1_IN_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | 157 | 309 | DEV_BOARD0_OBSCLK1_IN_PARENT_GLUELOGIC_LPXOSC_CLKOUT | CLK_STATE_READY | 32768 | | 157 | 310 | DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK_DUP0 | CLK_STATE_READY | 500000000 | | 157 | 311 | DEV_BOARD0_OBSCLK1_IN_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 157 | 312 | DEV_BOARD0_OBSCLK1_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 24000000 | | 157 | 313 | DEV_BOARD0_PCIE_REFCLK0_N_OUT_IN | CLK_STATE_READY | 0 | | 157 | 314 | DEV_BOARD0_PCIE_REFCLK0_P_OUT_IN | CLK_STATE_READY | 0 | | 157 | 315 | DEV_BOARD0_PCIE_REFCLK1_N_OUT_IN | CLK_STATE_READY | 0 | | 157 | 316 | DEV_BOARD0_PCIE_REFCLK1_P_OUT_IN | CLK_STATE_READY | 0 | | 157 | 317 | DEV_BOARD0_PCIE_REFCLK2_N_OUT_IN | CLK_STATE_READY | 0 | | 157 | 318 | DEV_BOARD0_PCIE_REFCLK2_P_OUT_IN | CLK_STATE_READY | 0 | | 157 | 319 | DEV_BOARD0_PCIE_REFCLK3_N_OUT_IN | CLK_STATE_READY | 0 | | 157 | 320 | DEV_BOARD0_PCIE_REFCLK3_P_OUT_IN | CLK_STATE_READY | 0 | | 157 | 321 | DEV_BOARD0_RGMII1_RXC_OUT | CLK_STATE_READY | 0 | | 157 | 322 | DEV_BOARD0_RGMII1_TXC_IN | CLK_STATE_READY | 0 | | 157 | 323 | DEV_BOARD0_RMII_REF_CLK_OUT | CLK_STATE_READY | 0 | | 157 | 324 | DEV_BOARD0_SERDES0_REFCLK_N_IN | CLK_STATE_READY | 0 | | 157 | 325 | DEV_BOARD0_SERDES0_REFCLK_N_OUT | CLK_STATE_READY | 0 | | 157 | 326 | DEV_BOARD0_SERDES0_REFCLK_P_IN | CLK_STATE_READY | 0 | | 157 | 327 | DEV_BOARD0_SERDES0_REFCLK_P_OUT | CLK_STATE_READY | 0 | | 157 | 328 | DEV_BOARD0_SERDES1_REFCLK_N_IN | CLK_STATE_READY | 0 | | 157 | 329 | DEV_BOARD0_SERDES1_REFCLK_N_OUT | CLK_STATE_READY | 0 | | 157 | 330 | DEV_BOARD0_SERDES1_REFCLK_P_IN | CLK_STATE_READY | 0 | | 157 | 331 | DEV_BOARD0_SERDES1_REFCLK_P_OUT | CLK_STATE_READY | 0 | | 157 | 332 | DEV_BOARD0_SERDES2_REFCLK_N_IN | CLK_STATE_READY | 0 | | 157 | 333 | DEV_BOARD0_SERDES2_REFCLK_N_OUT | CLK_STATE_READY | 0 | | 157 | 334 | DEV_BOARD0_SERDES2_REFCLK_P_IN | CLK_STATE_READY | 0 | | 157 | 335 | DEV_BOARD0_SERDES2_REFCLK_P_OUT | CLK_STATE_READY | 0 | | 157 | 336 | DEV_BOARD0_SERDES4_REFCLK_N_IN | CLK_STATE_READY | 0 | | 157 | 337 | DEV_BOARD0_SERDES4_REFCLK_N_OUT | CLK_STATE_READY | 0 | | 157 | 338 | DEV_BOARD0_SERDES4_REFCLK_P_IN | CLK_STATE_READY | 0 | | 157 | 339 | DEV_BOARD0_SERDES4_REFCLK_P_OUT | CLK_STATE_READY | 0 | | 157 | 340 | DEV_BOARD0_SPI0_CLK_IN | CLK_STATE_READY | 0 | | 157 | 341 | DEV_BOARD0_SPI0_CLK_OUT | CLK_STATE_READY | 0 | | 157 | 342 | DEV_BOARD0_SPI1_CLK_IN | CLK_STATE_READY | 0 | | 157 | 343 | DEV_BOARD0_SPI1_CLK_OUT | CLK_STATE_READY | 0 | | 157 | 344 | DEV_BOARD0_SPI2_CLK_IN | CLK_STATE_READY | 0 | | 157 | 345 | DEV_BOARD0_SPI2_CLK_OUT | CLK_STATE_READY | 0 | | 157 | 346 | DEV_BOARD0_SPI3_CLK_IN | CLK_STATE_READY | 0 | | 157 | 347 | DEV_BOARD0_SPI3_CLK_OUT | CLK_STATE_READY | 0 | | 157 | 348 | DEV_BOARD0_SPI5_CLK_IN | CLK_STATE_READY | 0 | | 157 | 349 | DEV_BOARD0_SPI5_CLK_OUT | CLK_STATE_READY | 0 | | 157 | 350 | DEV_BOARD0_SPI6_CLK_IN | CLK_STATE_READY | 0 | | 157 | 351 | DEV_BOARD0_SPI6_CLK_OUT | CLK_STATE_READY | 0 | | 157 | 352 | DEV_BOARD0_SPI7_CLK_IN | CLK_STATE_READY | 0 | | 157 | 353 | DEV_BOARD0_SPI7_CLK_OUT | CLK_STATE_READY | 0 | | 157 | 354 | DEV_BOARD0_SYSCLKOUT0_IN | CLK_STATE_READY | 125000000 | | 157 | 355 | DEV_BOARD0_TCK_OUT | CLK_STATE_READY | 0 | | 157 | 356 | DEV_BOARD0_TRC_CLK_IN | CLK_STATE_READY | 0 | | 157 | 357 | DEV_BOARD0_UFS0_REF_CLK_IN | CLK_STATE_READY | 0 | | 157 | 358 | DEV_BOARD0_VOUT0_EXTPCLKIN_OUT | CLK_STATE_READY | 0 | | 157 | 359 | DEV_BOARD0_VOUT0_PCLK_IN | CLK_STATE_READY | 600000000 | | 157 | 360 | DEV_BOARD0_WKUP_I2C0_SCL_IN | CLK_STATE_READY | 0 | | 157 | 361 | DEV_BOARD0_WKUP_I2C0_SCL_OUT | CLK_STATE_READY | 0 | | 157 | 363 | DEV_BOARD0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 11 | 0 | DEV_CMPEVENT_INTRTR0_INTR_CLK | CLK_STATE_READY | 125000000 | | 241 | 0 | DEV_CODEC0_VPU_ACLK_CLK | CLK_STATE_READY | 600000000 | | 241 | 1 | DEV_CODEC0_VPU_BCLK_CLK | CLK_STATE_READY | 400000000 | | 241 | 2 | DEV_CODEC0_VPU_CCLK_CLK | CLK_STATE_READY | 600000000 | | 241 | 3 | DEV_CODEC0_VPU_PCLK_CLK | CLK_STATE_READY | 600000000 | | 242 | 0 | DEV_CODEC1_VPU_ACLK_CLK | CLK_STATE_READY | 600000000 | | 242 | 1 | DEV_CODEC1_VPU_BCLK_CLK | CLK_STATE_READY | 400000000 | | 242 | 2 | DEV_CODEC1_VPU_CCLK_CLK | CLK_STATE_READY | 600000000 | | 242 | 3 | DEV_CODEC1_VPU_PCLK_CLK | CLK_STATE_READY | 600000000 | | 30 | 3 | DEV_COMPUTE_CLUSTER0_C71SS0_C7X_CLK | CLK_STATE_READY | 1000000000 | | 30 | 4 | DEV_COMPUTE_CLUSTER0_C71SS0_C7X_DIVH_CLK4_OBSCLK_OUT_CLK | CLK_STATE_READY | 0 | | 31 | 0 | DEV_COMPUTE_CLUSTER0_C71SS0_CORE0_C7X_CLK | CLK_STATE_READY | 1000000000 | | 31 | 2 | DEV_COMPUTE_CLUSTER0_C71SS0_CORE0_PLL_CTRL_CLK_CLK | CLK_STATE_READY | 500000000 | | 33 | 3 | DEV_COMPUTE_CLUSTER0_C71SS1_C7X_CLK | CLK_STATE_READY | 1000000000 | | 34 | 0 | DEV_COMPUTE_CLUSTER0_C71SS1_CORE0_C7X_CLK | CLK_STATE_READY | 1000000000 | | 34 | 2 | DEV_COMPUTE_CLUSTER0_C71SS1_CORE0_PLL_CTRL_CLK_CLK | CLK_STATE_READY | 500000000 | | 37 | 3 | DEV_COMPUTE_CLUSTER0_C71SS2_C7X_CLK | CLK_STATE_READY | 1000000000 | | 38 | 0 | DEV_COMPUTE_CLUSTER0_C71SS2_CORE0_C7X_CLK | CLK_STATE_READY | 1000000000 | | 40 | 3 | DEV_COMPUTE_CLUSTER0_C71SS3_C7X_CLK | CLK_STATE_READY | 1000000000 | | 41 | 0 | DEV_COMPUTE_CLUSTER0_C71SS3_CORE0_C7X_CLK | CLK_STATE_READY | 1000000000 | | 45 | 1 | DEV_COMPUTE_CLUSTER0_CORE_CORE_PSIL_LEAF_CLK | CLK_STATE_READY | 500000000 | | 50 | 0 | DEV_COMPUTE_CLUSTER0_DEBUG_WRAP_0_CLK1_CLK_CLK | CLK_STATE_READY | 1000000000 | | 50 | 1 | DEV_COMPUTE_CLUSTER0_DEBUG_WRAP_0_CLK2_CLK_CLK | CLK_STATE_READY | 500000000 | | 58 | 0 | DEV_COMPUTE_CLUSTER0_GIC500SS_VCLK_CLK | CLK_STATE_READY | 500000000 | | 62 | 0 | DEV_CPSW1_CPPI_CLK_CLK | CLK_STATE_READY | 320000000 | | 62 | 1 | DEV_CPSW1_CPTS_GENF0 | CLK_STATE_READY | 0 | | 62 | 3 | DEV_CPSW1_CPTS_RFT_CLK | CLK_STATE_READY | 200000000 | | 62 | 4 | DEV_CPSW1_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK | CLK_STATE_READY | 250000000 | | 62 | 5 | DEV_CPSW1_CPTS_RFT_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK | CLK_STATE_READY | 200000000 | | 62 | 6 | DEV_CPSW1_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | 62 | 7 | DEV_CPSW1_CPTS_RFT_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | 62 | 8 | DEV_CPSW1_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 62 | 9 | DEV_CPSW1_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | 62 | 10 | DEV_CPSW1_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN0_TXMCLK | CLK_STATE_READY | 0 | | 62 | 11 | DEV_CPSW1_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN1_TXMCLK | CLK_STATE_READY | 0 | | 62 | 12 | DEV_CPSW1_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN2_TXMCLK | CLK_STATE_READY | 0 | | 62 | 13 | DEV_CPSW1_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN3_TXMCLK | CLK_STATE_READY | 0 | | 62 | 14 | DEV_CPSW1_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN0_TXMCLK | CLK_STATE_READY | 0 | | 62 | 15 | DEV_CPSW1_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN1_TXMCLK | CLK_STATE_READY | 0 | | 62 | 16 | DEV_CPSW1_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP1_LN2_TXMCLK | CLK_STATE_READY | 0 | | 62 | 17 | DEV_CPSW1_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP3_LN2_TXMCLK | CLK_STATE_READY | 0 | | 62 | 18 | DEV_CPSW1_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK | CLK_STATE_READY | 500000000 | | 62 | 19 | DEV_CPSW1_CPTS_RFT_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK | CLK_STATE_READY | 500000000 | | 62 | 20 | DEV_CPSW1_GMII1_MR_CLK | CLK_STATE_READY | 25000000 | | 62 | 21 | DEV_CPSW1_GMII1_MT_CLK | CLK_STATE_READY | 25000000 | | 62 | 22 | DEV_CPSW1_GMII_RFT_CLK | CLK_STATE_READY | 125000000 | | 62 | 23 | DEV_CPSW1_MDIO_MDCLK_O | CLK_STATE_READY | 0 | | 62 | 24 | DEV_CPSW1_RGMII1_RXC_I | CLK_STATE_READY | 0 | | 62 | 26 | DEV_CPSW1_RGMII1_TXC_O | CLK_STATE_READY | 0 | | 62 | 27 | DEV_CPSW1_RGMII_MHZ_250_CLK | CLK_STATE_READY | 250000000 | | 62 | 28 | DEV_CPSW1_RGMII_MHZ_50_CLK | CLK_STATE_READY | 50000000 | | 62 | 29 | DEV_CPSW1_RGMII_MHZ_5_CLK | CLK_STATE_READY | 5000000 | | 62 | 30 | DEV_CPSW1_RMII_MHZ_50_CLK | CLK_STATE_READY | 0 | | 64 | 0 | DEV_CPSW_9XUSS_J7AM0_CPPI_CLK_CLK | CLK_STATE_READY | 320000000 | | 64 | 1 | DEV_CPSW_9XUSS_J7AM0_CPTS_GENF0 | CLK_STATE_READY | 0 | | 64 | 3 | DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK | CLK_STATE_READY | 250000000 | | 64 | 4 | DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK | CLK_STATE_READY | 250000000 | | 64 | 5 | DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK | CLK_STATE_READY | 200000000 | | 64 | 6 | DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | 64 | 7 | DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | 64 | 8 | DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 64 | 9 | DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | 64 | 10 | DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN0_TXMCLK | CLK_STATE_READY | 0 | | 64 | 11 | DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN1_TXMCLK | CLK_STATE_READY | 0 | | 64 | 12 | DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN2_TXMCLK | CLK_STATE_READY | 0 | | 64 | 13 | DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN3_TXMCLK | CLK_STATE_READY | 0 | | 64 | 14 | DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN0_TXMCLK | CLK_STATE_READY | 0 | | 64 | 15 | DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN1_TXMCLK | CLK_STATE_READY | 0 | | 64 | 16 | DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP1_LN2_TXMCLK | CLK_STATE_READY | 0 | | 64 | 17 | DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP3_LN2_TXMCLK | CLK_STATE_READY | 0 | | 64 | 18 | DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK | CLK_STATE_READY | 500000000 | | 64 | 19 | DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK | CLK_STATE_READY | 500000000 | | 64 | 22 | DEV_CPSW_9XUSS_J7AM0_GMII1_MR_CLK | CLK_STATE_READY | 25000000 | | 64 | 23 | DEV_CPSW_9XUSS_J7AM0_GMII1_MT_CLK | CLK_STATE_READY | 25000000 | | 64 | 24 | DEV_CPSW_9XUSS_J7AM0_GMII2_MR_CLK | CLK_STATE_READY | 25000000 | | 64 | 25 | DEV_CPSW_9XUSS_J7AM0_GMII2_MT_CLK | CLK_STATE_READY | 25000000 | | 64 | 26 | DEV_CPSW_9XUSS_J7AM0_GMII3_MR_CLK | CLK_STATE_READY | 25000000 | | 64 | 27 | DEV_CPSW_9XUSS_J7AM0_GMII3_MT_CLK | CLK_STATE_READY | 25000000 | | 64 | 28 | DEV_CPSW_9XUSS_J7AM0_GMII4_MR_CLK | CLK_STATE_READY | 25000000 | | 64 | 29 | DEV_CPSW_9XUSS_J7AM0_GMII4_MT_CLK | CLK_STATE_READY | 25000000 | | 64 | 30 | DEV_CPSW_9XUSS_J7AM0_GMII5_MR_CLK | CLK_STATE_READY | 25000000 | | 64 | 31 | DEV_CPSW_9XUSS_J7AM0_GMII5_MT_CLK | CLK_STATE_READY | 25000000 | | 64 | 32 | DEV_CPSW_9XUSS_J7AM0_GMII6_MR_CLK | CLK_STATE_READY | 25000000 | | 64 | 33 | DEV_CPSW_9XUSS_J7AM0_GMII6_MT_CLK | CLK_STATE_READY | 25000000 | | 64 | 34 | DEV_CPSW_9XUSS_J7AM0_GMII7_MR_CLK | CLK_STATE_READY | 25000000 | | 64 | 35 | DEV_CPSW_9XUSS_J7AM0_GMII7_MT_CLK | CLK_STATE_READY | 25000000 | | 64 | 36 | DEV_CPSW_9XUSS_J7AM0_GMII8_MR_CLK | CLK_STATE_READY | 25000000 | | 64 | 37 | DEV_CPSW_9XUSS_J7AM0_GMII8_MT_CLK | CLK_STATE_READY | 25000000 | | 64 | 38 | DEV_CPSW_9XUSS_J7AM0_GMII_RFT_CLK | CLK_STATE_READY | 125000000 | | 64 | 39 | DEV_CPSW_9XUSS_J7AM0_MDIO_MDCLK_O | CLK_STATE_READY | 0 | | 64 | 56 | DEV_CPSW_9XUSS_J7AM0_RGMII_MHZ_250_CLK | CLK_STATE_READY | 250000000 | | 64 | 57 | DEV_CPSW_9XUSS_J7AM0_RGMII_MHZ_50_CLK | CLK_STATE_READY | 50000000 | | 64 | 58 | DEV_CPSW_9XUSS_J7AM0_RGMII_MHZ_5_CLK | CLK_STATE_READY | 5000000 | | 64 | 59 | DEV_CPSW_9XUSS_J7AM0_RMII_MHZ_50_CLK | CLK_STATE_READY | 0 | | 64 | 60 | DEV_CPSW_9XUSS_J7AM0_SERDES1_REFCLK | CLK_STATE_READY | 0 | | 64 | 61 | DEV_CPSW_9XUSS_J7AM0_SERDES1_RXCLK | CLK_STATE_READY | 0 | | 64 | 62 | DEV_CPSW_9XUSS_J7AM0_SERDES1_RXFCLK | CLK_STATE_READY | 0 | | 64 | 63 | DEV_CPSW_9XUSS_J7AM0_SERDES1_TXCLK | CLK_STATE_READY | 0 | | 64 | 64 | DEV_CPSW_9XUSS_J7AM0_SERDES1_TXFCLK | CLK_STATE_READY | 0 | | 64 | 65 | DEV_CPSW_9XUSS_J7AM0_SERDES1_TXMCLK | CLK_STATE_READY | 0 | | 64 | 66 | DEV_CPSW_9XUSS_J7AM0_SERDES2_REFCLK | CLK_STATE_READY | 0 | | 64 | 67 | DEV_CPSW_9XUSS_J7AM0_SERDES2_RXCLK | CLK_STATE_READY | 0 | | 64 | 68 | DEV_CPSW_9XUSS_J7AM0_SERDES2_RXFCLK | CLK_STATE_READY | 0 | | 64 | 69 | DEV_CPSW_9XUSS_J7AM0_SERDES2_TXCLK | CLK_STATE_READY | 0 | | 64 | 70 | DEV_CPSW_9XUSS_J7AM0_SERDES2_TXFCLK | CLK_STATE_READY | 0 | | 64 | 71 | DEV_CPSW_9XUSS_J7AM0_SERDES2_TXMCLK | CLK_STATE_READY | 0 | | 64 | 72 | DEV_CPSW_9XUSS_J7AM0_SERDES3_REFCLK | CLK_STATE_READY | 0 | | 64 | 73 | DEV_CPSW_9XUSS_J7AM0_SERDES3_RXCLK | CLK_STATE_READY | 0 | | 64 | 74 | DEV_CPSW_9XUSS_J7AM0_SERDES3_RXFCLK | CLK_STATE_READY | 0 | | 64 | 75 | DEV_CPSW_9XUSS_J7AM0_SERDES3_TXCLK | CLK_STATE_READY | 0 | | 64 | 76 | DEV_CPSW_9XUSS_J7AM0_SERDES3_TXFCLK | CLK_STATE_READY | 0 | | 64 | 77 | DEV_CPSW_9XUSS_J7AM0_SERDES3_TXMCLK | CLK_STATE_READY | 0 | | 64 | 78 | DEV_CPSW_9XUSS_J7AM0_SERDES4_REFCLK | CLK_STATE_READY | 0 | | 64 | 79 | DEV_CPSW_9XUSS_J7AM0_SERDES4_RXCLK | CLK_STATE_READY | 0 | | 64 | 80 | DEV_CPSW_9XUSS_J7AM0_SERDES4_RXFCLK | CLK_STATE_READY | 0 | | 64 | 81 | DEV_CPSW_9XUSS_J7AM0_SERDES4_TXCLK | CLK_STATE_READY | 0 | | 64 | 82 | DEV_CPSW_9XUSS_J7AM0_SERDES4_TXFCLK | CLK_STATE_READY | 0 | | 64 | 83 | DEV_CPSW_9XUSS_J7AM0_SERDES4_TXMCLK | CLK_STATE_READY | 0 | | 64 | 84 | DEV_CPSW_9XUSS_J7AM0_SERDES5_REFCLK | CLK_STATE_READY | 0 | | 64 | 85 | DEV_CPSW_9XUSS_J7AM0_SERDES5_RXCLK | CLK_STATE_READY | 0 | | 64 | 86 | DEV_CPSW_9XUSS_J7AM0_SERDES5_RXFCLK | CLK_STATE_READY | 0 | | 64 | 87 | DEV_CPSW_9XUSS_J7AM0_SERDES5_TXCLK | CLK_STATE_READY | 0 | | 64 | 88 | DEV_CPSW_9XUSS_J7AM0_SERDES5_TXFCLK | CLK_STATE_READY | 0 | | 64 | 89 | DEV_CPSW_9XUSS_J7AM0_SERDES5_TXMCLK | CLK_STATE_READY | 0 | | 64 | 90 | DEV_CPSW_9XUSS_J7AM0_SERDES6_REFCLK | CLK_STATE_READY | 0 | | 64 | 91 | DEV_CPSW_9XUSS_J7AM0_SERDES6_RXCLK | CLK_STATE_READY | 0 | | 64 | 92 | DEV_CPSW_9XUSS_J7AM0_SERDES6_RXFCLK | CLK_STATE_READY | 0 | | 64 | 93 | DEV_CPSW_9XUSS_J7AM0_SERDES6_TXCLK | CLK_STATE_READY | 0 | | 64 | 94 | DEV_CPSW_9XUSS_J7AM0_SERDES6_TXFCLK | CLK_STATE_READY | 0 | | 64 | 95 | DEV_CPSW_9XUSS_J7AM0_SERDES6_TXMCLK | CLK_STATE_READY | 0 | | 64 | 96 | DEV_CPSW_9XUSS_J7AM0_SERDES7_REFCLK | CLK_STATE_READY | 0 | | 64 | 97 | DEV_CPSW_9XUSS_J7AM0_SERDES7_RXCLK | CLK_STATE_READY | 0 | | 64 | 98 | DEV_CPSW_9XUSS_J7AM0_SERDES7_RXFCLK | CLK_STATE_READY | 0 | | 64 | 99 | DEV_CPSW_9XUSS_J7AM0_SERDES7_TXCLK | CLK_STATE_READY | 0 | | 64 | 100 | DEV_CPSW_9XUSS_J7AM0_SERDES7_TXFCLK | CLK_STATE_READY | 0 | | 64 | 101 | DEV_CPSW_9XUSS_J7AM0_SERDES7_TXMCLK | CLK_STATE_READY | 0 | | 64 | 102 | DEV_CPSW_9XUSS_J7AM0_SERDES8_REFCLK | CLK_STATE_READY | 0 | | 64 | 103 | DEV_CPSW_9XUSS_J7AM0_SERDES8_RXCLK | CLK_STATE_READY | 0 | | 64 | 104 | DEV_CPSW_9XUSS_J7AM0_SERDES8_RXFCLK | CLK_STATE_READY | 0 | | 64 | 105 | DEV_CPSW_9XUSS_J7AM0_SERDES8_TXCLK | CLK_STATE_READY | 0 | | 64 | 106 | DEV_CPSW_9XUSS_J7AM0_SERDES8_TXFCLK | CLK_STATE_READY | 0 | | 64 | 107 | DEV_CPSW_9XUSS_J7AM0_SERDES8_TXMCLK | CLK_STATE_READY | 0 | | 70 | 0 | DEV_CPT2_AGGR0_VCLK_CLK | CLK_STATE_READY | 250000000 | | 65 | 0 | DEV_CPT2_AGGR1_VCLK_CLK | CLK_STATE_READY | 250000000 | | 67 | 0 | DEV_CPT2_AGGR2_VCLK_CLK | CLK_STATE_READY | 250000000 | | 69 | 0 | DEV_CPT2_AGGR3_VCLK_CLK | CLK_STATE_READY | 250000000 | | 68 | 0 | DEV_CPT2_AGGR4_VCLK_CLK | CLK_STATE_READY | 250000000 | | 66 | 0 | DEV_CPT2_AGGR5_VCLK_CLK | CLK_STATE_READY | 250000000 | | 189 | 0 | DEV_CSI_PSILSS0_MAIN_CLK | CLK_STATE_READY | 125000000 | | 72 | 0 | DEV_CSI_RX_IF0_MAIN_CLK_CLK | CLK_STATE_READY | 500000000 | | 72 | 1 | DEV_CSI_RX_IF0_PPI_D_RX_ULPS_ESC | CLK_STATE_READY | 0 | | 72 | 2 | DEV_CSI_RX_IF0_PPI_RX_BYTE_CLK | CLK_STATE_READY | 0 | | 72 | 3 | DEV_CSI_RX_IF0_VBUS_CLK_CLK | CLK_STATE_READY | 250000000 | | 72 | 4 | DEV_CSI_RX_IF0_VP_CLK_CLK | CLK_STATE_READY | 720000000 | | 73 | 0 | DEV_CSI_RX_IF1_MAIN_CLK_CLK | CLK_STATE_READY | 500000000 | | 73 | 1 | DEV_CSI_RX_IF1_PPI_D_RX_ULPS_ESC | CLK_STATE_READY | 0 | | 73 | 2 | DEV_CSI_RX_IF1_PPI_RX_BYTE_CLK | CLK_STATE_READY | 0 | | 73 | 3 | DEV_CSI_RX_IF1_VBUS_CLK_CLK | CLK_STATE_READY | 250000000 | | 73 | 4 | DEV_CSI_RX_IF1_VP_CLK_CLK | CLK_STATE_READY | 720000000 | | 74 | 0 | DEV_CSI_RX_IF2_MAIN_CLK_CLK | CLK_STATE_READY | 500000000 | | 74 | 1 | DEV_CSI_RX_IF2_PPI_D_RX_ULPS_ESC | CLK_STATE_READY | 0 | | 74 | 2 | DEV_CSI_RX_IF2_PPI_RX_BYTE_CLK | CLK_STATE_READY | 0 | | 74 | 3 | DEV_CSI_RX_IF2_VBUS_CLK_CLK | CLK_STATE_READY | 250000000 | | 74 | 4 | DEV_CSI_RX_IF2_VP_CLK_CLK | CLK_STATE_READY | 720000000 | | 75 | 2 | DEV_CSI_TX_IF_V2_0_DPHY_TXBYTECLKHS_CL_CLK | CLK_STATE_READY | 0 | | 75 | 3 | DEV_CSI_TX_IF_V2_0_ESC_CLK_CLK | CLK_STATE_READY | 20000000 | | 75 | 4 | DEV_CSI_TX_IF_V2_0_MAIN_CLK_CLK | CLK_STATE_READY | 500000000 | | 75 | 5 | DEV_CSI_TX_IF_V2_0_VBUS_CLK_CLK | CLK_STATE_READY | 250000000 | | 76 | 2 | DEV_CSI_TX_IF_V2_1_DPHY_TXBYTECLKHS_CL_CLK | CLK_STATE_READY | 0 | | 76 | 3 | DEV_CSI_TX_IF_V2_1_ESC_CLK_CLK | CLK_STATE_READY | 20000000 | | 76 | 4 | DEV_CSI_TX_IF_V2_1_MAIN_CLK_CLK | CLK_STATE_READY | 500000000 | | 76 | 5 | DEV_CSI_TX_IF_V2_1_VBUS_CLK_CLK | CLK_STATE_READY | 250000000 | | 78 | 0 | DEV_DCC0_DCC_CLKSRC0_CLK | CLK_STATE_READY | 250000000 | | 78 | 1 | DEV_DCC0_DCC_CLKSRC1_CLK | CLK_STATE_READY | 200000000 | | 78 | 2 | DEV_DCC0_DCC_CLKSRC2_CLK | CLK_STATE_READY | 133333333 | | 78 | 3 | DEV_DCC0_DCC_CLKSRC3_CLK | CLK_STATE_READY | 80000000 | | 78 | 4 | DEV_DCC0_DCC_CLKSRC4_CLK | CLK_STATE_READY | 24000000 | | 78 | 5 | DEV_DCC0_DCC_CLKSRC5_CLK | CLK_STATE_READY | 0 | | 78 | 6 | DEV_DCC0_DCC_CLKSRC6_CLK | CLK_STATE_READY | 500000000 | | 78 | 7 | DEV_DCC0_DCC_CLKSRC7_CLK | CLK_STATE_READY | 0 | | 78 | 8 | DEV_DCC0_DCC_INPUT00_CLK | CLK_STATE_READY | 24000000 | | 78 | 9 | DEV_DCC0_DCC_INPUT01_CLK | CLK_STATE_READY | 0 | | 78 | 10 | DEV_DCC0_DCC_INPUT02_CLK | CLK_STATE_READY | 12500000 | | 78 | 11 | DEV_DCC0_DCC_INPUT10_CLK | CLK_STATE_READY | 250000000 | | 78 | 12 | DEV_DCC0_VBUS_CLK | CLK_STATE_READY | 125000000 | | 79 | 0 | DEV_DCC1_DCC_CLKSRC0_CLK | CLK_STATE_READY | 50000000 | | 79 | 1 | DEV_DCC1_DCC_CLKSRC1_CLK | CLK_STATE_READY | 200000000 | | 79 | 2 | DEV_DCC1_DCC_CLKSRC2_CLK | CLK_STATE_READY | 200000000 | | 79 | 3 | DEV_DCC1_DCC_CLKSRC3_CLK | CLK_STATE_READY | 192000000 | | 79 | 4 | DEV_DCC1_DCC_CLKSRC4_CLK | CLK_STATE_READY | 320000000 | | 79 | 5 | DEV_DCC1_DCC_CLKSRC5_CLK | CLK_STATE_READY | 192000000 | | 79 | 6 | DEV_DCC1_DCC_CLKSRC6_CLK | CLK_STATE_READY | 192000000 | | 79 | 7 | DEV_DCC1_DCC_CLKSRC7_CLK | CLK_STATE_READY | 19200000 | | 79 | 8 | DEV_DCC1_DCC_INPUT00_CLK | CLK_STATE_READY | 24000000 | | 79 | 9 | DEV_DCC1_DCC_INPUT01_CLK | CLK_STATE_READY | 0 | | 79 | 10 | DEV_DCC1_DCC_INPUT02_CLK | CLK_STATE_READY | 12500000 | | 79 | 11 | DEV_DCC1_DCC_INPUT10_CLK | CLK_STATE_READY | 125000000 | | 79 | 12 | DEV_DCC1_VBUS_CLK | CLK_STATE_READY | 125000000 | | 80 | 0 | DEV_DCC2_DCC_CLKSRC0_CLK | CLK_STATE_READY | 24000000 | | 80 | 1 | DEV_DCC2_DCC_CLKSRC1_CLK | CLK_STATE_READY | 20000000 | | 80 | 3 | DEV_DCC2_DCC_CLKSRC3_CLK | CLK_STATE_READY | 100000000 | | 80 | 4 | DEV_DCC2_DCC_CLKSRC4_CLK | CLK_STATE_READY | 225000000 | | 80 | 5 | DEV_DCC2_DCC_CLKSRC5_CLK | CLK_STATE_READY | 300000000 | | 80 | 6 | DEV_DCC2_DCC_CLKSRC6_CLK | CLK_STATE_READY | 200000000 | | 80 | 7 | DEV_DCC2_DCC_CLKSRC7_CLK | CLK_STATE_READY | 250000000 | | 80 | 8 | DEV_DCC2_DCC_INPUT00_CLK | CLK_STATE_READY | 24000000 | | 80 | 9 | DEV_DCC2_DCC_INPUT01_CLK | CLK_STATE_READY | 0 | | 80 | 10 | DEV_DCC2_DCC_INPUT02_CLK | CLK_STATE_READY | 12500000 | | 80 | 11 | DEV_DCC2_DCC_INPUT10_CLK | CLK_STATE_READY | 125000000 | | 80 | 12 | DEV_DCC2_VBUS_CLK | CLK_STATE_READY | 125000000 | | 81 | 0 | DEV_DCC3_DCC_CLKSRC0_CLK | CLK_STATE_READY | 196608000 | | 81 | 1 | DEV_DCC3_DCC_CLKSRC1_CLK | CLK_STATE_READY | 200000000 | | 81 | 2 | DEV_DCC3_DCC_CLKSRC2_CLK | CLK_STATE_READY | 300000000 | | 81 | 3 | DEV_DCC3_DCC_CLKSRC3_CLK | CLK_STATE_READY | 500000000 | | 81 | 5 | DEV_DCC3_DCC_CLKSRC5_CLK | CLK_STATE_READY | 200000000 | | 81 | 6 | DEV_DCC3_DCC_CLKSRC6_CLK | CLK_STATE_READY | 250000000 | | 81 | 7 | DEV_DCC3_DCC_CLKSRC7_CLK | CLK_STATE_READY | 500000000 | | 81 | 8 | DEV_DCC3_DCC_INPUT00_CLK | CLK_STATE_READY | 24000000 | | 81 | 9 | DEV_DCC3_DCC_INPUT01_CLK | CLK_STATE_READY | 0 | | 81 | 10 | DEV_DCC3_DCC_INPUT02_CLK | CLK_STATE_READY | 12500000 | | 81 | 11 | DEV_DCC3_DCC_INPUT10_CLK | CLK_STATE_READY | 125000000 | | 81 | 12 | DEV_DCC3_VBUS_CLK | CLK_STATE_READY | 125000000 | | 82 | 0 | DEV_DCC4_DCC_CLKSRC0_CLK | CLK_STATE_READY | 200000000 | | 82 | 1 | DEV_DCC4_DCC_CLKSRC1_CLK | CLK_STATE_READY | 266625000 | | 82 | 2 | DEV_DCC4_DCC_CLKSRC2_CLK | CLK_STATE_READY | 266625000 | | 82 | 3 | DEV_DCC4_DCC_CLKSRC3_CLK | CLK_STATE_READY | 266625000 | | 82 | 4 | DEV_DCC4_DCC_CLKSRC4_CLK | CLK_STATE_READY | 250000000 | | 82 | 5 | DEV_DCC4_DCC_CLKSRC5_CLK | CLK_STATE_READY | 250000000 | | 82 | 6 | DEV_DCC4_DCC_CLKSRC6_CLK | CLK_STATE_READY | 266625000 | | 82 | 7 | DEV_DCC4_DCC_CLKSRC7_CLK | CLK_STATE_READY | 297000000 | | 82 | 8 | DEV_DCC4_DCC_INPUT00_CLK | CLK_STATE_READY | 24000000 | | 82 | 9 | DEV_DCC4_DCC_INPUT01_CLK | CLK_STATE_READY | 0 | | 82 | 10 | DEV_DCC4_DCC_INPUT02_CLK | CLK_STATE_READY | 12500000 | | 82 | 11 | DEV_DCC4_DCC_INPUT10_CLK | CLK_STATE_READY | 250000000 | | 82 | 12 | DEV_DCC4_VBUS_CLK | CLK_STATE_READY | 125000000 | | 83 | 1 | DEV_DCC5_DCC_CLKSRC1_CLK | CLK_STATE_READY | 300000000 | | 83 | 2 | DEV_DCC5_DCC_CLKSRC2_CLK | CLK_STATE_READY | 297000000 | | 83 | 3 | DEV_DCC5_DCC_CLKSRC3_CLK | CLK_STATE_READY | 240000000 | | 83 | 4 | DEV_DCC5_DCC_CLKSRC4_CLK | CLK_STATE_READY | 360000000 | | 83 | 6 | DEV_DCC5_DCC_CLKSRC6_CLK | CLK_STATE_READY | 0 | | 83 | 7 | DEV_DCC5_DCC_CLKSRC7_CLK | CLK_STATE_READY | 0 | | 83 | 8 | DEV_DCC5_DCC_INPUT00_CLK | CLK_STATE_READY | 24000000 | | 83 | 9 | DEV_DCC5_DCC_INPUT01_CLK | CLK_STATE_READY | 0 | | 83 | 10 | DEV_DCC5_DCC_INPUT02_CLK | CLK_STATE_READY | 12500000 | | 83 | 11 | DEV_DCC5_DCC_INPUT10_CLK | CLK_STATE_READY | 500000000 | | 83 | 12 | DEV_DCC5_VBUS_CLK | CLK_STATE_READY | 125000000 | | 84 | 0 | DEV_DCC6_DCC_CLKSRC0_CLK | CLK_STATE_READY | 0 | | 84 | 1 | DEV_DCC6_DCC_CLKSRC1_CLK | CLK_STATE_READY | 0 | | 84 | 2 | DEV_DCC6_DCC_CLKSRC2_CLK | CLK_STATE_READY | 0 | | 84 | 3 | DEV_DCC6_DCC_CLKSRC3_CLK | CLK_STATE_READY | 0 | | 84 | 4 | DEV_DCC6_DCC_CLKSRC4_CLK | CLK_STATE_READY | 0 | | 84 | 5 | DEV_DCC6_DCC_CLKSRC5_CLK | CLK_STATE_READY | 0 | | 84 | 6 | DEV_DCC6_DCC_CLKSRC6_CLK | CLK_STATE_READY | 0 | | 84 | 7 | DEV_DCC6_DCC_CLKSRC7_CLK | CLK_STATE_READY | 0 | | 84 | 8 | DEV_DCC6_DCC_INPUT00_CLK | CLK_STATE_READY | 24000000 | | 84 | 9 | DEV_DCC6_DCC_INPUT01_CLK | CLK_STATE_READY | 0 | | 84 | 10 | DEV_DCC6_DCC_INPUT02_CLK | CLK_STATE_READY | 12500000 | | 84 | 11 | DEV_DCC6_DCC_INPUT10_CLK | CLK_STATE_READY | 125000000 | | 84 | 12 | DEV_DCC6_VBUS_CLK | CLK_STATE_READY | 125000000 | | 85 | 0 | DEV_DCC7_DCC_CLKSRC0_CLK | CLK_STATE_READY | 0 | | 85 | 1 | DEV_DCC7_DCC_CLKSRC1_CLK | CLK_STATE_READY | 0 | | 85 | 2 | DEV_DCC7_DCC_CLKSRC2_CLK | CLK_STATE_READY | 250000000 | | 85 | 5 | DEV_DCC7_DCC_CLKSRC5_CLK | CLK_STATE_READY | 0 | | 85 | 6 | DEV_DCC7_DCC_CLKSRC6_CLK | CLK_STATE_READY | 120000000 | | 85 | 7 | DEV_DCC7_DCC_CLKSRC7_CLK | CLK_STATE_READY | 0 | | 85 | 8 | DEV_DCC7_DCC_INPUT00_CLK | CLK_STATE_READY | 24000000 | | 85 | 9 | DEV_DCC7_DCC_INPUT01_CLK | CLK_STATE_READY | 0 | | 85 | 10 | DEV_DCC7_DCC_INPUT02_CLK | CLK_STATE_READY | 12500000 | | 85 | 11 | DEV_DCC7_DCC_INPUT10_CLK | CLK_STATE_READY | 250000000 | | 85 | 12 | DEV_DCC7_VBUS_CLK | CLK_STATE_READY | 125000000 | | 86 | 0 | DEV_DCC8_DCC_CLKSRC0_CLK | CLK_STATE_READY | 32000 | | 86 | 1 | DEV_DCC8_DCC_CLKSRC1_CLK | CLK_STATE_READY | 32768 | | 86 | 2 | DEV_DCC8_DCC_CLKSRC2_CLK | CLK_STATE_READY | 0 | | 86 | 3 | DEV_DCC8_DCC_CLKSRC3_CLK | CLK_STATE_READY | 0 | | 86 | 4 | DEV_DCC8_DCC_CLKSRC4_CLK | CLK_STATE_READY | 0 | | 86 | 5 | DEV_DCC8_DCC_CLKSRC5_CLK | CLK_STATE_READY | 0 | | 86 | 6 | DEV_DCC8_DCC_CLKSRC6_CLK | CLK_STATE_READY | 250000000 | | 86 | 7 | DEV_DCC8_DCC_CLKSRC7_CLK | CLK_STATE_READY | 192307692 | | 86 | 8 | DEV_DCC8_DCC_INPUT00_CLK | CLK_STATE_READY | 24000000 | | 86 | 9 | DEV_DCC8_DCC_INPUT01_CLK | CLK_STATE_READY | 0 | | 86 | 10 | DEV_DCC8_DCC_INPUT02_CLK | CLK_STATE_READY | 12500000 | | 86 | 11 | DEV_DCC8_DCC_INPUT10_CLK | CLK_STATE_READY | 250000000 | | 86 | 12 | DEV_DCC8_VBUS_CLK | CLK_STATE_READY | 125000000 | | 87 | 0 | DEV_DCC9_DCC_CLKSRC0_CLK | CLK_STATE_READY | 250000000 | | 87 | 1 | DEV_DCC9_DCC_CLKSRC1_CLK | CLK_STATE_READY | 156250000 | | 87 | 2 | DEV_DCC9_DCC_CLKSRC2_CLK | CLK_STATE_READY | 0 | | 87 | 3 | DEV_DCC9_DCC_CLKSRC3_CLK | CLK_STATE_READY | 0 | | 87 | 4 | DEV_DCC9_DCC_CLKSRC4_CLK | CLK_STATE_READY | 0 | | 87 | 5 | DEV_DCC9_DCC_CLKSRC5_CLK | CLK_STATE_READY | 294912000 | | 87 | 6 | DEV_DCC9_DCC_CLKSRC6_CLK | CLK_STATE_READY | 196608000 | | 87 | 8 | DEV_DCC9_DCC_INPUT00_CLK | CLK_STATE_READY | 24000000 | | 87 | 9 | DEV_DCC9_DCC_INPUT01_CLK | CLK_STATE_READY | 0 | | 87 | 10 | DEV_DCC9_DCC_INPUT02_CLK | CLK_STATE_READY | 12500000 | | 87 | 11 | DEV_DCC9_DCC_INPUT10_CLK | CLK_STATE_READY | 250000000 | | 87 | 12 | DEV_DCC9_VBUS_CLK | CLK_STATE_READY | 125000000 | | 191 | 0 | DEV_DDR0_DDRSS_CFG_CLK | CLK_STATE_READY | 125000000 | | 191 | 1 | DEV_DDR0_DDRSS_DDR_PLL_CLK | CLK_STATE_READY | 1066500000 | | 191 | 4 | DEV_DDR0_DDRSS_VBUS_CLK | CLK_STATE_READY | 250000000 | | 191 | 5 | DEV_DDR0_PLL_CTRL_CLK | CLK_STATE_READY | 500000000 | | 192 | 0 | DEV_DDR1_DDRSS_CFG_CLK | CLK_STATE_READY | 125000000 | | 192 | 1 | DEV_DDR1_DDRSS_DDR_PLL_CLK | CLK_STATE_READY | 1066500000 | | 192 | 4 | DEV_DDR1_DDRSS_VBUS_CLK | CLK_STATE_READY | 250000000 | | 192 | 5 | DEV_DDR1_PLL_CTRL_CLK | CLK_STATE_READY | 500000000 | | 193 | 0 | DEV_DDR2_DDRSS_CFG_CLK | CLK_STATE_READY | 125000000 | | 193 | 1 | DEV_DDR2_DDRSS_DDR_PLL_CLK | CLK_STATE_READY | 1066500000 | | 193 | 4 | DEV_DDR2_DDRSS_VBUS_CLK | CLK_STATE_READY | 250000000 | | 193 | 5 | DEV_DDR2_PLL_CTRL_CLK | CLK_STATE_READY | 500000000 | | 194 | 0 | DEV_DDR3_DDRSS_CFG_CLK | CLK_STATE_READY | 125000000 | | 194 | 1 | DEV_DDR3_DDRSS_DDR_PLL_CLK | CLK_STATE_READY | 1066500000 | | 194 | 4 | DEV_DDR3_DDRSS_VBUS_CLK | CLK_STATE_READY | 250000000 | | 194 | 5 | DEV_DDR3_PLL_CTRL_CLK | CLK_STATE_READY | 500000000 | | 91 | 0 | DEV_DEBUGSS_WRAP0_ATB_CLK | CLK_STATE_READY | 250000000 | | 91 | 1 | DEV_DEBUGSS_WRAP0_CORE_CLK | CLK_STATE_READY | 125000000 | | 91 | 2 | DEV_DEBUGSS_WRAP0_CSTPIU_TRACECLK | CLK_STATE_READY | 0 | | 91 | 20 | DEV_DEBUGSS_WRAP0_JTAG_TCK | CLK_STATE_READY | 0 | | 91 | 22 | DEV_DEBUGSS_WRAP0_TREXPT_CLK | CLK_STATE_READY | 300000000 | | 190 | 0 | DEV_DEBUGSUSPENDRTR0_INTR_CLK | CLK_STATE_READY | 125000000 | | 92 | 0 | DEV_DMPAC0_CLK | CLK_STATE_READY | 480000000 | | 96 | 0 | DEV_DMPAC0_SDE_0_CLK | CLK_STATE_READY | 480000000 | | 95 | 0 | DEV_DMPAC0_UTC_0_PSIL_LEAF_CLK | CLK_STATE_READY | 480000000 | | 195 | 0 | DEV_DMPAC_VPAC_PSILSS0_MAIN_CLK | CLK_STATE_READY | 250000000 | | 212 | 2 | DEV_DPHY_RX0_IO_RX_CL_L_M | CLK_STATE_READY | 0 | | 212 | 3 | DEV_DPHY_RX0_IO_RX_CL_L_P | CLK_STATE_READY | 0 | | 212 | 4 | DEV_DPHY_RX0_JTAG_TCK | CLK_STATE_READY | 0 | | 212 | 5 | DEV_DPHY_RX0_MAIN_CLK_CLK | CLK_STATE_READY | 125000000 | | 212 | 6 | DEV_DPHY_RX0_PPI_D_RX_ULPS_ESC | CLK_STATE_READY | 0 | | 212 | 7 | DEV_DPHY_RX0_PPI_RX_BYTE_CLK | CLK_STATE_READY | 0 | | 213 | 2 | DEV_DPHY_RX1_IO_RX_CL_L_M | CLK_STATE_READY | 0 | | 213 | 3 | DEV_DPHY_RX1_IO_RX_CL_L_P | CLK_STATE_READY | 0 | | 213 | 4 | DEV_DPHY_RX1_JTAG_TCK | CLK_STATE_READY | 0 | | 213 | 5 | DEV_DPHY_RX1_MAIN_CLK_CLK | CLK_STATE_READY | 125000000 | | 213 | 6 | DEV_DPHY_RX1_PPI_D_RX_ULPS_ESC | CLK_STATE_READY | 0 | | 213 | 7 | DEV_DPHY_RX1_PPI_RX_BYTE_CLK | CLK_STATE_READY | 0 | | 214 | 2 | DEV_DPHY_RX2_IO_RX_CL_L_M | CLK_STATE_READY | 0 | | 214 | 3 | DEV_DPHY_RX2_IO_RX_CL_L_P | CLK_STATE_READY | 0 | | 214 | 4 | DEV_DPHY_RX2_JTAG_TCK | CLK_STATE_READY | 0 | | 214 | 5 | DEV_DPHY_RX2_MAIN_CLK_CLK | CLK_STATE_READY | 125000000 | | 214 | 6 | DEV_DPHY_RX2_PPI_D_RX_ULPS_ESC | CLK_STATE_READY | 0 | | 214 | 7 | DEV_DPHY_RX2_PPI_RX_BYTE_CLK | CLK_STATE_READY | 0 | | 402 | 0 | DEV_DPHY_TX0_CK_M | CLK_STATE_READY | 0 | | 402 | 1 | DEV_DPHY_TX0_CK_P | CLK_STATE_READY | 0 | | 402 | 2 | DEV_DPHY_TX0_CLK | CLK_STATE_READY | 125000000 | | 402 | 3 | DEV_DPHY_TX0_DPHY_REF_CLK | CLK_STATE_READY | 24000000 | | 402 | 4 | DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 24000000 | | 402 | 5 | DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 402 | 6 | DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK | CLK_STATE_READY | 156250000 | | 402 | 7 | DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK | CLK_STATE_READY | 100000000 | | 402 | 8 | DEV_DPHY_TX0_IP1_PPI_M_RXCLKESC_CLK | CLK_STATE_READY | 0 | | 402 | 9 | DEV_DPHY_TX0_IP1_PPI_M_TXCLKESC_CLK | CLK_STATE_READY | 20000000 | | 402 | 10 | DEV_DPHY_TX0_IP1_PPI_TXBYTECLKHS_CL_CLK | CLK_STATE_READY | 0 | | 402 | 12 | DEV_DPHY_TX0_IP2_PPI_M_TXCLKESC_CLK | CLK_STATE_READY | 20000000 | | 402 | 13 | DEV_DPHY_TX0_IP2_PPI_TXBYTECLKHS_CL_CLK | CLK_STATE_READY | 0 | | 402 | 20 | DEV_DPHY_TX0_PSM_CLK | CLK_STATE_READY | 20000000 | | 402 | 24 | DEV_DPHY_TX0_TAP_TCK | CLK_STATE_READY | 0 | | 403 | 0 | DEV_DPHY_TX1_CK_M | CLK_STATE_READY | 0 | | 403 | 1 | DEV_DPHY_TX1_CK_P | CLK_STATE_READY | 0 | | 403 | 2 | DEV_DPHY_TX1_CLK | CLK_STATE_READY | 125000000 | | 403 | 3 | DEV_DPHY_TX1_DPHY_REF_CLK | CLK_STATE_READY | 24000000 | | 403 | 4 | DEV_DPHY_TX1_DPHY_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 24000000 | | 403 | 5 | DEV_DPHY_TX1_DPHY_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 403 | 6 | DEV_DPHY_TX1_DPHY_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK | CLK_STATE_READY | 156250000 | | 403 | 7 | DEV_DPHY_TX1_DPHY_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK | CLK_STATE_READY | 100000000 | | 403 | 8 | DEV_DPHY_TX1_IP1_PPI_M_RXCLKESC_CLK | CLK_STATE_READY | 0 | | 403 | 9 | DEV_DPHY_TX1_IP1_PPI_M_TXCLKESC_CLK | CLK_STATE_READY | 20000000 | | 403 | 10 | DEV_DPHY_TX1_IP1_PPI_TXBYTECLKHS_CL_CLK | CLK_STATE_READY | 0 | | 403 | 13 | DEV_DPHY_TX1_IP2_PPI_TXBYTECLKHS_CL_CLK | CLK_STATE_READY | 0 | | 403 | 20 | DEV_DPHY_TX1_PSM_CLK | CLK_STATE_READY | 20000000 | | 403 | 24 | DEV_DPHY_TX1_TAP_TCK | CLK_STATE_READY | 0 | | 218 | 0 | DEV_DSS0_DSS_FUNC_CLK | CLK_STATE_READY | 600000000 | | 218 | 1 | DEV_DSS0_DSS_INST0_DPI_0_IN_CLK | CLK_STATE_READY | 297000000 | | 218 | 2 | DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK | CLK_STATE_READY | 594000000 | | 218 | 3 | DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK | CLK_STATE_READY | 594000000 | | 218 | 4 | DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK_PARENT_DPI_1_PCLK_SEL_OUT0 | CLK_STATE_READY | 600000000 | | 218 | 5 | DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK | CLK_STATE_READY | 600000000 | | 218 | 6 | DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT0_CLK | CLK_STATE_READY | 594000000 | | 218 | 7 | DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0 | CLK_STATE_READY | 600000000 | | 218 | 8 | DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0_DUP0 | CLK_STATE_READY | 600000000 | | 218 | 9 | DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK | CLK_STATE_READY | 594000000 | | 218 | 10 | DEV_DSS0_DSS_INST0_DPI_2_IN_CLK | CLK_STATE_READY | 297000000 | | 218 | 11 | DEV_DSS0_DSS_INST0_DPI_2_IN_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK | CLK_STATE_READY | 297000000 | | 218 | 12 | DEV_DSS0_DSS_INST0_DPI_2_IN_CLK_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT0_CLK | CLK_STATE_READY | 297000000 | | 218 | 13 | DEV_DSS0_DSS_INST0_DPI_2_IN_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0 | CLK_STATE_READY | 300000000 | | 218 | 14 | DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK | CLK_STATE_READY | 594000000 | | 218 | 15 | DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK | CLK_STATE_READY | 594000000 | | 218 | 16 | DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT0_CLK | CLK_STATE_READY | 594000000 | | 218 | 17 | DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0 | CLK_STATE_READY | 600000000 | | 218 | 18 | DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK | CLK_STATE_READY | 600000000 | | 218 | 19 | DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT1_CLK | CLK_STATE_READY | 594000000 | | 218 | 20 | DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT1_CLK | CLK_STATE_READY | 594000000 | | 218 | 21 | DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT1_CLK_DUP0 | CLK_STATE_READY | 594000000 | | 218 | 22 | DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0 | CLK_STATE_READY | 600000000 | | 218 | 23 | DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0_DUP0 | CLK_STATE_READY | 600000000 | | 218 | 24 | DEV_DSS0_DSS_INST0_PARA_1_OUT_CLK | CLK_STATE_READY | 0 | | 218 | 25 | DEV_DSS0_DSS_INST0_PARA_3_OUT_CLK | CLK_STATE_READY | 0 | | 218 | 26 | DEV_DSS0_DSS_INST0_DPI_0_OUT_CLK | CLK_STATE_READY | 0 | | 218 | 27 | DEV_DSS0_DSS_INST0_DPI_1_OUT_CLK | CLK_STATE_READY | 0 | | 218 | 28 | DEV_DSS0_DSS_INST0_DPI_2_OUT_CLK | CLK_STATE_READY | 0 | | 218 | 29 | DEV_DSS0_DSS_INST0_DPI_3_OUT_CLK | CLK_STATE_READY | 0 | | 218 | 30 | DEV_DSS0_DSS_INST0_DPI_0_OUT_2X_CLK | CLK_STATE_READY | 0 | | 215 | 0 | DEV_DSS_DSI0_DPHY_0_RX_ESC_CLK | CLK_STATE_READY | 0 | | 215 | 1 | DEV_DSS_DSI0_DPHY_0_TX_ESC_CLK | CLK_STATE_READY | 20000000 | | 215 | 2 | DEV_DSS_DSI0_DPI_0_CLK | CLK_STATE_READY | 0 | | 215 | 3 | DEV_DSS_DSI0_PLL_CTRL_CLK | CLK_STATE_READY | 500000000 | | 215 | 4 | DEV_DSS_DSI0_PPI_0_TXBYTECLKHS_CL_CLK | CLK_STATE_READY | 0 | | 215 | 5 | DEV_DSS_DSI0_SYS_CLK | CLK_STATE_READY | 250000000 | | 216 | 0 | DEV_DSS_DSI1_DPHY_0_RX_ESC_CLK | CLK_STATE_READY | 0 | | 216 | 1 | DEV_DSS_DSI1_DPHY_0_TX_ESC_CLK | CLK_STATE_READY | 20000000 | | 216 | 2 | DEV_DSS_DSI1_DPI_0_CLK | CLK_STATE_READY | 0 | | 216 | 3 | DEV_DSS_DSI1_PLL_CTRL_CLK | CLK_STATE_READY | 500000000 | | 216 | 4 | DEV_DSS_DSI1_PPI_0_TXBYTECLKHS_CL_CLK | CLK_STATE_READY | 0 | | 216 | 5 | DEV_DSS_DSI1_SYS_CLK | CLK_STATE_READY | 250000000 | | 217 | 0 | DEV_DSS_EDP0_AIF_I2S_CLK | CLK_STATE_READY | 0 | | 217 | 6 | DEV_DSS_EDP0_DPI_2_2X_CLK | CLK_STATE_READY | 0 | | 217 | 7 | DEV_DSS_EDP0_DPI_2_CLK | CLK_STATE_READY | 0 | | 217 | 8 | DEV_DSS_EDP0_DPI_3_CLK | CLK_STATE_READY | 0 | | 217 | 9 | DEV_DSS_EDP0_DPI_4_CLK | CLK_STATE_READY | 0 | | 217 | 10 | DEV_DSS_EDP0_DPI_5_CLK | CLK_STATE_READY | 0 | | 217 | 11 | DEV_DSS_EDP0_DPTX_MOD_CLK | CLK_STATE_READY | 125000000 | | 217 | 12 | DEV_DSS_EDP0_PHY_LN0_REFCLK | CLK_STATE_READY | 0 | | 217 | 13 | DEV_DSS_EDP0_PHY_LN0_RXCLK | CLK_STATE_READY | 0 | | 217 | 14 | DEV_DSS_EDP0_PHY_LN0_RXFCLK | CLK_STATE_READY | 0 | | 217 | 15 | DEV_DSS_EDP0_PHY_LN0_TXCLK | CLK_STATE_READY | 0 | | 217 | 16 | DEV_DSS_EDP0_PHY_LN0_TXFCLK | CLK_STATE_READY | 0 | | 217 | 17 | DEV_DSS_EDP0_PHY_LN0_TXMCLK | CLK_STATE_READY | 0 | | 217 | 18 | DEV_DSS_EDP0_PHY_LN1_REFCLK | CLK_STATE_READY | 0 | | 217 | 19 | DEV_DSS_EDP0_PHY_LN1_RXCLK | CLK_STATE_READY | 0 | | 217 | 20 | DEV_DSS_EDP0_PHY_LN1_RXFCLK | CLK_STATE_READY | 0 | | 217 | 21 | DEV_DSS_EDP0_PHY_LN1_TXCLK | CLK_STATE_READY | 0 | | 217 | 22 | DEV_DSS_EDP0_PHY_LN1_TXFCLK | CLK_STATE_READY | 0 | | 217 | 23 | DEV_DSS_EDP0_PHY_LN1_TXMCLK | CLK_STATE_READY | 0 | | 217 | 24 | DEV_DSS_EDP0_PHY_LN2_REFCLK | CLK_STATE_READY | 0 | | 217 | 25 | DEV_DSS_EDP0_PHY_LN2_RXCLK | CLK_STATE_READY | 0 | | 217 | 26 | DEV_DSS_EDP0_PHY_LN2_RXFCLK | CLK_STATE_READY | 0 | | 217 | 27 | DEV_DSS_EDP0_PHY_LN2_TXCLK | CLK_STATE_READY | 0 | | 217 | 28 | DEV_DSS_EDP0_PHY_LN2_TXFCLK | CLK_STATE_READY | 0 | | 217 | 29 | DEV_DSS_EDP0_PHY_LN2_TXMCLK | CLK_STATE_READY | 0 | | 217 | 30 | DEV_DSS_EDP0_PHY_LN3_REFCLK | CLK_STATE_READY | 0 | | 217 | 31 | DEV_DSS_EDP0_PHY_LN3_RXCLK | CLK_STATE_READY | 0 | | 217 | 32 | DEV_DSS_EDP0_PHY_LN3_RXFCLK | CLK_STATE_READY | 0 | | 217 | 33 | DEV_DSS_EDP0_PHY_LN3_TXCLK | CLK_STATE_READY | 0 | | 217 | 34 | DEV_DSS_EDP0_PHY_LN3_TXFCLK | CLK_STATE_READY | 0 | | 217 | 35 | DEV_DSS_EDP0_PHY_LN3_TXMCLK | CLK_STATE_READY | 0 | | 217 | 36 | DEV_DSS_EDP0_PLL_CTRL_CLK | CLK_STATE_READY | 500000000 | | 126 | 0 | DEV_ECAP0_VBUS_CLK | CLK_STATE_READY | 125000000 | | 127 | 0 | DEV_ECAP1_VBUS_CLK | CLK_STATE_READY | 125000000 | | 128 | 0 | DEV_ECAP2_VBUS_CLK | CLK_STATE_READY | 125000000 | | 130 | 0 | DEV_ELM0_VBUSP_CLK | CLK_STATE_READY | 125000000 | | 219 | 0 | DEV_EPWM0_VBUSP_CLK | CLK_STATE_READY | 125000000 | | 220 | 0 | DEV_EPWM1_VBUSP_CLK | CLK_STATE_READY | 125000000 | | 221 | 0 | DEV_EPWM2_VBUSP_CLK | CLK_STATE_READY | 125000000 | | 222 | 0 | DEV_EPWM3_VBUSP_CLK | CLK_STATE_READY | 125000000 | | 223 | 0 | DEV_EPWM4_VBUSP_CLK | CLK_STATE_READY | 125000000 | | 224 | 0 | DEV_EPWM5_VBUSP_CLK | CLK_STATE_READY | 125000000 | | 142 | 0 | DEV_EQEP0_VBUS_CLK | CLK_STATE_READY | 125000000 | | 143 | 0 | DEV_EQEP1_VBUS_CLK | CLK_STATE_READY | 125000000 | | 144 | 0 | DEV_EQEP2_VBUS_CLK | CLK_STATE_READY | 125000000 | | 145 | 0 | DEV_ESM0_CLK | CLK_STATE_READY | 125000000 | | 417 | 0 | DEV_GLUELOGIC_ACSPCIE0_BUFFER_CLKIN0 | CLK_STATE_READY | 24000000 | | 417 | 1 | DEV_GLUELOGIC_ACSPCIE0_BUFFER_CLKIN1 | CLK_STATE_READY | 24000000 | | 417 | 2 | DEV_GLUELOGIC_ACSPCIE0_BUFFER_PAD0_M | CLK_STATE_READY | 62500000 | | 417 | 3 | DEV_GLUELOGIC_ACSPCIE0_BUFFER_PAD0_P | CLK_STATE_READY | 12500000 | | 417 | 4 | DEV_GLUELOGIC_ACSPCIE0_BUFFER_PAD1_M | CLK_STATE_READY | 200000000 | | 417 | 5 | DEV_GLUELOGIC_ACSPCIE0_BUFFER_PAD1_P | CLK_STATE_READY | 0 | | 418 | 0 | DEV_GLUELOGIC_ACSPCIE1_BUFFER_CLKIN0 | CLK_STATE_READY | 24000000 | | 418 | 1 | DEV_GLUELOGIC_ACSPCIE1_BUFFER_CLKIN1 | CLK_STATE_READY | 24000000 | | 418 | 2 | DEV_GLUELOGIC_ACSPCIE1_BUFFER_PAD0_M | CLK_STATE_READY | 62500000 | | 418 | 3 | DEV_GLUELOGIC_ACSPCIE1_BUFFER_PAD0_P | CLK_STATE_READY | 12500000 | | 418 | 4 | DEV_GLUELOGIC_ACSPCIE1_BUFFER_PAD1_M | CLK_STATE_READY | 200000000 | | 418 | 5 | DEV_GLUELOGIC_ACSPCIE1_BUFFER_PAD1_P | CLK_STATE_READY | 0 | | 163 | 0 | DEV_GPIO0_MMR_CLK | CLK_STATE_READY | 125000000 | | 164 | 0 | DEV_GPIO2_MMR_CLK | CLK_STATE_READY | 125000000 | | 165 | 0 | DEV_GPIO4_MMR_CLK | CLK_STATE_READY | 125000000 | | 166 | 0 | DEV_GPIO6_MMR_CLK | CLK_STATE_READY | 125000000 | | 10 | 0 | DEV_GPIOMUX_INTRTR0_INTR_CLK | CLK_STATE_READY | 125000000 | | 169 | 0 | DEV_GPMC0_FUNC_CLK | CLK_STATE_READY | 133333333 | | 169 | 1 | DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT3_CLK | CLK_STATE_READY | 133333333 | | 169 | 2 | DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK6 | CLK_STATE_READY | 100000000 | | 169 | 3 | DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK4 | CLK_STATE_READY | 150000000 | | 169 | 4 | DEV_GPMC0_FUNC_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK4 | CLK_STATE_READY | 125000000 | | 169 | 5 | DEV_GPMC0_PI_GPMC_RET_CLK | CLK_STATE_READY | 0 | | 169 | 6 | DEV_GPMC0_PO_GPMC_DEV_CLK | CLK_STATE_READY | 0 | | 169 | 7 | DEV_GPMC0_VBUSM_CLK | CLK_STATE_READY | 250000000 | | 61 | 0 | DEV_GTC0_GTC_CLK | CLK_STATE_READY | 200000000 | | 61 | 1 | DEV_GTC0_GTC_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK | CLK_STATE_READY | 250000000 | | 61 | 2 | DEV_GTC0_GTC_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK | CLK_STATE_READY | 200000000 | | 61 | 3 | DEV_GTC0_GTC_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | 61 | 4 | DEV_GTC0_GTC_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | 61 | 5 | DEV_GTC0_GTC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 61 | 6 | DEV_GTC0_GTC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | 61 | 7 | DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN0_TXMCLK | CLK_STATE_READY | 0 | | 61 | 8 | DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN1_TXMCLK | CLK_STATE_READY | 0 | | 61 | 9 | DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN2_TXMCLK | CLK_STATE_READY | 0 | | 61 | 10 | DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN3_TXMCLK | CLK_STATE_READY | 0 | | 61 | 11 | DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN0_TXMCLK | CLK_STATE_READY | 0 | | 61 | 12 | DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN1_TXMCLK | CLK_STATE_READY | 0 | | 61 | 13 | DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP1_LN2_TXMCLK | CLK_STATE_READY | 0 | | 61 | 14 | DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP3_LN2_TXMCLK | CLK_STATE_READY | 0 | | 61 | 15 | DEV_GTC0_GTC_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK | CLK_STATE_READY | 500000000 | | 61 | 16 | DEV_GTC0_GTC_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK | CLK_STATE_READY | 500000000 | | 61 | 17 | DEV_GTC0_VBUSP_CLK | CLK_STATE_READY | 125000000 | | 270 | 0 | DEV_I2C0_CLK | CLK_STATE_READY | 125000000 | | 270 | 1 | DEV_I2C0_PISCL | CLK_STATE_READY | 0 | | 270 | 2 | DEV_I2C0_PISYS_CLK | CLK_STATE_READY | 96000000 | | 270 | 3 | DEV_I2C0_PORSCL | CLK_STATE_READY | 0 | | 271 | 0 | DEV_I2C1_CLK | CLK_STATE_READY | 125000000 | | 271 | 1 | DEV_I2C1_PISCL | CLK_STATE_READY | 0 | | 271 | 2 | DEV_I2C1_PISYS_CLK | CLK_STATE_READY | 96000000 | | 271 | 3 | DEV_I2C1_PORSCL | CLK_STATE_READY | 0 | | 272 | 0 | DEV_I2C2_CLK | CLK_STATE_READY | 125000000 | | 272 | 1 | DEV_I2C2_PISCL | CLK_STATE_READY | 0 | | 272 | 2 | DEV_I2C2_PISYS_CLK | CLK_STATE_READY | 96000000 | | 272 | 3 | DEV_I2C2_PORSCL | CLK_STATE_READY | 0 | | 273 | 0 | DEV_I2C3_CLK | CLK_STATE_READY | 125000000 | | 273 | 1 | DEV_I2C3_PISCL | CLK_STATE_READY | 0 | | 273 | 2 | DEV_I2C3_PISYS_CLK | CLK_STATE_READY | 96000000 | | 273 | 3 | DEV_I2C3_PORSCL | CLK_STATE_READY | 0 | | 274 | 0 | DEV_I2C4_CLK | CLK_STATE_READY | 125000000 | | 274 | 1 | DEV_I2C4_PISCL | CLK_STATE_READY | 0 | | 274 | 2 | DEV_I2C4_PISYS_CLK | CLK_STATE_READY | 96000000 | | 274 | 3 | DEV_I2C4_PORSCL | CLK_STATE_READY | 0 | | 275 | 0 | DEV_I2C5_CLK | CLK_STATE_READY | 125000000 | | 275 | 1 | DEV_I2C5_PISCL | CLK_STATE_READY | 0 | | 275 | 2 | DEV_I2C5_PISYS_CLK | CLK_STATE_READY | 96000000 | | 275 | 3 | DEV_I2C5_PORSCL | CLK_STATE_READY | 0 | | 276 | 0 | DEV_I2C6_CLK | CLK_STATE_READY | 125000000 | | 276 | 1 | DEV_I2C6_PISCL | CLK_STATE_READY | 0 | | 276 | 2 | DEV_I2C6_PISYS_CLK | CLK_STATE_READY | 96000000 | | 276 | 3 | DEV_I2C6_PORSCL | CLK_STATE_READY | 0 | | 181 | 1 | DEV_J7AEP_GPU_BXS464_WRAP0_GPU_SS_0_GPU_PLL_CLK | CLK_STATE_READY | 800000000 | | 181 | 4 | DEV_J7AEP_GPU_BXS464_WRAP0_GPU_SS_0_PLL_CTRL_CLK | CLK_STATE_READY | 500000000 | | 183 | 0 | DEV_J7AM_32_64_ATB_FUNNEL0_DBG_CLK | CLK_STATE_READY | 250000000 | | 184 | 0 | DEV_J7AM_32_64_ATB_FUNNEL1_DBG_CLK | CLK_STATE_READY | 250000000 | | 185 | 0 | DEV_J7AM_32_64_ATB_FUNNEL2_DBG_CLK | CLK_STATE_READY | 250000000 | | 187 | 0 | DEV_J7AM_BOLT_PGD0_WKUP_OSC0_CLK | CLK_STATE_READY | 24000000 | | 188 | 0 | DEV_J7AM_BOLT_PSC_WRAP0_CLK | CLK_STATE_READY | 125000000 | | 188 | 1 | DEV_J7AM_BOLT_PSC_WRAP0_SLOW_CLK | CLK_STATE_READY | 20833333 | | 197 | 0 | DEV_J7AM_HWA_ATB_FUNNEL0_DBG_CLK | CLK_STATE_READY | 250000000 | | 199 | 0 | DEV_J7AM_MAIN_16FF0_WKUP_OSC0_CLK | CLK_STATE_READY | 24000000 | | 7 | 0 | DEV_J7AM_PULSAR_ATB_FUNNEL0_DBG_CLK | CLK_STATE_READY | 250000000 | | 172 | 0 | DEV_LED0_LED_CLK | CLK_STATE_READY | 0 | | 172 | 1 | DEV_LED0_VBUS_CLK | CLK_STATE_READY | 250000000 | | 173 | 0 | DEV_MAIN2MCU_LVL_INTRTR0_INTR_CLK | CLK_STATE_READY | 125000000 | | 174 | 0 | DEV_MAIN2MCU_PLS_INTRTR0_INTR_CLK | CLK_STATE_READY | 125000000 | | 245 | 0 | DEV_MCAN0_MCANSS_CAN_RXD | CLK_STATE_READY | 0 | | 245 | 1 | DEV_MCAN0_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | 245 | 2 | DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | CLK_STATE_READY | 80000000 | | 245 | 3 | DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 245 | 4 | DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 245 | 5 | DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 24000000 | | 245 | 6 | DEV_MCAN0_MCANSS_HCLK_CLK | CLK_STATE_READY | 125000000 | | 246 | 0 | DEV_MCAN1_MCANSS_CAN_RXD | CLK_STATE_READY | 0 | | 246 | 1 | DEV_MCAN1_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | 246 | 2 | DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | CLK_STATE_READY | 80000000 | | 246 | 3 | DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 246 | 4 | DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 246 | 5 | DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 24000000 | | 246 | 6 | DEV_MCAN1_MCANSS_HCLK_CLK | CLK_STATE_READY | 125000000 | | 255 | 0 | DEV_MCAN10_MCANSS_CAN_RXD | CLK_STATE_READY | 0 | | 255 | 1 | DEV_MCAN10_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | 255 | 2 | DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | CLK_STATE_READY | 80000000 | | 255 | 3 | DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 255 | 4 | DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 255 | 5 | DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 24000000 | | 255 | 6 | DEV_MCAN10_MCANSS_HCLK_CLK | CLK_STATE_READY | 125000000 | | 256 | 0 | DEV_MCAN11_MCANSS_CAN_RXD | CLK_STATE_READY | 0 | | 256 | 1 | DEV_MCAN11_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | 256 | 2 | DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | CLK_STATE_READY | 80000000 | | 256 | 3 | DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 256 | 4 | DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 256 | 5 | DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 24000000 | | 256 | 6 | DEV_MCAN11_MCANSS_HCLK_CLK | CLK_STATE_READY | 125000000 | | 257 | 0 | DEV_MCAN12_MCANSS_CAN_RXD | CLK_STATE_READY | 0 | | 257 | 1 | DEV_MCAN12_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | 257 | 2 | DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | CLK_STATE_READY | 80000000 | | 257 | 3 | DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 257 | 4 | DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 257 | 5 | DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 24000000 | | 257 | 6 | DEV_MCAN12_MCANSS_HCLK_CLK | CLK_STATE_READY | 125000000 | | 258 | 0 | DEV_MCAN13_MCANSS_CAN_RXD | CLK_STATE_READY | 0 | | 258 | 1 | DEV_MCAN13_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | 258 | 2 | DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | CLK_STATE_READY | 80000000 | | 258 | 3 | DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 258 | 4 | DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 258 | 5 | DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 24000000 | | 258 | 6 | DEV_MCAN13_MCANSS_HCLK_CLK | CLK_STATE_READY | 125000000 | | 259 | 0 | DEV_MCAN14_MCANSS_CAN_RXD | CLK_STATE_READY | 0 | | 259 | 1 | DEV_MCAN14_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | 259 | 2 | DEV_MCAN14_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | CLK_STATE_READY | 80000000 | | 259 | 3 | DEV_MCAN14_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 259 | 4 | DEV_MCAN14_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 259 | 5 | DEV_MCAN14_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 24000000 | | 259 | 6 | DEV_MCAN14_MCANSS_HCLK_CLK | CLK_STATE_READY | 125000000 | | 260 | 0 | DEV_MCAN15_MCANSS_CAN_RXD | CLK_STATE_READY | 0 | | 260 | 1 | DEV_MCAN15_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | 260 | 2 | DEV_MCAN15_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | CLK_STATE_READY | 80000000 | | 260 | 3 | DEV_MCAN15_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 260 | 4 | DEV_MCAN15_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 260 | 5 | DEV_MCAN15_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 24000000 | | 260 | 6 | DEV_MCAN15_MCANSS_HCLK_CLK | CLK_STATE_READY | 125000000 | | 261 | 0 | DEV_MCAN16_MCANSS_CAN_RXD | CLK_STATE_READY | 0 | | 261 | 1 | DEV_MCAN16_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | 261 | 2 | DEV_MCAN16_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | CLK_STATE_READY | 80000000 | | 261 | 3 | DEV_MCAN16_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 261 | 4 | DEV_MCAN16_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 261 | 5 | DEV_MCAN16_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 24000000 | | 261 | 6 | DEV_MCAN16_MCANSS_HCLK_CLK | CLK_STATE_READY | 125000000 | | 262 | 0 | DEV_MCAN17_MCANSS_CAN_RXD | CLK_STATE_READY | 0 | | 262 | 1 | DEV_MCAN17_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | 262 | 2 | DEV_MCAN17_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | CLK_STATE_READY | 80000000 | | 262 | 3 | DEV_MCAN17_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 262 | 4 | DEV_MCAN17_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 262 | 5 | DEV_MCAN17_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 24000000 | | 262 | 6 | DEV_MCAN17_MCANSS_HCLK_CLK | CLK_STATE_READY | 125000000 | | 247 | 0 | DEV_MCAN2_MCANSS_CAN_RXD | CLK_STATE_READY | 0 | | 247 | 1 | DEV_MCAN2_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | 247 | 2 | DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | CLK_STATE_READY | 80000000 | | 247 | 3 | DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 247 | 4 | DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 247 | 5 | DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 24000000 | | 247 | 6 | DEV_MCAN2_MCANSS_HCLK_CLK | CLK_STATE_READY | 125000000 | | 248 | 0 | DEV_MCAN3_MCANSS_CAN_RXD | CLK_STATE_READY | 0 | | 248 | 1 | DEV_MCAN3_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | 248 | 2 | DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | CLK_STATE_READY | 80000000 | | 248 | 3 | DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 248 | 4 | DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 248 | 5 | DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 24000000 | | 248 | 6 | DEV_MCAN3_MCANSS_HCLK_CLK | CLK_STATE_READY | 125000000 | | 249 | 0 | DEV_MCAN4_MCANSS_CAN_RXD | CLK_STATE_READY | 0 | | 249 | 1 | DEV_MCAN4_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | 249 | 2 | DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | CLK_STATE_READY | 80000000 | | 249 | 3 | DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 249 | 4 | DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 249 | 5 | DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 24000000 | | 249 | 6 | DEV_MCAN4_MCANSS_HCLK_CLK | CLK_STATE_READY | 125000000 | | 250 | 0 | DEV_MCAN5_MCANSS_CAN_RXD | CLK_STATE_READY | 0 | | 250 | 1 | DEV_MCAN5_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | 250 | 2 | DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | CLK_STATE_READY | 80000000 | | 250 | 3 | DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 250 | 4 | DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 250 | 5 | DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 24000000 | | 250 | 6 | DEV_MCAN5_MCANSS_HCLK_CLK | CLK_STATE_READY | 125000000 | | 251 | 0 | DEV_MCAN6_MCANSS_CAN_RXD | CLK_STATE_READY | 0 | | 251 | 1 | DEV_MCAN6_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | 251 | 2 | DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | CLK_STATE_READY | 80000000 | | 251 | 3 | DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 251 | 4 | DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 251 | 5 | DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 24000000 | | 251 | 6 | DEV_MCAN6_MCANSS_HCLK_CLK | CLK_STATE_READY | 125000000 | | 252 | 0 | DEV_MCAN7_MCANSS_CAN_RXD | CLK_STATE_READY | 0 | | 252 | 1 | DEV_MCAN7_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | 252 | 2 | DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | CLK_STATE_READY | 80000000 | | 252 | 3 | DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 252 | 4 | DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 252 | 5 | DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 24000000 | | 252 | 6 | DEV_MCAN7_MCANSS_HCLK_CLK | CLK_STATE_READY | 125000000 | | 253 | 0 | DEV_MCAN8_MCANSS_CAN_RXD | CLK_STATE_READY | 0 | | 253 | 1 | DEV_MCAN8_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | 253 | 2 | DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | CLK_STATE_READY | 80000000 | | 253 | 3 | DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 253 | 4 | DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 253 | 5 | DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 24000000 | | 253 | 6 | DEV_MCAN8_MCANSS_HCLK_CLK | CLK_STATE_READY | 125000000 | | 254 | 0 | DEV_MCAN9_MCANSS_CAN_RXD | CLK_STATE_READY | 0 | | 254 | 1 | DEV_MCAN9_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | 254 | 2 | DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | CLK_STATE_READY | 80000000 | | 254 | 3 | DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 254 | 4 | DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 254 | 5 | DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 24000000 | | 254 | 6 | DEV_MCAN9_MCANSS_HCLK_CLK | CLK_STATE_READY | 125000000 | | 265 | 0 | DEV_MCASP0_AUX_CLK | CLK_STATE_READY | 196608000 | | 265 | 1 | DEV_MCASP0_AUX_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK | CLK_STATE_READY | 196608000 | | 265 | 2 | DEV_MCASP0_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | 265 | 5 | DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | 265 | 6 | DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | 265 | 7 | DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | 265 | 8 | DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | 265 | 9 | DEV_MCASP0_MCASP_ACLKR_PIN | CLK_STATE_READY | 0 | | 265 | 10 | DEV_MCASP0_MCASP_ACLKR_POUT | CLK_STATE_READY | 0 | | 265 | 11 | DEV_MCASP0_MCASP_ACLKX_PIN | CLK_STATE_READY | 0 | | 265 | 12 | DEV_MCASP0_MCASP_ACLKX_POUT | CLK_STATE_READY | 0 | | 265 | 13 | DEV_MCASP0_MCASP_AFSR_POUT | CLK_STATE_READY | 0 | | 265 | 14 | DEV_MCASP0_MCASP_AFSX_POUT | CLK_STATE_READY | 0 | | 265 | 15 | DEV_MCASP0_MCASP_AHCLKR_PIN | CLK_STATE_READY | 0 | | 265 | 16 | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 265 | 17 | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 24000000 | | 265 | 18 | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 265 | 19 | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | 265 | 24 | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | 265 | 25 | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | 265 | 26 | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | 265 | 27 | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | 265 | 32 | DEV_MCASP0_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | 265 | 33 | DEV_MCASP0_MCASP_AHCLKX_PIN | CLK_STATE_READY | 0 | | 265 | 34 | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 265 | 35 | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 24000000 | | 265 | 36 | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 265 | 37 | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | 265 | 42 | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | 265 | 43 | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | 265 | 44 | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | 265 | 45 | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | 265 | 50 | DEV_MCASP0_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | 265 | 51 | DEV_MCASP0_VBUSP_CLK | CLK_STATE_READY | 250000000 | | 266 | 0 | DEV_MCASP1_AUX_CLK | CLK_STATE_READY | 196608000 | | 266 | 1 | DEV_MCASP1_AUX_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK | CLK_STATE_READY | 196608000 | | 266 | 2 | DEV_MCASP1_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | 266 | 5 | DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | 266 | 6 | DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | 266 | 7 | DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | 266 | 8 | DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | 266 | 9 | DEV_MCASP1_MCASP_ACLKR_PIN | CLK_STATE_READY | 0 | | 266 | 10 | DEV_MCASP1_MCASP_ACLKR_POUT | CLK_STATE_READY | 0 | | 266 | 11 | DEV_MCASP1_MCASP_ACLKX_PIN | CLK_STATE_READY | 0 | | 266 | 12 | DEV_MCASP1_MCASP_ACLKX_POUT | CLK_STATE_READY | 0 | | 266 | 13 | DEV_MCASP1_MCASP_AFSR_POUT | CLK_STATE_READY | 0 | | 266 | 14 | DEV_MCASP1_MCASP_AFSX_POUT | CLK_STATE_READY | 0 | | 266 | 15 | DEV_MCASP1_MCASP_AHCLKR_PIN | CLK_STATE_READY | 0 | | 266 | 16 | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 266 | 17 | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 24000000 | | 266 | 18 | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 266 | 19 | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | 266 | 24 | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | 266 | 25 | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | 266 | 26 | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | 266 | 27 | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | 266 | 32 | DEV_MCASP1_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | 266 | 33 | DEV_MCASP1_MCASP_AHCLKX_PIN | CLK_STATE_READY | 0 | | 266 | 34 | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 266 | 35 | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 24000000 | | 266 | 36 | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 266 | 37 | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | 266 | 42 | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | 266 | 43 | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | 266 | 44 | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | 266 | 45 | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | 266 | 50 | DEV_MCASP1_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | 266 | 51 | DEV_MCASP1_VBUSP_CLK | CLK_STATE_READY | 250000000 | | 267 | 0 | DEV_MCASP2_AUX_CLK | CLK_STATE_READY | 196608000 | | 267 | 1 | DEV_MCASP2_AUX_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK | CLK_STATE_READY | 196608000 | | 267 | 2 | DEV_MCASP2_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | 267 | 5 | DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | 267 | 6 | DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | 267 | 7 | DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | 267 | 8 | DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | 267 | 9 | DEV_MCASP2_MCASP_ACLKR_PIN | CLK_STATE_READY | 0 | | 267 | 10 | DEV_MCASP2_MCASP_ACLKR_POUT | CLK_STATE_READY | 0 | | 267 | 11 | DEV_MCASP2_MCASP_ACLKX_PIN | CLK_STATE_READY | 0 | | 267 | 12 | DEV_MCASP2_MCASP_ACLKX_POUT | CLK_STATE_READY | 0 | | 267 | 13 | DEV_MCASP2_MCASP_AFSR_POUT | CLK_STATE_READY | 0 | | 267 | 14 | DEV_MCASP2_MCASP_AFSX_POUT | CLK_STATE_READY | 0 | | 267 | 15 | DEV_MCASP2_MCASP_AHCLKR_PIN | CLK_STATE_READY | 0 | | 267 | 16 | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 267 | 17 | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 24000000 | | 267 | 18 | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 267 | 19 | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | 267 | 24 | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | 267 | 25 | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | 267 | 26 | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | 267 | 27 | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | 267 | 32 | DEV_MCASP2_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | 267 | 33 | DEV_MCASP2_MCASP_AHCLKX_PIN | CLK_STATE_READY | 0 | | 267 | 34 | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 267 | 35 | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 24000000 | | 267 | 36 | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 267 | 37 | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | 267 | 42 | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | 267 | 43 | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | 267 | 44 | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | 267 | 45 | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | 267 | 50 | DEV_MCASP2_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | 267 | 51 | DEV_MCASP2_VBUSP_CLK | CLK_STATE_READY | 250000000 | | 268 | 0 | DEV_MCASP3_AUX_CLK | CLK_STATE_READY | 196608000 | | 268 | 1 | DEV_MCASP3_AUX_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK | CLK_STATE_READY | 196608000 | | 268 | 2 | DEV_MCASP3_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | 268 | 5 | DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | 268 | 6 | DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | 268 | 7 | DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | 268 | 8 | DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | 268 | 9 | DEV_MCASP3_MCASP_ACLKR_PIN | CLK_STATE_READY | 0 | | 268 | 10 | DEV_MCASP3_MCASP_ACLKR_POUT | CLK_STATE_READY | 0 | | 268 | 11 | DEV_MCASP3_MCASP_ACLKX_PIN | CLK_STATE_READY | 0 | | 268 | 12 | DEV_MCASP3_MCASP_ACLKX_POUT | CLK_STATE_READY | 0 | | 268 | 13 | DEV_MCASP3_MCASP_AFSR_POUT | CLK_STATE_READY | 0 | | 268 | 14 | DEV_MCASP3_MCASP_AFSX_POUT | CLK_STATE_READY | 0 | | 268 | 15 | DEV_MCASP3_MCASP_AHCLKR_PIN | CLK_STATE_READY | 0 | | 268 | 16 | DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 268 | 17 | DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 24000000 | | 268 | 18 | DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 268 | 19 | DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | 268 | 24 | DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | 268 | 25 | DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | 268 | 26 | DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | 268 | 27 | DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | 268 | 32 | DEV_MCASP3_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | 268 | 33 | DEV_MCASP3_MCASP_AHCLKX_PIN | CLK_STATE_READY | 0 | | 268 | 34 | DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 268 | 35 | DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 24000000 | | 268 | 36 | DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 268 | 37 | DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | 268 | 42 | DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | 268 | 43 | DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | 268 | 44 | DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | 268 | 45 | DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | 268 | 50 | DEV_MCASP3_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | 268 | 51 | DEV_MCASP3_VBUSP_CLK | CLK_STATE_READY | 250000000 | | 269 | 0 | DEV_MCASP4_AUX_CLK | CLK_STATE_READY | 196608000 | | 269 | 1 | DEV_MCASP4_AUX_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK | CLK_STATE_READY | 196608000 | | 269 | 2 | DEV_MCASP4_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | 269 | 5 | DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | 269 | 6 | DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | 269 | 7 | DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | 269 | 8 | DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | 269 | 9 | DEV_MCASP4_MCASP_ACLKR_PIN | CLK_STATE_READY | 0 | | 269 | 10 | DEV_MCASP4_MCASP_ACLKR_POUT | CLK_STATE_READY | 0 | | 269 | 11 | DEV_MCASP4_MCASP_ACLKX_PIN | CLK_STATE_READY | 0 | | 269 | 12 | DEV_MCASP4_MCASP_ACLKX_POUT | CLK_STATE_READY | 0 | | 269 | 13 | DEV_MCASP4_MCASP_AFSR_POUT | CLK_STATE_READY | 0 | | 269 | 14 | DEV_MCASP4_MCASP_AFSX_POUT | CLK_STATE_READY | 0 | | 269 | 15 | DEV_MCASP4_MCASP_AHCLKR_PIN | CLK_STATE_READY | 0 | | 269 | 16 | DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 269 | 17 | DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 24000000 | | 269 | 18 | DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 269 | 19 | DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | 269 | 24 | DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | 269 | 25 | DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | 269 | 26 | DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | 269 | 27 | DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | 269 | 32 | DEV_MCASP4_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | 269 | 33 | DEV_MCASP4_MCASP_AHCLKX_PIN | CLK_STATE_READY | 0 | | 269 | 34 | DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 269 | 35 | DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 24000000 | | 269 | 36 | DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 269 | 37 | DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | 269 | 42 | DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | 269 | 43 | DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | 269 | 44 | DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | 269 | 45 | DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | 269 | 50 | DEV_MCASP4_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | 269 | 51 | DEV_MCASP4_VBUSP_CLK | CLK_STATE_READY | 250000000 | | 376 | 0 | DEV_MCSPI0_CLKSPIREF_CLK | CLK_STATE_READY | 50000000 | | 376 | 1 | DEV_MCSPI0_IO_CLKSPII_CLK | CLK_STATE_READY | 0 | | 376 | 2 | DEV_MCSPI0_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI0_CLK_OUT | CLK_STATE_READY | 0 | | 376 | 3 | DEV_MCSPI0_IO_CLKSPII_CLK_PARENT_SPI_MAIN_0_IO_CLKSPIO_CLK | CLK_STATE_NOT_READY | 0 | | 376 | 4 | DEV_MCSPI0_IO_CLKSPIO_CLK | CLK_STATE_READY | 0 | | 376 | 5 | DEV_MCSPI0_VBUSP_CLK | CLK_STATE_READY | 125000000 | | 377 | 0 | DEV_MCSPI1_CLKSPIREF_CLK | CLK_STATE_READY | 50000000 | | 377 | 1 | DEV_MCSPI1_IO_CLKSPII_CLK | CLK_STATE_READY | 0 | | 377 | 2 | DEV_MCSPI1_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI1_CLK_OUT | CLK_STATE_READY | 0 | | 377 | 3 | DEV_MCSPI1_IO_CLKSPII_CLK_PARENT_SPI_MAIN_1_IO_CLKSPIO_CLK | CLK_STATE_NOT_READY | 0 | | 377 | 4 | DEV_MCSPI1_IO_CLKSPIO_CLK | CLK_STATE_READY | 0 | | 377 | 5 | DEV_MCSPI1_VBUSP_CLK | CLK_STATE_READY | 125000000 | | 378 | 0 | DEV_MCSPI2_CLKSPIREF_CLK | CLK_STATE_READY | 50000000 | | 378 | 1 | DEV_MCSPI2_IO_CLKSPII_CLK | CLK_STATE_READY | 0 | | 378 | 2 | DEV_MCSPI2_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI2_CLK_OUT | CLK_STATE_READY | 0 | | 378 | 3 | DEV_MCSPI2_IO_CLKSPII_CLK_PARENT_SPI_MAIN_2_IO_CLKSPIO_CLK | CLK_STATE_NOT_READY | 0 | | 378 | 4 | DEV_MCSPI2_IO_CLKSPIO_CLK | CLK_STATE_READY | 0 | | 378 | 5 | DEV_MCSPI2_VBUSP_CLK | CLK_STATE_READY | 125000000 | | 379 | 0 | DEV_MCSPI3_CLKSPIREF_CLK | CLK_STATE_READY | 50000000 | | 379 | 1 | DEV_MCSPI3_IO_CLKSPII_CLK | CLK_STATE_NOT_READY | 0 | | 379 | 2 | DEV_MCSPI3_IO_CLKSPII_CLK_PARENT_SPI_MAIN_3_IO_CLKSPIO_CLK | CLK_STATE_NOT_READY | 0 | | 379 | 3 | DEV_MCSPI3_IO_CLKSPII_CLK_PARENT_SPI3_CLK_LPBK_MUX_OUT0 | CLK_STATE_READY | 0 | | 379 | 4 | DEV_MCSPI3_IO_CLKSPIO_CLK | CLK_STATE_READY | 0 | | 379 | 5 | DEV_MCSPI3_VBUSP_CLK | CLK_STATE_READY | 125000000 | | 380 | 0 | DEV_MCSPI4_CLKSPIREF_CLK | CLK_STATE_READY | 50000000 | | 380 | 1 | DEV_MCSPI4_IO_CLKSPII_CLK | CLK_STATE_READY | 0 | | 380 | 2 | DEV_MCSPI4_IO_CLKSPIO_CLK | CLK_STATE_READY | 0 | | 380 | 3 | DEV_MCSPI4_VBUSP_CLK | CLK_STATE_READY | 125000000 | | 381 | 0 | DEV_MCSPI5_CLKSPIREF_CLK | CLK_STATE_READY | 50000000 | | 381 | 1 | DEV_MCSPI5_IO_CLKSPII_CLK | CLK_STATE_READY | 0 | | 381 | 2 | DEV_MCSPI5_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI5_CLK_OUT | CLK_STATE_READY | 0 | | 381 | 3 | DEV_MCSPI5_IO_CLKSPII_CLK_PARENT_SPI_MAIN_5_IO_CLKSPIO_CLK | CLK_STATE_NOT_READY | 0 | | 381 | 4 | DEV_MCSPI5_IO_CLKSPIO_CLK | CLK_STATE_READY | 0 | | 381 | 5 | DEV_MCSPI5_VBUSP_CLK | CLK_STATE_READY | 125000000 | | 382 | 0 | DEV_MCSPI6_CLKSPIREF_CLK | CLK_STATE_READY | 50000000 | | 382 | 1 | DEV_MCSPI6_IO_CLKSPII_CLK | CLK_STATE_READY | 0 | | 382 | 2 | DEV_MCSPI6_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI6_CLK_OUT | CLK_STATE_READY | 0 | | 382 | 3 | DEV_MCSPI6_IO_CLKSPII_CLK_PARENT_SPI_MAIN_6_IO_CLKSPIO_CLK | CLK_STATE_NOT_READY | 0 | | 382 | 4 | DEV_MCSPI6_IO_CLKSPIO_CLK | CLK_STATE_READY | 0 | | 382 | 5 | DEV_MCSPI6_VBUSP_CLK | CLK_STATE_READY | 125000000 | | 383 | 0 | DEV_MCSPI7_CLKSPIREF_CLK | CLK_STATE_READY | 50000000 | | 383 | 1 | DEV_MCSPI7_IO_CLKSPII_CLK | CLK_STATE_READY | 0 | | 383 | 2 | DEV_MCSPI7_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI7_CLK_OUT | CLK_STATE_READY | 0 | | 383 | 3 | DEV_MCSPI7_IO_CLKSPII_CLK_PARENT_SPI_MAIN_7_IO_CLKSPIO_CLK | CLK_STATE_NOT_READY | 0 | | 383 | 4 | DEV_MCSPI7_IO_CLKSPIO_CLK | CLK_STATE_READY | 0 | | 383 | 5 | DEV_MCSPI7_VBUSP_CLK | CLK_STATE_READY | 125000000 | | 0 | 0 | DEV_MCU_ADC12FC_16FFC0_ADC_CLK | CLK_STATE_READY | 24000000 | | 0 | 1 | DEV_MCU_ADC12FC_16FFC0_ADC_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 24000000 | | 0 | 2 | DEV_MCU_ADC12FC_16FFC0_ADC_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT1_CLK | CLK_STATE_READY | 60000000 | | 0 | 3 | DEV_MCU_ADC12FC_16FFC0_ADC_CLK_PARENT_HSDIV1_16FFT_MCU_0_HSDIVOUT1_CLK | CLK_STATE_READY | 58823529 | | 0 | 4 | DEV_MCU_ADC12FC_16FFC0_ADC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 0 | 5 | DEV_MCU_ADC12FC_16FFC0_SYS_CLK | CLK_STATE_READY | 500000000 | | 0 | 6 | DEV_MCU_ADC12FC_16FFC0_VBUS_CLK | CLK_STATE_READY | 333333333 | | 1 | 0 | DEV_MCU_ADC12FC_16FFC1_ADC_CLK | CLK_STATE_READY | 24000000 | | 1 | 1 | DEV_MCU_ADC12FC_16FFC1_ADC_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 24000000 | | 1 | 2 | DEV_MCU_ADC12FC_16FFC1_ADC_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT1_CLK | CLK_STATE_READY | 60000000 | | 1 | 3 | DEV_MCU_ADC12FC_16FFC1_ADC_CLK_PARENT_HSDIV1_16FFT_MCU_0_HSDIVOUT1_CLK | CLK_STATE_READY | 58823529 | | 1 | 4 | DEV_MCU_ADC12FC_16FFC1_ADC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 1 | 5 | DEV_MCU_ADC12FC_16FFC1_SYS_CLK | CLK_STATE_READY | 500000000 | | 1 | 6 | DEV_MCU_ADC12FC_16FFC1_VBUS_CLK | CLK_STATE_READY | 333333333 | | 63 | 0 | DEV_MCU_CPSW0_CPPI_CLK_CLK | CLK_STATE_READY | 333333333 | | 63 | 1 | DEV_MCU_CPSW0_CPTS_GENF0 | CLK_STATE_READY | 0 | | 63 | 3 | DEV_MCU_CPSW0_CPTS_RFT_CLK | CLK_STATE_READY | 500000000 | | 63 | 4 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK | CLK_STATE_READY | 250000000 | | 63 | 5 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK | CLK_STATE_READY | 200000000 | | 63 | 6 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | 63 | 7 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | 63 | 8 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 63 | 9 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | 63 | 10 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN0_TXMCLK | CLK_STATE_READY | 0 | | 63 | 11 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN1_TXMCLK | CLK_STATE_READY | 0 | | 63 | 12 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN2_TXMCLK | CLK_STATE_READY | 0 | | 63 | 13 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN3_TXMCLK | CLK_STATE_READY | 0 | | 63 | 14 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN0_TXMCLK | CLK_STATE_READY | 0 | | 63 | 15 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN1_TXMCLK | CLK_STATE_READY | 0 | | 63 | 16 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP1_LN2_TXMCLK | CLK_STATE_READY | 0 | | 63 | 17 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP3_LN2_TXMCLK | CLK_STATE_READY | 0 | | 63 | 18 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK | CLK_STATE_READY | 500000000 | | 63 | 19 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK2 | CLK_STATE_READY | 500000000 | | 63 | 20 | DEV_MCU_CPSW0_GMII1_MR_CLK | CLK_STATE_READY | 25000000 | | 63 | 21 | DEV_MCU_CPSW0_GMII1_MT_CLK | CLK_STATE_READY | 25000000 | | 63 | 22 | DEV_MCU_CPSW0_GMII_RFT_CLK | CLK_STATE_READY | 125000000 | | 63 | 23 | DEV_MCU_CPSW0_MDIO_MDCLK_O | CLK_STATE_READY | 0 | | 63 | 24 | DEV_MCU_CPSW0_RGMII1_RXC_I | CLK_STATE_READY | 0 | | 63 | 26 | DEV_MCU_CPSW0_RGMII1_TXC_O | CLK_STATE_READY | 0 | | 63 | 27 | DEV_MCU_CPSW0_RGMII_MHZ_250_CLK | CLK_STATE_READY | 250000000 | | 63 | 28 | DEV_MCU_CPSW0_RGMII_MHZ_50_CLK | CLK_STATE_READY | 50000000 | | 63 | 29 | DEV_MCU_CPSW0_RGMII_MHZ_5_CLK | CLK_STATE_READY | 5000000 | | 63 | 30 | DEV_MCU_CPSW0_RMII_MHZ_50_CLK | CLK_STATE_READY | 0 | | 71 | 0 | DEV_MCU_CPT2_AGGR0_VCLK_CLK | CLK_STATE_READY | 333333333 | | 88 | 0 | DEV_MCU_DCC0_DCC_CLKSRC0_CLK | CLK_STATE_READY | 200000000 | | 88 | 1 | DEV_MCU_DCC0_DCC_CLKSRC1_CLK | CLK_STATE_READY | 60000000 | | 88 | 2 | DEV_MCU_DCC0_DCC_CLKSRC2_CLK | CLK_STATE_READY | 80000000 | | 88 | 3 | DEV_MCU_DCC0_DCC_CLKSRC3_CLK | CLK_STATE_READY | 96000000 | | 88 | 4 | DEV_MCU_DCC0_DCC_CLKSRC4_CLK | CLK_STATE_READY | 133333333 | | 88 | 5 | DEV_MCU_DCC0_DCC_CLKSRC5_CLK | CLK_STATE_READY | 32000 | | 88 | 6 | DEV_MCU_DCC0_DCC_CLKSRC6_CLK | CLK_STATE_READY | 32768 | | 88 | 7 | DEV_MCU_DCC0_DCC_CLKSRC7_CLK | CLK_STATE_READY | 0 | | 88 | 8 | DEV_MCU_DCC0_DCC_INPUT00_CLK | CLK_STATE_READY | 24000000 | | 88 | 9 | DEV_MCU_DCC0_DCC_INPUT01_CLK | CLK_STATE_READY | 32000 | | 88 | 10 | DEV_MCU_DCC0_DCC_INPUT02_CLK | CLK_STATE_READY | 12500000 | | 88 | 11 | DEV_MCU_DCC0_DCC_INPUT10_CLK | CLK_STATE_READY | 333333333 | | 88 | 12 | DEV_MCU_DCC0_VBUS_CLK | CLK_STATE_READY | 166666666 | | 89 | 0 | DEV_MCU_DCC1_DCC_CLKSRC0_CLK | CLK_STATE_READY | 250000000 | | 89 | 1 | DEV_MCU_DCC1_DCC_CLKSRC1_CLK | CLK_STATE_READY | 200000000 | | 89 | 2 | DEV_MCU_DCC1_DCC_CLKSRC2_CLK | CLK_STATE_READY | 80000000 | | 89 | 3 | DEV_MCU_DCC1_DCC_CLKSRC3_CLK | CLK_STATE_READY | 166666666 | | 89 | 4 | DEV_MCU_DCC1_DCC_CLKSRC4_CLK | CLK_STATE_READY | 250000000 | | 89 | 5 | DEV_MCU_DCC1_DCC_CLKSRC5_CLK | CLK_STATE_READY | 58823529 | | 89 | 6 | DEV_MCU_DCC1_DCC_CLKSRC6_CLK | CLK_STATE_READY | 0 | | 89 | 7 | DEV_MCU_DCC1_DCC_CLKSRC7_CLK | CLK_STATE_READY | 500000000 | | 89 | 8 | DEV_MCU_DCC1_DCC_INPUT00_CLK | CLK_STATE_READY | 24000000 | | 89 | 9 | DEV_MCU_DCC1_DCC_INPUT01_CLK | CLK_STATE_READY | 32768 | | 89 | 10 | DEV_MCU_DCC1_DCC_INPUT02_CLK | CLK_STATE_READY | 12500000 | | 89 | 11 | DEV_MCU_DCC1_DCC_INPUT10_CLK | CLK_STATE_READY | 250000000 | | 89 | 12 | DEV_MCU_DCC1_VBUS_CLK | CLK_STATE_READY | 166666666 | | 90 | 0 | DEV_MCU_DCC2_DCC_CLKSRC0_CLK | CLK_STATE_READY | 0 | | 90 | 1 | DEV_MCU_DCC2_DCC_CLKSRC1_CLK | CLK_STATE_READY | 0 | | 90 | 2 | DEV_MCU_DCC2_DCC_CLKSRC2_CLK | CLK_STATE_READY | 0 | | 90 | 3 | DEV_MCU_DCC2_DCC_CLKSRC3_CLK | CLK_STATE_READY | 192000000 | | 90 | 4 | DEV_MCU_DCC2_DCC_CLKSRC4_CLK | CLK_STATE_READY | 0 | | 90 | 6 | DEV_MCU_DCC2_DCC_CLKSRC6_CLK | CLK_STATE_READY | 12500000 | | 90 | 7 | DEV_MCU_DCC2_DCC_CLKSRC7_CLK | CLK_STATE_READY | 24000000 | | 90 | 8 | DEV_MCU_DCC2_DCC_INPUT00_CLK | CLK_STATE_READY | 24000000 | | 90 | 9 | DEV_MCU_DCC2_DCC_INPUT01_CLK | CLK_STATE_READY | 0 | | 90 | 10 | DEV_MCU_DCC2_DCC_INPUT02_CLK | CLK_STATE_READY | 12500000 | | 90 | 11 | DEV_MCU_DCC2_DCC_INPUT10_CLK | CLK_STATE_READY | 333333333 | | 90 | 12 | DEV_MCU_DCC2_VBUS_CLK | CLK_STATE_READY | 166666666 | | 148 | 0 | DEV_MCU_ESM0_CLK | CLK_STATE_READY | 166666666 | | 158 | 0 | DEV_MCU_FSS0_FSAS_0_GCLK | CLK_STATE_READY | 1000000000 | | 160 | 0 | DEV_MCU_FSS0_HYPERBUS1P0_0_CBA_CLK | CLK_STATE_READY | 1000000000 | | 160 | 2 | DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX1_CLK | CLK_STATE_READY | 83333333 | | 160 | 4 | DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX1_INV_CLK | CLK_STATE_READY | 83333333 | | 160 | 6 | DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX2_CLK | CLK_STATE_READY | 166666666 | | 160 | 8 | DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX2_INV_CLK | CLK_STATE_READY | 166666666 | | 160 | 10 | DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_OUT_CLK_N | CLK_STATE_READY | 0 | | 160 | 11 | DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_OUT_CLK_P | CLK_STATE_READY | 0 | | 161 | 0 | DEV_MCU_FSS0_OSPI_0_OSPI_DQS_CLK | CLK_STATE_READY | 0 | | 161 | 1 | DEV_MCU_FSS0_OSPI_0_OSPI_HCLK_CLK | CLK_STATE_READY | 1000000000 | | 161 | 2 | DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK | CLK_STATE_READY | 0 | | 161 | 3 | DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_BOARD_0_MCU_OSPI0_DQS_OUT | CLK_STATE_READY | 0 | | 161 | 4 | DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_FSS_MCU_0_OSPI_0_OSPI_OCLK_CLK | CLK_STATE_NOT_READY | 0 | | 161 | 5 | DEV_MCU_FSS0_OSPI_0_OSPI_OCLK_CLK | CLK_STATE_READY | 0 | | 161 | 6 | DEV_MCU_FSS0_OSPI_0_OSPI_PCLK_CLK | CLK_STATE_READY | 1000000000 | | 161 | 7 | DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK | CLK_STATE_READY | 166666666 | | 161 | 8 | DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT4_CLK | CLK_STATE_READY | 133333333 | | 161 | 9 | DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT4_CLK | CLK_STATE_READY | 166666666 | | 162 | 0 | DEV_MCU_FSS0_OSPI_1_OSPI_DQS_CLK | CLK_STATE_READY | 0 | | 162 | 1 | DEV_MCU_FSS0_OSPI_1_OSPI_HCLK_CLK | CLK_STATE_READY | 1000000000 | | 162 | 2 | DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK | CLK_STATE_READY | 0 | | 162 | 3 | DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK_PARENT_BOARD_0_MCU_OSPI1_DQS_OUT | CLK_STATE_READY | 0 | | 162 | 4 | DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK_PARENT_FSS_MCU_0_OSPI_1_OSPI_OCLK_CLK | CLK_STATE_READY | 0 | | 162 | 5 | DEV_MCU_FSS0_OSPI_1_OSPI_OCLK_CLK | CLK_STATE_READY | 0 | | 162 | 6 | DEV_MCU_FSS0_OSPI_1_OSPI_PCLK_CLK | CLK_STATE_READY | 1000000000 | | 162 | 7 | DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK | CLK_STATE_READY | 133333333 | | 162 | 8 | DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT4_CLK | CLK_STATE_READY | 133333333 | | 162 | 9 | DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT4_CLK | CLK_STATE_READY | 166666666 | | 277 | 0 | DEV_MCU_I2C0_CLK | CLK_STATE_READY | 166666666 | | 277 | 1 | DEV_MCU_I2C0_PISCL | CLK_STATE_READY | 0 | | 277 | 2 | DEV_MCU_I2C0_PISYS_CLK | CLK_STATE_READY | 96000000 | | 277 | 3 | DEV_MCU_I2C0_PORSCL | CLK_STATE_READY | 0 | | 278 | 0 | DEV_MCU_I2C1_CLK | CLK_STATE_READY | 166666666 | | 278 | 1 | DEV_MCU_I2C1_PISCL | CLK_STATE_READY | 0 | | 278 | 2 | DEV_MCU_I2C1_PISYS_CLK | CLK_STATE_READY | 96000000 | | 278 | 3 | DEV_MCU_I2C1_PORSCL | CLK_STATE_READY | 0 | | 170 | 0 | DEV_MCU_I3C0_I3C_PCLK_CLK | CLK_STATE_READY | 166666666 | | 170 | 1 | DEV_MCU_I3C0_I3C_SCL_DI | CLK_STATE_READY | 0 | | 170 | 2 | DEV_MCU_I3C0_I3C_SCL_DO | CLK_STATE_READY | 0 | | 170 | 3 | DEV_MCU_I3C0_I3C_SCLK_CLK | CLK_STATE_READY | 166666666 | | 170 | 4 | DEV_MCU_I3C0_I3C_SDA_DI | CLK_STATE_READY | 0 | | 171 | 0 | DEV_MCU_I3C1_I3C_PCLK_CLK | CLK_STATE_READY | 166666666 | | 171 | 3 | DEV_MCU_I3C1_I3C_SCLK_CLK | CLK_STATE_READY | 166666666 | | 263 | 0 | DEV_MCU_MCAN0_MCANSS_CAN_RXD | CLK_STATE_READY | 0 | | 263 | 1 | DEV_MCU_MCAN0_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | 263 | 2 | DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT3_CLK | CLK_STATE_READY | 80000000 | | 263 | 3 | DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 263 | 4 | DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT2_CLK | CLK_STATE_READY | 80000000 | | 263 | 5 | DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 24000000 | | 263 | 6 | DEV_MCU_MCAN0_MCANSS_HCLK_CLK | CLK_STATE_READY | 166666666 | | 264 | 0 | DEV_MCU_MCAN1_MCANSS_CAN_RXD | CLK_STATE_READY | 0 | | 264 | 1 | DEV_MCU_MCAN1_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | 264 | 2 | DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT3_CLK | CLK_STATE_READY | 80000000 | | 264 | 3 | DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 264 | 4 | DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT2_CLK | CLK_STATE_READY | 80000000 | | 264 | 5 | DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 24000000 | | 264 | 6 | DEV_MCU_MCAN1_MCANSS_HCLK_CLK | CLK_STATE_READY | 166666666 | | 384 | 0 | DEV_MCU_MCSPI0_CLKSPIREF_CLK | CLK_STATE_READY | 50000000 | | 384 | 1 | DEV_MCU_MCSPI0_IO_CLKSPII_CLK | CLK_STATE_READY | 0 | | 384 | 2 | DEV_MCU_MCSPI0_IO_CLKSPII_CLK_PARENT_BOARD_0_MCU_SPI0_CLK_OUT | CLK_STATE_READY | 0 | | 384 | 3 | DEV_MCU_MCSPI0_IO_CLKSPII_CLK_PARENT_SPI_MCU_0_IO_CLKSPIO_CLK | CLK_STATE_READY | 0 | | 384 | 4 | DEV_MCU_MCSPI0_IO_CLKSPIO_CLK | CLK_STATE_READY | 0 | | 384 | 5 | DEV_MCU_MCSPI0_VBUSP_CLK | CLK_STATE_READY | 166666666 | | 385 | 0 | DEV_MCU_MCSPI1_CLKSPIREF_CLK | CLK_STATE_READY | 50000000 | | 385 | 1 | DEV_MCU_MCSPI1_IO_CLKSPII_CLK | CLK_STATE_NOT_READY | 0 | | 385 | 2 | DEV_MCU_MCSPI1_IO_CLKSPII_CLK_PARENT_SPI_MAIN_3_IO_CLKSPIO_CLK | CLK_STATE_NOT_READY | 0 | | 385 | 3 | DEV_MCU_MCSPI1_IO_CLKSPII_CLK_PARENT_MCU_SPI1_CLK_LPBK_MUX_OUT0 | CLK_STATE_READY | 0 | | 385 | 4 | DEV_MCU_MCSPI1_IO_CLKSPIO_CLK | CLK_STATE_READY | 0 | | 385 | 5 | DEV_MCU_MCSPI1_VBUSP_CLK | CLK_STATE_READY | 166666666 | | 386 | 0 | DEV_MCU_MCSPI2_CLKSPIREF_CLK | CLK_STATE_READY | 50000000 | | 386 | 1 | DEV_MCU_MCSPI2_IO_CLKSPII_CLK | CLK_STATE_READY | 0 | | 386 | 2 | DEV_MCU_MCSPI2_IO_CLKSPIO_CLK | CLK_STATE_READY | 0 | | 386 | 3 | DEV_MCU_MCSPI2_VBUSP_CLK | CLK_STATE_READY | 166666666 | | 324 | 0 | DEV_MCU_NAVSS0_INTR_ROUTER_0_INTR_CLK | CLK_STATE_READY | 1000000000 | | 325 | 0 | DEV_MCU_NAVSS0_MCRC_0_CLK | CLK_STATE_READY | 1000000000 | | 326 | 0 | DEV_MCU_NAVSS0_MODSS_VD2CLK | CLK_STATE_READY | 1000000000 | | 327 | 0 | DEV_MCU_NAVSS0_PROXY0_CLK_CLK | CLK_STATE_READY | 1000000000 | | 328 | 0 | DEV_MCU_NAVSS0_RINGACC0_SYS_CLK | CLK_STATE_READY | 1000000000 | | 329 | 0 | DEV_MCU_NAVSS0_UDMAP_0_SYS_CLK | CLK_STATE_READY | 1000000000 | | 330 | 0 | DEV_MCU_NAVSS0_UDMASS_VD2CLK | CLK_STATE_READY | 1000000000 | | 331 | 0 | DEV_MCU_NAVSS0_UDMASS_INTA_0_SYS_CLK | CLK_STATE_READY | 1000000000 | | 238 | 0 | DEV_MCU_PBIST0_CLK1_CLK | CLK_STATE_READY | 500000000 | | 238 | 1 | DEV_MCU_PBIST0_CLK2_CLK | CLK_STATE_READY | 333333333 | | 238 | 2 | DEV_MCU_PBIST0_CLK3_CLK | CLK_STATE_READY | 166666666 | | 238 | 3 | DEV_MCU_PBIST0_CLK4_CLK | CLK_STATE_READY | 83333333 | | 238 | 4 | DEV_MCU_PBIST0_CLK5_CLK | CLK_STATE_READY | 83333333 | | 238 | 5 | DEV_MCU_PBIST0_CLK6_CLK | CLK_STATE_READY | 83333333 | | 238 | 6 | DEV_MCU_PBIST0_CLK7_CLK | CLK_STATE_READY | 83333333 | | 238 | 7 | DEV_MCU_PBIST0_CLK8_CLK | CLK_STATE_READY | 83333333 | | 239 | 0 | DEV_MCU_PBIST1_CLK1_CLK | CLK_STATE_READY | 500000000 | | 239 | 1 | DEV_MCU_PBIST1_CLK2_CLK | CLK_STATE_READY | 400000000 | | 239 | 2 | DEV_MCU_PBIST1_CLK3_CLK | CLK_STATE_READY | 333333333 | | 239 | 3 | DEV_MCU_PBIST1_CLK4_CLK | CLK_STATE_READY | 83333333 | | 239 | 4 | DEV_MCU_PBIST1_CLK5_CLK | CLK_STATE_READY | 166666666 | | 239 | 5 | DEV_MCU_PBIST1_CLK6_CLK | CLK_STATE_READY | 83333333 | | 239 | 6 | DEV_MCU_PBIST1_CLK7_CLK | CLK_STATE_READY | 83333333 | | 239 | 7 | DEV_MCU_PBIST1_CLK8_CLK | CLK_STATE_READY | 83333333 | | 240 | 7 | DEV_MCU_PBIST2_CLK8_CLK | CLK_STATE_READY | 83333333 | | 346 | 0 | DEV_MCU_R5FSS0_CORE0_CPU_CLK | CLK_STATE_READY | 1000000000 | | 346 | 1 | DEV_MCU_R5FSS0_CORE0_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK | CLK_STATE_READY | 1000000000 | | 346 | 2 | DEV_MCU_R5FSS0_CORE0_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK3 | CLK_STATE_READY | 333333333 | | 346 | 3 | DEV_MCU_R5FSS0_CORE0_INTERFACE_CLK | CLK_STATE_READY | 1000000000 | | 346 | 4 | DEV_MCU_R5FSS0_CORE0_INTERFACE_PHASE | CLK_STATE_READY | 333333333 | | 347 | 0 | DEV_MCU_R5FSS0_CORE1_CPU_CLK | CLK_STATE_READY | 1000000000 | | 347 | 1 | DEV_MCU_R5FSS0_CORE1_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK | CLK_STATE_READY | 1000000000 | | 347 | 2 | DEV_MCU_R5FSS0_CORE1_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK3 | CLK_STATE_READY | 333333333 | | 347 | 3 | DEV_MCU_R5FSS0_CORE1_INTERFACE_CLK | CLK_STATE_READY | 1000000000 | | 347 | 4 | DEV_MCU_R5FSS0_CORE1_INTERFACE_PHASE | CLK_STATE_READY | 333333333 | | 367 | 0 | DEV_MCU_RTI0_RTI_CLK | CLK_STATE_READY | 24000000 | | 367 | 1 | DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 24000000 | | 367 | 2 | DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | CLK_STATE_READY | 32768 | | 367 | 3 | DEV_MCU_RTI0_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | 367 | 4 | DEV_MCU_RTI0_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32000 | | 367 | 9 | DEV_MCU_RTI0_VBUSP_CLK | CLK_STATE_READY | 166666666 | | 368 | 0 | DEV_MCU_RTI1_RTI_CLK | CLK_STATE_READY | 24000000 | | 368 | 1 | DEV_MCU_RTI1_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 24000000 | | 368 | 2 | DEV_MCU_RTI1_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | CLK_STATE_READY | 32768 | | 368 | 3 | DEV_MCU_RTI1_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | 368 | 4 | DEV_MCU_RTI1_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32000 | | 368 | 9 | DEV_MCU_RTI1_VBUSP_CLK | CLK_STATE_READY | 166666666 | | 35 | 0 | DEV_MCU_TIMER0_TIMER_HCLK_CLK | CLK_STATE_READY | 166666666 | | 35 | 1 | DEV_MCU_TIMER0_TIMER_PWM | CLK_STATE_READY | 0 | | 35 | 2 | DEV_MCU_TIMER0_TIMER_TCLK_CLK | CLK_STATE_READY | 62500000 | | 35 | 3 | DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 24000000 | | 35 | 4 | DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16 | CLK_STATE_READY | 62500000 | | 35 | 5 | DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | 35 | 6 | DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | 35 | 7 | DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 35 | 8 | DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | CLK_STATE_READY | 32768 | | 35 | 9 | DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0 | CLK_STATE_READY | 0 | | 35 | 10 | DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32000 | | 117 | 0 | DEV_MCU_TIMER1_TIMER_HCLK_CLK | CLK_STATE_READY | 166666666 | | 117 | 2 | DEV_MCU_TIMER1_TIMER_TCLK_CLK | CLK_STATE_READY | 24000000 | | 117 | 3 | DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT1 | CLK_STATE_READY | 24000000 | | 117 | 4 | DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_0_TIMER_PWM | CLK_STATE_READY | 0 | | 118 | 0 | DEV_MCU_TIMER2_TIMER_HCLK_CLK | CLK_STATE_READY | 166666666 | | 118 | 1 | DEV_MCU_TIMER2_TIMER_PWM | CLK_STATE_READY | 0 | | 118 | 2 | DEV_MCU_TIMER2_TIMER_TCLK_CLK | CLK_STATE_READY | 24000000 | | 118 | 3 | DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 24000000 | | 118 | 4 | DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16 | CLK_STATE_READY | 62500000 | | 118 | 5 | DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | 118 | 6 | DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | 118 | 7 | DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 118 | 8 | DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | CLK_STATE_READY | 32768 | | 118 | 9 | DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0 | CLK_STATE_READY | 0 | | 118 | 10 | DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32000 | | 119 | 0 | DEV_MCU_TIMER3_TIMER_HCLK_CLK | CLK_STATE_READY | 166666666 | | 119 | 2 | DEV_MCU_TIMER3_TIMER_TCLK_CLK | CLK_STATE_READY | 24000000 | | 119 | 3 | DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT3 | CLK_STATE_READY | 24000000 | | 119 | 4 | DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_2_TIMER_PWM | CLK_STATE_READY | 0 | | 120 | 0 | DEV_MCU_TIMER4_TIMER_HCLK_CLK | CLK_STATE_READY | 166666666 | | 120 | 1 | DEV_MCU_TIMER4_TIMER_PWM | CLK_STATE_READY | 0 | | 120 | 2 | DEV_MCU_TIMER4_TIMER_TCLK_CLK | CLK_STATE_READY | 24000000 | | 120 | 3 | DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 24000000 | | 120 | 4 | DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16 | CLK_STATE_READY | 62500000 | | 120 | 5 | DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | 120 | 6 | DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | 120 | 7 | DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 120 | 8 | DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | CLK_STATE_READY | 32768 | | 120 | 9 | DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0 | CLK_STATE_READY | 0 | | 120 | 10 | DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32000 | | 121 | 0 | DEV_MCU_TIMER5_TIMER_HCLK_CLK | CLK_STATE_READY | 166666666 | | 121 | 2 | DEV_MCU_TIMER5_TIMER_TCLK_CLK | CLK_STATE_READY | 24000000 | | 121 | 3 | DEV_MCU_TIMER5_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT5 | CLK_STATE_READY | 24000000 | | 121 | 4 | DEV_MCU_TIMER5_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_4_TIMER_PWM | CLK_STATE_READY | 0 | | 122 | 0 | DEV_MCU_TIMER6_TIMER_HCLK_CLK | CLK_STATE_READY | 166666666 | | 122 | 1 | DEV_MCU_TIMER6_TIMER_PWM | CLK_STATE_READY | 0 | | 122 | 2 | DEV_MCU_TIMER6_TIMER_TCLK_CLK | CLK_STATE_READY | 24000000 | | 122 | 3 | DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 24000000 | | 122 | 4 | DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16 | CLK_STATE_READY | 62500000 | | 122 | 5 | DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | 122 | 6 | DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | 122 | 7 | DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 122 | 8 | DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | CLK_STATE_READY | 32768 | | 122 | 9 | DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0 | CLK_STATE_READY | 0 | | 122 | 10 | DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32000 | | 123 | 0 | DEV_MCU_TIMER7_TIMER_HCLK_CLK | CLK_STATE_READY | 166666666 | | 123 | 2 | DEV_MCU_TIMER7_TIMER_TCLK_CLK | CLK_STATE_READY | 24000000 | | 123 | 3 | DEV_MCU_TIMER7_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT7 | CLK_STATE_READY | 24000000 | | 123 | 4 | DEV_MCU_TIMER7_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_6_TIMER_PWM | CLK_STATE_READY | 0 | | 124 | 0 | DEV_MCU_TIMER8_TIMER_HCLK_CLK | CLK_STATE_READY | 166666666 | | 124 | 1 | DEV_MCU_TIMER8_TIMER_PWM | CLK_STATE_READY | 0 | | 124 | 2 | DEV_MCU_TIMER8_TIMER_TCLK_CLK | CLK_STATE_READY | 24000000 | | 124 | 3 | DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 24000000 | | 124 | 4 | DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16 | CLK_STATE_READY | 62500000 | | 124 | 5 | DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | 124 | 6 | DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | 124 | 7 | DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 124 | 8 | DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | CLK_STATE_READY | 32768 | | 124 | 9 | DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0 | CLK_STATE_READY | 0 | | 124 | 10 | DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32000 | | 125 | 0 | DEV_MCU_TIMER9_TIMER_HCLK_CLK | CLK_STATE_READY | 166666666 | | 125 | 2 | DEV_MCU_TIMER9_TIMER_TCLK_CLK | CLK_STATE_READY | 62500000 | | 125 | 3 | DEV_MCU_TIMER9_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT9 | CLK_STATE_READY | 62500000 | | 125 | 4 | DEV_MCU_TIMER9_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_8_TIMER_PWM | CLK_STATE_READY | 0 | | 149 | 0 | DEV_MCU_UART0_FCLK_CLK | CLK_STATE_READY | 96000000 | | 149 | 1 | DEV_MCU_UART0_FCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT3_CLK | CLK_STATE_READY | 96000000 | | 149 | 2 | DEV_MCU_UART0_FCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_1_HSDIVOUT5_CLK | CLK_STATE_READY | 192000000 | | 149 | 5 | DEV_MCU_UART0_VBUSP_CLK | CLK_STATE_READY | 166666666 | | 140 | 1 | DEV_MMCSD0_EMMCSS_VBUS_CLK | CLK_STATE_READY | 250000000 | | 140 | 2 | DEV_MMCSD0_EMMCSS_XIN_CLK | CLK_STATE_READY | 200000000 | | 140 | 3 | DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | 140 | 4 | DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT2_CLK | CLK_STATE_READY | 192000000 | | 140 | 5 | DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | 140 | 6 | DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT2_CLK | CLK_STATE_READY | 192307692 | | 141 | 0 | DEV_MMCSD1_EMMCSDSS_IO_CLK_I | CLK_STATE_READY | 0 | | 141 | 1 | DEV_MMCSD1_EMMCSDSS_IO_CLK_O | CLK_STATE_READY | 0 | | 141 | 3 | DEV_MMCSD1_EMMCSDSS_VBUS_CLK | CLK_STATE_READY | 250000000 | | 141 | 4 | DEV_MMCSD1_EMMCSDSS_XIN_CLK | CLK_STATE_READY | 200000000 | | 141 | 5 | DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | 141 | 6 | DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT2_CLK | CLK_STATE_READY | 192000000 | | 141 | 7 | DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | 141 | 8 | DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT2_CLK | CLK_STATE_READY | 192307692 | | 280 | 0 | DEV_NAVSS0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | 280 | 1 | DEV_NAVSS0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | 281 | 0 | DEV_NAVSS0_BCDMA_0_CLK | CLK_STATE_READY | 500000000 | | 282 | 0 | DEV_NAVSS0_CPTS_0_RCLK | CLK_STATE_READY | 250000000 | | 282 | 1 | DEV_NAVSS0_CPTS_0_RCLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK | CLK_STATE_READY | 250000000 | | 282 | 2 | DEV_NAVSS0_CPTS_0_RCLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK | CLK_STATE_READY | 200000000 | | 282 | 3 | DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | 282 | 4 | DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | 282 | 5 | DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 282 | 6 | DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | 282 | 7 | DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN0_TXMCLK | CLK_STATE_READY | 0 | | 282 | 8 | DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN1_TXMCLK | CLK_STATE_READY | 0 | | 282 | 9 | DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN2_TXMCLK | CLK_STATE_READY | 0 | | 282 | 10 | DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN3_TXMCLK | CLK_STATE_READY | 0 | | 282 | 11 | DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN0_TXMCLK | CLK_STATE_READY | 0 | | 282 | 12 | DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN1_TXMCLK | CLK_STATE_READY | 0 | | 282 | 13 | DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP1_LN2_TXMCLK | CLK_STATE_READY | 0 | | 282 | 14 | DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP3_LN2_TXMCLK | CLK_STATE_READY | 0 | | 282 | 15 | DEV_NAVSS0_CPTS_0_RCLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK | CLK_STATE_READY | 500000000 | | 282 | 16 | DEV_NAVSS0_CPTS_0_RCLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK | CLK_STATE_READY | 500000000 | | 282 | 17 | DEV_NAVSS0_CPTS_0_TS_GENF0 | CLK_STATE_READY | 0 | | 282 | 18 | DEV_NAVSS0_CPTS_0_TS_GENF1 | CLK_STATE_READY | 0 | | 282 | 21 | DEV_NAVSS0_CPTS_0_VBUSP_GCLK | CLK_STATE_READY | 500000000 | | 283 | 0 | DEV_NAVSS0_INTR_0_INTR_CLK | CLK_STATE_READY | 500000000 | | 284 | 0 | DEV_NAVSS0_MAILBOX1_0_VCLK_CLK | CLK_STATE_READY | 500000000 | | 285 | 0 | DEV_NAVSS0_MAILBOX1_1_VCLK_CLK | CLK_STATE_READY | 500000000 | | 294 | 0 | DEV_NAVSS0_MAILBOX1_10_VCLK_CLK | CLK_STATE_READY | 500000000 | | 295 | 0 | DEV_NAVSS0_MAILBOX1_11_VCLK_CLK | CLK_STATE_READY | 500000000 | | 286 | 0 | DEV_NAVSS0_MAILBOX1_2_VCLK_CLK | CLK_STATE_READY | 500000000 | | 287 | 0 | DEV_NAVSS0_MAILBOX1_3_VCLK_CLK | CLK_STATE_READY | 500000000 | | 288 | 0 | DEV_NAVSS0_MAILBOX1_4_VCLK_CLK | CLK_STATE_READY | 500000000 | | 289 | 0 | DEV_NAVSS0_MAILBOX1_5_VCLK_CLK | CLK_STATE_READY | 500000000 | | 290 | 0 | DEV_NAVSS0_MAILBOX1_6_VCLK_CLK | CLK_STATE_READY | 500000000 | | 291 | 0 | DEV_NAVSS0_MAILBOX1_7_VCLK_CLK | CLK_STATE_READY | 500000000 | | 292 | 0 | DEV_NAVSS0_MAILBOX1_8_VCLK_CLK | CLK_STATE_READY | 500000000 | | 293 | 0 | DEV_NAVSS0_MAILBOX1_9_VCLK_CLK | CLK_STATE_READY | 500000000 | | 296 | 0 | DEV_NAVSS0_MAILBOX_0_VCLK_CLK | CLK_STATE_READY | 500000000 | | 297 | 0 | DEV_NAVSS0_MAILBOX_1_VCLK_CLK | CLK_STATE_READY | 500000000 | | 306 | 0 | DEV_NAVSS0_MAILBOX_10_VCLK_CLK | CLK_STATE_READY | 500000000 | | 307 | 0 | DEV_NAVSS0_MAILBOX_11_VCLK_CLK | CLK_STATE_READY | 500000000 | | 298 | 0 | DEV_NAVSS0_MAILBOX_2_VCLK_CLK | CLK_STATE_READY | 500000000 | | 299 | 0 | DEV_NAVSS0_MAILBOX_3_VCLK_CLK | CLK_STATE_READY | 500000000 | | 300 | 0 | DEV_NAVSS0_MAILBOX_4_VCLK_CLK | CLK_STATE_READY | 500000000 | | 301 | 0 | DEV_NAVSS0_MAILBOX_5_VCLK_CLK | CLK_STATE_READY | 500000000 | | 302 | 0 | DEV_NAVSS0_MAILBOX_6_VCLK_CLK | CLK_STATE_READY | 500000000 | | 303 | 0 | DEV_NAVSS0_MAILBOX_7_VCLK_CLK | CLK_STATE_READY | 500000000 | | 304 | 0 | DEV_NAVSS0_MAILBOX_8_VCLK_CLK | CLK_STATE_READY | 500000000 | | 305 | 0 | DEV_NAVSS0_MAILBOX_9_VCLK_CLK | CLK_STATE_READY | 500000000 | | 308 | 0 | DEV_NAVSS0_MCRC_0_CLK | CLK_STATE_READY | 500000000 | | 309 | 0 | DEV_NAVSS0_MODSS_VD2CLK | CLK_STATE_READY | 500000000 | | 310 | 0 | DEV_NAVSS0_MODSS_INTA_0_SYS_CLK | CLK_STATE_READY | 500000000 | | 311 | 0 | DEV_NAVSS0_MODSS_INTA_1_SYS_CLK | CLK_STATE_READY | 500000000 | | 312 | 0 | DEV_NAVSS0_PROXY_0_CLK_CLK | CLK_STATE_READY | 500000000 | | 313 | 0 | DEV_NAVSS0_PVU_0_CLK_CLK | CLK_STATE_READY | 500000000 | | 314 | 0 | DEV_NAVSS0_PVU_1_CLK_CLK | CLK_STATE_READY | 500000000 | | 315 | 0 | DEV_NAVSS0_RINGACC_0_SYS_CLK | CLK_STATE_READY | 500000000 | | 316 | 0 | DEV_NAVSS0_SPINLOCK_0_CLK | CLK_STATE_READY | 500000000 | | 317 | 0 | DEV_NAVSS0_TIMERMGR_0_EON_TICK_EVT | CLK_STATE_READY | 0 | | 317 | 1 | DEV_NAVSS0_TIMERMGR_0_VCLK_CLK | CLK_STATE_READY | 500000000 | | 318 | 0 | DEV_NAVSS0_TIMERMGR_1_EON_TICK_EVT | CLK_STATE_READY | 0 | | 318 | 1 | DEV_NAVSS0_TIMERMGR_1_VCLK_CLK | CLK_STATE_READY | 500000000 | | 319 | 0 | DEV_NAVSS0_UDMAP_0_SYS_CLK | CLK_STATE_READY | 500000000 | | 320 | 0 | DEV_NAVSS0_UDMASS_VD2CLK | CLK_STATE_READY | 500000000 | | 321 | 0 | DEV_NAVSS0_UDMASS_INTA_0_SYS_CLK | CLK_STATE_READY | 500000000 | | 322 | 0 | DEV_NAVSS0_VIRTSS_VD2CLK | CLK_STATE_READY | 500000000 | | 232 | 7 | DEV_PBIST0_CLK8_CLK | CLK_STATE_READY | 125000000 | | 233 | 7 | DEV_PBIST1_CLK8_CLK | CLK_STATE_READY | 125000000 | | 236 | 7 | DEV_PBIST10_CLK8_CLK | CLK_STATE_READY | 125000000 | | 227 | 6 | DEV_PBIST11_CLK7_CLK | CLK_STATE_READY | 125000000 | | 237 | 7 | DEV_PBIST14_CLK8_CLK | CLK_STATE_READY | 125000000 | | 235 | 7 | DEV_PBIST2_CLK8_CLK | CLK_STATE_READY | 125000000 | | 231 | 7 | DEV_PBIST3_CLK8_CLK | CLK_STATE_READY | 125000000 | | 234 | 7 | DEV_PBIST4_CLK8_CLK | CLK_STATE_READY | 125000000 | | 226 | 7 | DEV_PBIST5_CLK8_CLK | CLK_STATE_READY | 125000000 | | 332 | 0 | DEV_PCIE0_PCIE_CBA_CLK | CLK_STATE_READY | 250000000 | | 332 | 2 | DEV_PCIE0_PCIE_CPTS_RCLK_CLK | CLK_STATE_READY | 250000000 | | 332 | 3 | DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK | CLK_STATE_READY | 250000000 | | 332 | 4 | DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK | CLK_STATE_READY | 200000000 | | 332 | 5 | DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | 332 | 6 | DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | 332 | 7 | DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 332 | 8 | DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | 332 | 9 | DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN0_TXMCLK | CLK_STATE_READY | 0 | | 332 | 10 | DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN1_TXMCLK | CLK_STATE_READY | 0 | | 332 | 11 | DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN2_TXMCLK | CLK_STATE_READY | 0 | | 332 | 12 | DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN3_TXMCLK | CLK_STATE_READY | 0 | | 332 | 13 | DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN0_TXMCLK | CLK_STATE_READY | 0 | | 332 | 14 | DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN1_TXMCLK | CLK_STATE_READY | 0 | | 332 | 15 | DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP1_LN2_TXMCLK | CLK_STATE_READY | 0 | | 332 | 16 | DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP3_LN2_TXMCLK | CLK_STATE_READY | 0 | | 332 | 17 | DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK | CLK_STATE_READY | 500000000 | | 332 | 18 | DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK | CLK_STATE_READY | 500000000 | | 332 | 19 | DEV_PCIE0_PCIE_LANE0_REFCLK | CLK_STATE_READY | 0 | | 332 | 20 | DEV_PCIE0_PCIE_LANE0_RXCLK | CLK_STATE_READY | 0 | | 332 | 21 | DEV_PCIE0_PCIE_LANE0_RXFCLK | CLK_STATE_READY | 0 | | 332 | 22 | DEV_PCIE0_PCIE_LANE0_TXCLK | CLK_STATE_READY | 0 | | 332 | 23 | DEV_PCIE0_PCIE_LANE0_TXFCLK | CLK_STATE_READY | 0 | | 332 | 24 | DEV_PCIE0_PCIE_LANE0_TXMCLK | CLK_STATE_READY | 0 | | 332 | 25 | DEV_PCIE0_PCIE_LANE1_REFCLK | CLK_STATE_READY | 0 | | 332 | 26 | DEV_PCIE0_PCIE_LANE1_RXCLK | CLK_STATE_READY | 0 | | 332 | 27 | DEV_PCIE0_PCIE_LANE1_RXFCLK | CLK_STATE_READY | 0 | | 332 | 28 | DEV_PCIE0_PCIE_LANE1_TXCLK | CLK_STATE_READY | 0 | | 332 | 29 | DEV_PCIE0_PCIE_LANE1_TXFCLK | CLK_STATE_READY | 0 | | 332 | 30 | DEV_PCIE0_PCIE_LANE1_TXMCLK | CLK_STATE_READY | 0 | | 332 | 31 | DEV_PCIE0_PCIE_LANE2_REFCLK | CLK_STATE_READY | 0 | | 332 | 32 | DEV_PCIE0_PCIE_LANE2_RXCLK | CLK_STATE_READY | 0 | | 332 | 33 | DEV_PCIE0_PCIE_LANE2_RXFCLK | CLK_STATE_READY | 0 | | 332 | 34 | DEV_PCIE0_PCIE_LANE2_TXCLK | CLK_STATE_READY | 0 | | 332 | 35 | DEV_PCIE0_PCIE_LANE2_TXFCLK | CLK_STATE_READY | 0 | | 332 | 36 | DEV_PCIE0_PCIE_LANE2_TXMCLK | CLK_STATE_READY | 0 | | 332 | 37 | DEV_PCIE0_PCIE_LANE3_REFCLK | CLK_STATE_READY | 0 | | 332 | 38 | DEV_PCIE0_PCIE_LANE3_RXCLK | CLK_STATE_READY | 0 | | 332 | 39 | DEV_PCIE0_PCIE_LANE3_RXFCLK | CLK_STATE_READY | 0 | | 332 | 40 | DEV_PCIE0_PCIE_LANE3_TXCLK | CLK_STATE_READY | 0 | | 332 | 41 | DEV_PCIE0_PCIE_LANE3_TXFCLK | CLK_STATE_READY | 0 | | 332 | 42 | DEV_PCIE0_PCIE_LANE3_TXMCLK | CLK_STATE_READY | 0 | | 332 | 43 | DEV_PCIE0_PCIE_PM_CLK | CLK_STATE_READY | 12500000 | | 333 | 0 | DEV_PCIE1_PCIE_CBA_CLK | CLK_STATE_READY | 250000000 | | 333 | 2 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK | CLK_STATE_READY | 250000000 | | 333 | 3 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK | CLK_STATE_READY | 250000000 | | 333 | 4 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK | CLK_STATE_READY | 200000000 | | 333 | 5 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | 333 | 6 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | 333 | 7 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 333 | 8 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | 333 | 9 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN0_TXMCLK | CLK_STATE_READY | 0 | | 333 | 10 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN1_TXMCLK | CLK_STATE_READY | 0 | | 333 | 11 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN2_TXMCLK | CLK_STATE_READY | 0 | | 333 | 12 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN3_TXMCLK | CLK_STATE_READY | 0 | | 333 | 13 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN0_TXMCLK | CLK_STATE_READY | 0 | | 333 | 14 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN1_TXMCLK | CLK_STATE_READY | 0 | | 333 | 15 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP1_LN2_TXMCLK | CLK_STATE_READY | 0 | | 333 | 16 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP3_LN2_TXMCLK | CLK_STATE_READY | 0 | | 333 | 17 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK | CLK_STATE_READY | 500000000 | | 333 | 18 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK | CLK_STATE_READY | 500000000 | | 333 | 19 | DEV_PCIE1_PCIE_LANE0_REFCLK | CLK_STATE_READY | 0 | | 333 | 20 | DEV_PCIE1_PCIE_LANE0_RXCLK | CLK_STATE_READY | 0 | | 333 | 21 | DEV_PCIE1_PCIE_LANE0_RXFCLK | CLK_STATE_READY | 0 | | 333 | 22 | DEV_PCIE1_PCIE_LANE0_TXCLK | CLK_STATE_READY | 0 | | 333 | 23 | DEV_PCIE1_PCIE_LANE0_TXFCLK | CLK_STATE_READY | 0 | | 333 | 24 | DEV_PCIE1_PCIE_LANE0_TXMCLK | CLK_STATE_READY | 0 | | 333 | 25 | DEV_PCIE1_PCIE_LANE1_REFCLK | CLK_STATE_READY | 0 | | 333 | 26 | DEV_PCIE1_PCIE_LANE1_RXCLK | CLK_STATE_READY | 0 | | 333 | 27 | DEV_PCIE1_PCIE_LANE1_RXFCLK | CLK_STATE_READY | 0 | | 333 | 28 | DEV_PCIE1_PCIE_LANE1_TXCLK | CLK_STATE_READY | 0 | | 333 | 29 | DEV_PCIE1_PCIE_LANE1_TXFCLK | CLK_STATE_READY | 0 | | 333 | 30 | DEV_PCIE1_PCIE_LANE1_TXMCLK | CLK_STATE_READY | 0 | | 333 | 31 | DEV_PCIE1_PCIE_LANE2_REFCLK | CLK_STATE_READY | 0 | | 333 | 32 | DEV_PCIE1_PCIE_LANE2_RXCLK | CLK_STATE_READY | 0 | | 333 | 33 | DEV_PCIE1_PCIE_LANE2_RXFCLK | CLK_STATE_READY | 0 | | 333 | 34 | DEV_PCIE1_PCIE_LANE2_TXCLK | CLK_STATE_READY | 0 | | 333 | 35 | DEV_PCIE1_PCIE_LANE2_TXFCLK | CLK_STATE_READY | 0 | | 333 | 36 | DEV_PCIE1_PCIE_LANE2_TXMCLK | CLK_STATE_READY | 0 | | 333 | 37 | DEV_PCIE1_PCIE_LANE3_REFCLK | CLK_STATE_READY | 0 | | 333 | 38 | DEV_PCIE1_PCIE_LANE3_RXCLK | CLK_STATE_READY | 0 | | 333 | 39 | DEV_PCIE1_PCIE_LANE3_RXFCLK | CLK_STATE_READY | 0 | | 333 | 40 | DEV_PCIE1_PCIE_LANE3_TXCLK | CLK_STATE_READY | 0 | | 333 | 41 | DEV_PCIE1_PCIE_LANE3_TXFCLK | CLK_STATE_READY | 0 | | 333 | 42 | DEV_PCIE1_PCIE_LANE3_TXMCLK | CLK_STATE_READY | 0 | | 333 | 43 | DEV_PCIE1_PCIE_PM_CLK | CLK_STATE_READY | 12500000 | | 334 | 0 | DEV_PCIE2_PCIE_CBA_CLK | CLK_STATE_READY | 250000000 | | 334 | 2 | DEV_PCIE2_PCIE_CPTS_RCLK_CLK | CLK_STATE_READY | 250000000 | | 334 | 3 | DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK | CLK_STATE_READY | 250000000 | | 334 | 4 | DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK | CLK_STATE_READY | 200000000 | | 334 | 5 | DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | 334 | 6 | DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | 334 | 7 | DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 334 | 8 | DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | 334 | 9 | DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN0_TXMCLK | CLK_STATE_READY | 0 | | 334 | 10 | DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN1_TXMCLK | CLK_STATE_READY | 0 | | 334 | 11 | DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN2_TXMCLK | CLK_STATE_READY | 0 | | 334 | 12 | DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN3_TXMCLK | CLK_STATE_READY | 0 | | 334 | 13 | DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN0_TXMCLK | CLK_STATE_READY | 0 | | 334 | 14 | DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN1_TXMCLK | CLK_STATE_READY | 0 | | 334 | 15 | DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP1_LN2_TXMCLK | CLK_STATE_READY | 0 | | 334 | 16 | DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP3_LN2_TXMCLK | CLK_STATE_READY | 0 | | 334 | 17 | DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK | CLK_STATE_READY | 500000000 | | 334 | 18 | DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK | CLK_STATE_READY | 500000000 | | 334 | 19 | DEV_PCIE2_PCIE_LANE0_REFCLK | CLK_STATE_READY | 0 | | 334 | 20 | DEV_PCIE2_PCIE_LANE0_RXCLK | CLK_STATE_READY | 0 | | 334 | 21 | DEV_PCIE2_PCIE_LANE0_RXFCLK | CLK_STATE_READY | 0 | | 334 | 22 | DEV_PCIE2_PCIE_LANE0_TXCLK | CLK_STATE_READY | 0 | | 334 | 23 | DEV_PCIE2_PCIE_LANE0_TXFCLK | CLK_STATE_READY | 0 | | 334 | 24 | DEV_PCIE2_PCIE_LANE0_TXMCLK | CLK_STATE_READY | 0 | | 334 | 25 | DEV_PCIE2_PCIE_LANE1_REFCLK | CLK_STATE_READY | 0 | | 334 | 26 | DEV_PCIE2_PCIE_LANE1_RXCLK | CLK_STATE_READY | 0 | | 334 | 27 | DEV_PCIE2_PCIE_LANE1_RXFCLK | CLK_STATE_READY | 0 | | 334 | 28 | DEV_PCIE2_PCIE_LANE1_TXCLK | CLK_STATE_READY | 0 | | 334 | 29 | DEV_PCIE2_PCIE_LANE1_TXFCLK | CLK_STATE_READY | 0 | | 334 | 30 | DEV_PCIE2_PCIE_LANE1_TXMCLK | CLK_STATE_READY | 0 | | 334 | 43 | DEV_PCIE2_PCIE_PM_CLK | CLK_STATE_READY | 12500000 | | 335 | 0 | DEV_PCIE3_PCIE_CBA_CLK | CLK_STATE_READY | 250000000 | | 335 | 2 | DEV_PCIE3_PCIE_CPTS_RCLK_CLK | CLK_STATE_READY | 250000000 | | 335 | 3 | DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK | CLK_STATE_READY | 250000000 | | 335 | 4 | DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK | CLK_STATE_READY | 200000000 | | 335 | 5 | DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | 335 | 6 | DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | 335 | 7 | DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 335 | 8 | DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | 335 | 9 | DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN0_TXMCLK | CLK_STATE_READY | 0 | | 335 | 10 | DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN1_TXMCLK | CLK_STATE_READY | 0 | | 335 | 11 | DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN2_TXMCLK | CLK_STATE_READY | 0 | | 335 | 12 | DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN3_TXMCLK | CLK_STATE_READY | 0 | | 335 | 13 | DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN0_TXMCLK | CLK_STATE_READY | 0 | | 335 | 14 | DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN1_TXMCLK | CLK_STATE_READY | 0 | | 335 | 15 | DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP1_LN2_TXMCLK | CLK_STATE_READY | 0 | | 335 | 16 | DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP3_LN2_TXMCLK | CLK_STATE_READY | 0 | | 335 | 17 | DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK | CLK_STATE_READY | 500000000 | | 335 | 18 | DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK | CLK_STATE_READY | 500000000 | | 335 | 19 | DEV_PCIE3_PCIE_LANE0_REFCLK | CLK_STATE_READY | 0 | | 335 | 20 | DEV_PCIE3_PCIE_LANE0_RXCLK | CLK_STATE_READY | 0 | | 335 | 21 | DEV_PCIE3_PCIE_LANE0_RXFCLK | CLK_STATE_READY | 0 | | 335 | 22 | DEV_PCIE3_PCIE_LANE0_TXCLK | CLK_STATE_READY | 0 | | 335 | 23 | DEV_PCIE3_PCIE_LANE0_TXFCLK | CLK_STATE_READY | 0 | | 335 | 24 | DEV_PCIE3_PCIE_LANE0_TXMCLK | CLK_STATE_READY | 0 | | 335 | 25 | DEV_PCIE3_PCIE_LANE1_REFCLK | CLK_STATE_READY | 0 | | 335 | 26 | DEV_PCIE3_PCIE_LANE1_RXCLK | CLK_STATE_READY | 0 | | 335 | 27 | DEV_PCIE3_PCIE_LANE1_RXFCLK | CLK_STATE_READY | 0 | | 335 | 28 | DEV_PCIE3_PCIE_LANE1_TXCLK | CLK_STATE_READY | 0 | | 335 | 29 | DEV_PCIE3_PCIE_LANE1_TXFCLK | CLK_STATE_READY | 0 | | 335 | 30 | DEV_PCIE3_PCIE_LANE1_TXMCLK | CLK_STATE_READY | 0 | | 335 | 43 | DEV_PCIE3_PCIE_PM_CLK | CLK_STATE_READY | 12500000 | | 201 | 0 | DEV_PSC0_CLK | CLK_STATE_READY | 125000000 | | 201 | 1 | DEV_PSC0_SLOW_CLK | CLK_STATE_READY | 20833333 | | 339 | 0 | DEV_R5FSS0_CORE0_CPU_CLK | CLK_STATE_READY | 1000000000 | | 339 | 1 | DEV_R5FSS0_CORE0_INTERFACE_CLK | CLK_STATE_READY | 1000000000 | | 340 | 0 | DEV_R5FSS0_CORE1_CPU_CLK | CLK_STATE_READY | 1000000000 | | 340 | 1 | DEV_R5FSS0_CORE1_INTERFACE_CLK | CLK_STATE_READY | 1000000000 | | 341 | 0 | DEV_R5FSS1_CORE0_CPU_CLK | CLK_STATE_READY | 1000000000 | | 341 | 1 | DEV_R5FSS1_CORE0_INTERFACE_CLK | CLK_STATE_READY | 1000000000 | | 342 | 0 | DEV_R5FSS1_CORE1_CPU_CLK | CLK_STATE_READY | 1000000000 | | 342 | 1 | DEV_R5FSS1_CORE1_INTERFACE_CLK | CLK_STATE_READY | 1000000000 | | 343 | 0 | DEV_R5FSS2_CORE0_CPU_CLK | CLK_STATE_READY | 1000000000 | | 343 | 1 | DEV_R5FSS2_CORE0_INTERFACE_CLK | CLK_STATE_READY | 1000000000 | | 344 | 0 | DEV_R5FSS2_CORE1_CPU_CLK | CLK_STATE_READY | 1000000000 | | 344 | 1 | DEV_R5FSS2_CORE1_INTERFACE_CLK | CLK_STATE_READY | 1000000000 | | 348 | 0 | DEV_RTI0_RTI_CLK | CLK_STATE_READY | 32000 | | 348 | 1 | DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 24000000 | | 348 | 2 | DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | CLK_STATE_READY | 32768 | | 348 | 3 | DEV_RTI0_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | 348 | 4 | DEV_RTI0_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32000 | | 348 | 5 | DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 348 | 6 | DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0 | CLK_STATE_READY | 0 | | 348 | 7 | DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1 | CLK_STATE_READY | 0 | | 348 | 8 | DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2 | CLK_STATE_READY | 0 | | 348 | 9 | DEV_RTI0_VBUSP_CLK | CLK_STATE_READY | 125000000 | | 349 | 0 | DEV_RTI1_RTI_CLK | CLK_STATE_READY | 32000 | | 349 | 1 | DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 24000000 | | 349 | 2 | DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | CLK_STATE_READY | 32768 | | 349 | 3 | DEV_RTI1_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | 349 | 4 | DEV_RTI1_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32000 | | 349 | 5 | DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 349 | 6 | DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0 | CLK_STATE_READY | 0 | | 349 | 7 | DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1 | CLK_STATE_READY | 0 | | 349 | 8 | DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2 | CLK_STATE_READY | 0 | | 349 | 9 | DEV_RTI1_VBUSP_CLK | CLK_STATE_READY | 125000000 | | 360 | 0 | DEV_RTI15_RTI_CLK | CLK_STATE_READY | 24000000 | | 360 | 1 | DEV_RTI15_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 24000000 | | 360 | 2 | DEV_RTI15_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | CLK_STATE_READY | 32768 | | 360 | 3 | DEV_RTI15_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | 360 | 4 | DEV_RTI15_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32000 | | 360 | 5 | DEV_RTI15_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 360 | 6 | DEV_RTI15_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0 | CLK_STATE_READY | 0 | | 360 | 7 | DEV_RTI15_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1 | CLK_STATE_READY | 0 | | 360 | 8 | DEV_RTI15_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2 | CLK_STATE_READY | 0 | | 360 | 9 | DEV_RTI15_VBUSP_CLK | CLK_STATE_READY | 125000000 | | 356 | 0 | DEV_RTI16_RTI_CLK | CLK_STATE_READY | 24000000 | | 356 | 1 | DEV_RTI16_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 24000000 | | 356 | 2 | DEV_RTI16_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | CLK_STATE_READY | 32768 | | 356 | 3 | DEV_RTI16_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | 356 | 4 | DEV_RTI16_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32000 | | 356 | 5 | DEV_RTI16_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 356 | 6 | DEV_RTI16_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0 | CLK_STATE_READY | 0 | | 356 | 7 | DEV_RTI16_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1 | CLK_STATE_READY | 0 | | 356 | 8 | DEV_RTI16_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2 | CLK_STATE_READY | 0 | | 356 | 9 | DEV_RTI16_VBUSP_CLK | CLK_STATE_READY | 125000000 | | 357 | 0 | DEV_RTI17_RTI_CLK | CLK_STATE_READY | 24000000 | | 357 | 1 | DEV_RTI17_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 24000000 | | 357 | 2 | DEV_RTI17_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | CLK_STATE_READY | 32768 | | 357 | 3 | DEV_RTI17_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | 357 | 4 | DEV_RTI17_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32000 | | 357 | 5 | DEV_RTI17_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 357 | 6 | DEV_RTI17_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0 | CLK_STATE_READY | 0 | | 357 | 7 | DEV_RTI17_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1 | CLK_STATE_READY | 0 | | 357 | 8 | DEV_RTI17_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2 | CLK_STATE_READY | 0 | | 357 | 9 | DEV_RTI17_VBUSP_CLK | CLK_STATE_READY | 125000000 | | 358 | 0 | DEV_RTI18_RTI_CLK | CLK_STATE_READY | 24000000 | | 358 | 1 | DEV_RTI18_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 24000000 | | 358 | 2 | DEV_RTI18_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | CLK_STATE_READY | 32768 | | 358 | 3 | DEV_RTI18_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | 358 | 4 | DEV_RTI18_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32000 | | 358 | 5 | DEV_RTI18_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 358 | 6 | DEV_RTI18_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0 | CLK_STATE_READY | 0 | | 358 | 7 | DEV_RTI18_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1 | CLK_STATE_READY | 0 | | 358 | 8 | DEV_RTI18_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2 | CLK_STATE_READY | 0 | | 358 | 9 | DEV_RTI18_VBUSP_CLK | CLK_STATE_READY | 125000000 | | 359 | 0 | DEV_RTI19_RTI_CLK | CLK_STATE_READY | 24000000 | | 359 | 1 | DEV_RTI19_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 24000000 | | 359 | 2 | DEV_RTI19_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | CLK_STATE_READY | 32768 | | 359 | 3 | DEV_RTI19_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | 359 | 4 | DEV_RTI19_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32000 | | 359 | 5 | DEV_RTI19_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 359 | 6 | DEV_RTI19_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0 | CLK_STATE_READY | 0 | | 359 | 7 | DEV_RTI19_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1 | CLK_STATE_READY | 0 | | 359 | 8 | DEV_RTI19_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2 | CLK_STATE_READY | 0 | | 359 | 9 | DEV_RTI19_VBUSP_CLK | CLK_STATE_READY | 125000000 | | 350 | 0 | DEV_RTI2_RTI_CLK | CLK_STATE_READY | 32000 | | 350 | 1 | DEV_RTI2_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 24000000 | | 350 | 2 | DEV_RTI2_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | CLK_STATE_READY | 32768 | | 350 | 3 | DEV_RTI2_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | 350 | 4 | DEV_RTI2_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32000 | | 350 | 5 | DEV_RTI2_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 350 | 6 | DEV_RTI2_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0 | CLK_STATE_READY | 0 | | 350 | 7 | DEV_RTI2_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1 | CLK_STATE_READY | 0 | | 350 | 8 | DEV_RTI2_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2 | CLK_STATE_READY | 0 | | 350 | 9 | DEV_RTI2_VBUSP_CLK | CLK_STATE_READY | 125000000 | | 361 | 0 | DEV_RTI28_RTI_CLK | CLK_STATE_READY | 24000000 | | 361 | 1 | DEV_RTI28_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 24000000 | | 361 | 2 | DEV_RTI28_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | CLK_STATE_READY | 32768 | | 361 | 3 | DEV_RTI28_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | 361 | 4 | DEV_RTI28_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32000 | | 361 | 5 | DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 361 | 6 | DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0 | CLK_STATE_READY | 0 | | 361 | 7 | DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1 | CLK_STATE_READY | 0 | | 361 | 8 | DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2 | CLK_STATE_READY | 0 | | 361 | 9 | DEV_RTI28_VBUSP_CLK | CLK_STATE_READY | 125000000 | | 362 | 0 | DEV_RTI29_RTI_CLK | CLK_STATE_READY | 24000000 | | 362 | 1 | DEV_RTI29_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 24000000 | | 362 | 2 | DEV_RTI29_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | CLK_STATE_READY | 32768 | | 362 | 3 | DEV_RTI29_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | 362 | 4 | DEV_RTI29_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32000 | | 362 | 5 | DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 362 | 6 | DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0 | CLK_STATE_READY | 0 | | 362 | 7 | DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1 | CLK_STATE_READY | 0 | | 362 | 8 | DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2 | CLK_STATE_READY | 0 | | 362 | 9 | DEV_RTI29_VBUSP_CLK | CLK_STATE_READY | 125000000 | | 351 | 0 | DEV_RTI3_RTI_CLK | CLK_STATE_READY | 32000 | | 351 | 1 | DEV_RTI3_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 24000000 | | 351 | 2 | DEV_RTI3_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | CLK_STATE_READY | 32768 | | 351 | 3 | DEV_RTI3_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | 351 | 4 | DEV_RTI3_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32000 | | 351 | 5 | DEV_RTI3_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 351 | 6 | DEV_RTI3_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0 | CLK_STATE_READY | 0 | | 351 | 7 | DEV_RTI3_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1 | CLK_STATE_READY | 0 | | 351 | 8 | DEV_RTI3_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2 | CLK_STATE_READY | 0 | | 351 | 9 | DEV_RTI3_VBUSP_CLK | CLK_STATE_READY | 125000000 | | 363 | 0 | DEV_RTI30_RTI_CLK | CLK_STATE_READY | 24000000 | | 363 | 1 | DEV_RTI30_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 24000000 | | 363 | 2 | DEV_RTI30_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | CLK_STATE_READY | 32768 | | 363 | 3 | DEV_RTI30_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | 363 | 4 | DEV_RTI30_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32000 | | 363 | 5 | DEV_RTI30_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 363 | 6 | DEV_RTI30_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0 | CLK_STATE_READY | 0 | | 363 | 7 | DEV_RTI30_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1 | CLK_STATE_READY | 0 | | 363 | 8 | DEV_RTI30_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2 | CLK_STATE_READY | 0 | | 363 | 9 | DEV_RTI30_VBUSP_CLK | CLK_STATE_READY | 125000000 | | 364 | 0 | DEV_RTI31_RTI_CLK | CLK_STATE_READY | 24000000 | | 364 | 1 | DEV_RTI31_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 24000000 | | 364 | 2 | DEV_RTI31_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | CLK_STATE_READY | 32768 | | 364 | 3 | DEV_RTI31_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | 364 | 4 | DEV_RTI31_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32000 | | 364 | 5 | DEV_RTI31_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 364 | 6 | DEV_RTI31_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0 | CLK_STATE_READY | 0 | | 364 | 7 | DEV_RTI31_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1 | CLK_STATE_READY | 0 | | 364 | 8 | DEV_RTI31_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2 | CLK_STATE_READY | 0 | | 364 | 9 | DEV_RTI31_VBUSP_CLK | CLK_STATE_READY | 125000000 | | 365 | 0 | DEV_RTI32_RTI_CLK | CLK_STATE_READY | 24000000 | | 365 | 1 | DEV_RTI32_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 24000000 | | 365 | 2 | DEV_RTI32_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | CLK_STATE_READY | 32768 | | 365 | 3 | DEV_RTI32_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | 365 | 4 | DEV_RTI32_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32000 | | 365 | 5 | DEV_RTI32_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 365 | 6 | DEV_RTI32_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0 | CLK_STATE_READY | 0 | | 365 | 7 | DEV_RTI32_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1 | CLK_STATE_READY | 0 | | 365 | 8 | DEV_RTI32_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2 | CLK_STATE_READY | 0 | | 365 | 9 | DEV_RTI32_VBUSP_CLK | CLK_STATE_READY | 125000000 | | 366 | 0 | DEV_RTI33_RTI_CLK | CLK_STATE_READY | 24000000 | | 366 | 1 | DEV_RTI33_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 24000000 | | 366 | 2 | DEV_RTI33_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | CLK_STATE_READY | 32768 | | 366 | 3 | DEV_RTI33_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | 366 | 4 | DEV_RTI33_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32000 | | 366 | 5 | DEV_RTI33_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 366 | 6 | DEV_RTI33_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0 | CLK_STATE_READY | 0 | | 366 | 7 | DEV_RTI33_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1 | CLK_STATE_READY | 0 | | 366 | 8 | DEV_RTI33_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2 | CLK_STATE_READY | 0 | | 366 | 9 | DEV_RTI33_VBUSP_CLK | CLK_STATE_READY | 125000000 | | 352 | 0 | DEV_RTI4_RTI_CLK | CLK_STATE_READY | 32000 | | 352 | 1 | DEV_RTI4_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 24000000 | | 352 | 2 | DEV_RTI4_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | CLK_STATE_READY | 32768 | | 352 | 3 | DEV_RTI4_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | 352 | 4 | DEV_RTI4_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32000 | | 352 | 5 | DEV_RTI4_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 352 | 6 | DEV_RTI4_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0 | CLK_STATE_READY | 0 | | 352 | 7 | DEV_RTI4_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1 | CLK_STATE_READY | 0 | | 352 | 8 | DEV_RTI4_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2 | CLK_STATE_READY | 0 | | 352 | 9 | DEV_RTI4_VBUSP_CLK | CLK_STATE_READY | 125000000 | | 353 | 0 | DEV_RTI5_RTI_CLK | CLK_STATE_READY | 32000 | | 353 | 1 | DEV_RTI5_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 24000000 | | 353 | 2 | DEV_RTI5_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | CLK_STATE_READY | 32768 | | 353 | 3 | DEV_RTI5_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | 353 | 4 | DEV_RTI5_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32000 | | 353 | 5 | DEV_RTI5_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 353 | 6 | DEV_RTI5_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0 | CLK_STATE_READY | 0 | | 353 | 7 | DEV_RTI5_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1 | CLK_STATE_READY | 0 | | 353 | 8 | DEV_RTI5_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2 | CLK_STATE_READY | 0 | | 353 | 9 | DEV_RTI5_VBUSP_CLK | CLK_STATE_READY | 125000000 | | 354 | 0 | DEV_RTI6_RTI_CLK | CLK_STATE_READY | 32000 | | 354 | 1 | DEV_RTI6_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 24000000 | | 354 | 2 | DEV_RTI6_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | CLK_STATE_READY | 32768 | | 354 | 3 | DEV_RTI6_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | 354 | 4 | DEV_RTI6_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32000 | | 354 | 5 | DEV_RTI6_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 354 | 6 | DEV_RTI6_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0 | CLK_STATE_READY | 0 | | 354 | 7 | DEV_RTI6_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1 | CLK_STATE_READY | 0 | | 354 | 8 | DEV_RTI6_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2 | CLK_STATE_READY | 0 | | 354 | 9 | DEV_RTI6_VBUSP_CLK | CLK_STATE_READY | 125000000 | | 355 | 0 | DEV_RTI7_RTI_CLK | CLK_STATE_READY | 32000 | | 355 | 1 | DEV_RTI7_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 24000000 | | 355 | 2 | DEV_RTI7_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | CLK_STATE_READY | 32768 | | 355 | 3 | DEV_RTI7_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | 355 | 4 | DEV_RTI7_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32000 | | 355 | 5 | DEV_RTI7_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 355 | 6 | DEV_RTI7_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0 | CLK_STATE_READY | 0 | | 355 | 7 | DEV_RTI7_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1 | CLK_STATE_READY | 0 | | 355 | 8 | DEV_RTI7_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2 | CLK_STATE_READY | 0 | | 355 | 9 | DEV_RTI7_VBUSP_CLK | CLK_STATE_READY | 125000000 | | 8 | 0 | DEV_SA2_CPSW_PSILSS0_MAIN_2_CLK | CLK_STATE_READY | 250000000 | | 8 | 1 | DEV_SA2_CPSW_PSILSS0_MAIN_CLK | CLK_STATE_READY | 500000000 | | 369 | 0 | DEV_SA2_UL0_PKA_IN_CLK | CLK_STATE_READY | 400000000 | | 369 | 1 | DEV_SA2_UL0_X1_CLK | CLK_STATE_READY | 125000000 | | 369 | 2 | DEV_SA2_UL0_X2_CLK | CLK_STATE_READY | 250000000 | | 404 | 2 | DEV_SERDES_10G0_CLK | CLK_STATE_READY | 125000000 | | 404 | 3 | DEV_SERDES_10G0_CMN_REFCLK_M | CLK_STATE_READY | 0 | | 404 | 3 | DEV_SERDES_10G0_CMN_REFCLK_M | CLK_STATE_READY | 0 | | 404 | 4 | DEV_SERDES_10G0_CMN_REFCLK_P | CLK_STATE_READY | 0 | | 404 | 4 | DEV_SERDES_10G0_CMN_REFCLK_P | CLK_STATE_READY | 0 | | 404 | 5 | DEV_SERDES_10G0_CORE_REF1_CLK | CLK_STATE_READY | 156250000 | | 404 | 6 | DEV_SERDES_10G0_CORE_REF_CLK | CLK_STATE_READY | 100000000 | | 404 | 7 | DEV_SERDES_10G0_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 24000000 | | 404 | 8 | DEV_SERDES_10G0_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 404 | 9 | DEV_SERDES_10G0_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK | CLK_STATE_READY | 156250000 | | 404 | 10 | DEV_SERDES_10G0_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK | CLK_STATE_READY | 100000000 | | 404 | 15 | DEV_SERDES_10G0_IP1_LN0_TXCLK | CLK_STATE_READY | 0 | | 404 | 21 | DEV_SERDES_10G0_IP1_LN1_TXCLK | CLK_STATE_READY | 0 | | 404 | 24 | DEV_SERDES_10G0_IP1_LN2_REFCLK | CLK_STATE_READY | 0 | | 404 | 25 | DEV_SERDES_10G0_IP1_LN2_RXCLK | CLK_STATE_READY | 0 | | 404 | 26 | DEV_SERDES_10G0_IP1_LN2_RXFCLK | CLK_STATE_READY | 0 | | 404 | 27 | DEV_SERDES_10G0_IP1_LN2_TXCLK | CLK_STATE_READY | 0 | | 404 | 28 | DEV_SERDES_10G0_IP1_LN2_TXFCLK | CLK_STATE_READY | 0 | | 404 | 29 | DEV_SERDES_10G0_IP1_LN2_TXMCLK | CLK_STATE_READY | 0 | | 404 | 30 | DEV_SERDES_10G0_IP1_LN3_REFCLK | CLK_STATE_READY | 0 | | 404 | 31 | DEV_SERDES_10G0_IP1_LN3_RXCLK | CLK_STATE_READY | 0 | | 404 | 32 | DEV_SERDES_10G0_IP1_LN3_RXFCLK | CLK_STATE_READY | 0 | | 404 | 33 | DEV_SERDES_10G0_IP1_LN3_TXCLK | CLK_STATE_READY | 0 | | 404 | 34 | DEV_SERDES_10G0_IP1_LN3_TXFCLK | CLK_STATE_READY | 0 | | 404 | 35 | DEV_SERDES_10G0_IP1_LN3_TXMCLK | CLK_STATE_READY | 0 | | 404 | 36 | DEV_SERDES_10G0_IP2_LN0_REFCLK | CLK_STATE_READY | 0 | | 404 | 37 | DEV_SERDES_10G0_IP2_LN0_RXCLK | CLK_STATE_READY | 0 | | 404 | 38 | DEV_SERDES_10G0_IP2_LN0_RXFCLK | CLK_STATE_READY | 0 | | 404 | 39 | DEV_SERDES_10G0_IP2_LN0_TXCLK | CLK_STATE_READY | 0 | | 404 | 40 | DEV_SERDES_10G0_IP2_LN0_TXFCLK | CLK_STATE_READY | 0 | | 404 | 41 | DEV_SERDES_10G0_IP2_LN0_TXMCLK | CLK_STATE_READY | 0 | | 404 | 42 | DEV_SERDES_10G0_IP2_LN1_REFCLK | CLK_STATE_READY | 0 | | 404 | 43 | DEV_SERDES_10G0_IP2_LN1_RXCLK | CLK_STATE_READY | 0 | | 404 | 44 | DEV_SERDES_10G0_IP2_LN1_RXFCLK | CLK_STATE_READY | 0 | | 404 | 45 | DEV_SERDES_10G0_IP2_LN1_TXCLK | CLK_STATE_READY | 0 | | 404 | 46 | DEV_SERDES_10G0_IP2_LN1_TXFCLK | CLK_STATE_READY | 0 | | 404 | 47 | DEV_SERDES_10G0_IP2_LN1_TXMCLK | CLK_STATE_READY | 0 | | 404 | 48 | DEV_SERDES_10G0_IP2_LN2_REFCLK | CLK_STATE_READY | 0 | | 404 | 49 | DEV_SERDES_10G0_IP2_LN2_RXCLK | CLK_STATE_READY | 0 | | 404 | 50 | DEV_SERDES_10G0_IP2_LN2_RXFCLK | CLK_STATE_READY | 0 | | 404 | 51 | DEV_SERDES_10G0_IP2_LN2_TXCLK | CLK_STATE_READY | 0 | | 404 | 52 | DEV_SERDES_10G0_IP2_LN2_TXFCLK | CLK_STATE_READY | 0 | | 404 | 53 | DEV_SERDES_10G0_IP2_LN2_TXMCLK | CLK_STATE_READY | 0 | | 404 | 54 | DEV_SERDES_10G0_IP2_LN3_REFCLK | CLK_STATE_READY | 0 | | 404 | 55 | DEV_SERDES_10G0_IP2_LN3_RXCLK | CLK_STATE_READY | 0 | | 404 | 56 | DEV_SERDES_10G0_IP2_LN3_RXFCLK | CLK_STATE_READY | 0 | | 404 | 57 | DEV_SERDES_10G0_IP2_LN3_TXCLK | CLK_STATE_READY | 0 | | 404 | 58 | DEV_SERDES_10G0_IP2_LN3_TXFCLK | CLK_STATE_READY | 0 | | 404 | 59 | DEV_SERDES_10G0_IP2_LN3_TXMCLK | CLK_STATE_READY | 0 | | 404 | 78 | DEV_SERDES_10G0_IP3_LN3_REFCLK | CLK_STATE_READY | 0 | | 404 | 79 | DEV_SERDES_10G0_IP3_LN3_RXCLK | CLK_STATE_READY | 0 | | 404 | 80 | DEV_SERDES_10G0_IP3_LN3_RXFCLK | CLK_STATE_READY | 0 | | 404 | 81 | DEV_SERDES_10G0_IP3_LN3_TXCLK | CLK_STATE_READY | 0 | | 404 | 82 | DEV_SERDES_10G0_IP3_LN3_TXFCLK | CLK_STATE_READY | 0 | | 404 | 83 | DEV_SERDES_10G0_IP3_LN3_TXMCLK | CLK_STATE_READY | 0 | | 404 | 84 | DEV_SERDES_10G0_IP4_LN0_REFCLK | CLK_STATE_READY | 0 | | 404 | 85 | DEV_SERDES_10G0_IP4_LN0_RXCLK | CLK_STATE_READY | 0 | | 404 | 86 | DEV_SERDES_10G0_IP4_LN0_RXFCLK | CLK_STATE_READY | 0 | | 404 | 87 | DEV_SERDES_10G0_IP4_LN0_TXCLK | CLK_STATE_READY | 0 | | 404 | 88 | DEV_SERDES_10G0_IP4_LN0_TXFCLK | CLK_STATE_READY | 0 | | 404 | 89 | DEV_SERDES_10G0_IP4_LN0_TXMCLK | CLK_STATE_READY | 0 | | 404 | 90 | DEV_SERDES_10G0_IP4_LN1_REFCLK | CLK_STATE_READY | 0 | | 404 | 91 | DEV_SERDES_10G0_IP4_LN1_RXCLK | CLK_STATE_READY | 0 | | 404 | 92 | DEV_SERDES_10G0_IP4_LN1_RXFCLK | CLK_STATE_READY | 0 | | 404 | 93 | DEV_SERDES_10G0_IP4_LN1_TXCLK | CLK_STATE_READY | 0 | | 404 | 94 | DEV_SERDES_10G0_IP4_LN1_TXFCLK | CLK_STATE_READY | 0 | | 404 | 95 | DEV_SERDES_10G0_IP4_LN1_TXMCLK | CLK_STATE_READY | 0 | | 404 | 96 | DEV_SERDES_10G0_IP4_LN2_REFCLK | CLK_STATE_READY | 0 | | 404 | 97 | DEV_SERDES_10G0_IP4_LN2_RXCLK | CLK_STATE_READY | 0 | | 404 | 98 | DEV_SERDES_10G0_IP4_LN2_RXFCLK | CLK_STATE_READY | 0 | | 404 | 99 | DEV_SERDES_10G0_IP4_LN2_TXCLK | CLK_STATE_READY | 0 | | 404 | 100 | DEV_SERDES_10G0_IP4_LN2_TXFCLK | CLK_STATE_READY | 0 | | 404 | 101 | DEV_SERDES_10G0_IP4_LN2_TXMCLK | CLK_STATE_READY | 0 | | 404 | 102 | DEV_SERDES_10G0_IP4_LN3_REFCLK | CLK_STATE_READY | 0 | | 404 | 103 | DEV_SERDES_10G0_IP4_LN3_RXCLK | CLK_STATE_READY | 0 | | 404 | 104 | DEV_SERDES_10G0_IP4_LN3_RXFCLK | CLK_STATE_READY | 0 | | 404 | 105 | DEV_SERDES_10G0_IP4_LN3_TXCLK | CLK_STATE_READY | 0 | | 404 | 106 | DEV_SERDES_10G0_IP4_LN3_TXFCLK | CLK_STATE_READY | 0 | | 404 | 107 | DEV_SERDES_10G0_IP4_LN3_TXMCLK | CLK_STATE_READY | 0 | | 404 | 124 | DEV_SERDES_10G0_REF_DER_OUT_CLK | CLK_STATE_READY | 0 | | 404 | 125 | DEV_SERDES_10G0_REF_OUT_CLK | CLK_STATE_READY | 0 | | 404 | 129 | DEV_SERDES_10G0_TAP_TCK | CLK_STATE_READY | 0 | | 405 | 2 | DEV_SERDES_10G1_CLK | CLK_STATE_READY | 125000000 | | 405 | 3 | DEV_SERDES_10G1_CMN_REFCLK_M | CLK_STATE_READY | 0 | | 405 | 3 | DEV_SERDES_10G1_CMN_REFCLK_M | CLK_STATE_READY | 0 | | 405 | 4 | DEV_SERDES_10G1_CMN_REFCLK_P | CLK_STATE_READY | 0 | | 405 | 4 | DEV_SERDES_10G1_CMN_REFCLK_P | CLK_STATE_READY | 0 | | 405 | 5 | DEV_SERDES_10G1_CORE_REF1_CLK | CLK_STATE_READY | 156250000 | | 405 | 6 | DEV_SERDES_10G1_CORE_REF_CLK | CLK_STATE_READY | 100000000 | | 405 | 7 | DEV_SERDES_10G1_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 24000000 | | 405 | 8 | DEV_SERDES_10G1_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 405 | 9 | DEV_SERDES_10G1_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK | CLK_STATE_READY | 156250000 | | 405 | 10 | DEV_SERDES_10G1_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK | CLK_STATE_READY | 100000000 | | 405 | 12 | DEV_SERDES_10G1_IP1_LN0_REFCLK | CLK_STATE_READY | 0 | | 405 | 13 | DEV_SERDES_10G1_IP1_LN0_RXCLK | CLK_STATE_READY | 0 | | 405 | 14 | DEV_SERDES_10G1_IP1_LN0_RXFCLK | CLK_STATE_READY | 0 | | 405 | 15 | DEV_SERDES_10G1_IP1_LN0_TXCLK | CLK_STATE_READY | 0 | | 405 | 16 | DEV_SERDES_10G1_IP1_LN0_TXFCLK | CLK_STATE_READY | 0 | | 405 | 17 | DEV_SERDES_10G1_IP1_LN0_TXMCLK | CLK_STATE_READY | 0 | | 405 | 18 | DEV_SERDES_10G1_IP1_LN1_REFCLK | CLK_STATE_READY | 0 | | 405 | 19 | DEV_SERDES_10G1_IP1_LN1_RXCLK | CLK_STATE_READY | 0 | | 405 | 20 | DEV_SERDES_10G1_IP1_LN1_RXFCLK | CLK_STATE_READY | 0 | | 405 | 21 | DEV_SERDES_10G1_IP1_LN1_TXCLK | CLK_STATE_READY | 0 | | 405 | 22 | DEV_SERDES_10G1_IP1_LN1_TXFCLK | CLK_STATE_READY | 0 | | 405 | 23 | DEV_SERDES_10G1_IP1_LN1_TXMCLK | CLK_STATE_READY | 0 | | 405 | 24 | DEV_SERDES_10G1_IP1_LN2_REFCLK | CLK_STATE_READY | 0 | | 405 | 25 | DEV_SERDES_10G1_IP1_LN2_RXCLK | CLK_STATE_READY | 0 | | 405 | 26 | DEV_SERDES_10G1_IP1_LN2_RXFCLK | CLK_STATE_READY | 0 | | 405 | 27 | DEV_SERDES_10G1_IP1_LN2_TXCLK | CLK_STATE_READY | 0 | | 405 | 28 | DEV_SERDES_10G1_IP1_LN2_TXFCLK | CLK_STATE_READY | 0 | | 405 | 29 | DEV_SERDES_10G1_IP1_LN2_TXMCLK | CLK_STATE_READY | 0 | | 405 | 30 | DEV_SERDES_10G1_IP1_LN3_REFCLK | CLK_STATE_READY | 0 | | 405 | 31 | DEV_SERDES_10G1_IP1_LN3_RXCLK | CLK_STATE_READY | 0 | | 405 | 32 | DEV_SERDES_10G1_IP1_LN3_RXFCLK | CLK_STATE_READY | 0 | | 405 | 33 | DEV_SERDES_10G1_IP1_LN3_TXCLK | CLK_STATE_READY | 0 | | 405 | 34 | DEV_SERDES_10G1_IP1_LN3_TXFCLK | CLK_STATE_READY | 0 | | 405 | 35 | DEV_SERDES_10G1_IP1_LN3_TXMCLK | CLK_STATE_READY | 0 | | 405 | 36 | DEV_SERDES_10G1_IP2_LN0_REFCLK | CLK_STATE_READY | 0 | | 405 | 37 | DEV_SERDES_10G1_IP2_LN0_RXCLK | CLK_STATE_READY | 0 | | 405 | 38 | DEV_SERDES_10G1_IP2_LN0_RXFCLK | CLK_STATE_READY | 0 | | 405 | 39 | DEV_SERDES_10G1_IP2_LN0_TXCLK | CLK_STATE_READY | 0 | | 405 | 40 | DEV_SERDES_10G1_IP2_LN0_TXFCLK | CLK_STATE_READY | 0 | | 405 | 41 | DEV_SERDES_10G1_IP2_LN0_TXMCLK | CLK_STATE_READY | 0 | | 405 | 42 | DEV_SERDES_10G1_IP2_LN1_REFCLK | CLK_STATE_READY | 0 | | 405 | 43 | DEV_SERDES_10G1_IP2_LN1_RXCLK | CLK_STATE_READY | 0 | | 405 | 44 | DEV_SERDES_10G1_IP2_LN1_RXFCLK | CLK_STATE_READY | 0 | | 405 | 45 | DEV_SERDES_10G1_IP2_LN1_TXCLK | CLK_STATE_READY | 0 | | 405 | 46 | DEV_SERDES_10G1_IP2_LN1_TXFCLK | CLK_STATE_READY | 0 | | 405 | 47 | DEV_SERDES_10G1_IP2_LN1_TXMCLK | CLK_STATE_READY | 0 | | 405 | 48 | DEV_SERDES_10G1_IP2_LN2_REFCLK | CLK_STATE_READY | 0 | | 405 | 49 | DEV_SERDES_10G1_IP2_LN2_RXCLK | CLK_STATE_READY | 0 | | 405 | 50 | DEV_SERDES_10G1_IP2_LN2_RXFCLK | CLK_STATE_READY | 0 | | 405 | 51 | DEV_SERDES_10G1_IP2_LN2_TXCLK | CLK_STATE_READY | 0 | | 405 | 52 | DEV_SERDES_10G1_IP2_LN2_TXFCLK | CLK_STATE_READY | 0 | | 405 | 53 | DEV_SERDES_10G1_IP2_LN2_TXMCLK | CLK_STATE_READY | 0 | | 405 | 54 | DEV_SERDES_10G1_IP2_LN3_REFCLK | CLK_STATE_READY | 0 | | 405 | 55 | DEV_SERDES_10G1_IP2_LN3_RXCLK | CLK_STATE_READY | 0 | | 405 | 56 | DEV_SERDES_10G1_IP2_LN3_RXFCLK | CLK_STATE_READY | 0 | | 405 | 57 | DEV_SERDES_10G1_IP2_LN3_TXCLK | CLK_STATE_READY | 0 | | 405 | 58 | DEV_SERDES_10G1_IP2_LN3_TXFCLK | CLK_STATE_READY | 0 | | 405 | 59 | DEV_SERDES_10G1_IP2_LN3_TXMCLK | CLK_STATE_READY | 0 | | 405 | 72 | DEV_SERDES_10G1_IP3_LN2_REFCLK | CLK_STATE_READY | 0 | | 405 | 73 | DEV_SERDES_10G1_IP3_LN2_RXCLK | CLK_STATE_READY | 0 | | 405 | 74 | DEV_SERDES_10G1_IP3_LN2_RXFCLK | CLK_STATE_READY | 0 | | 405 | 75 | DEV_SERDES_10G1_IP3_LN2_TXCLK | CLK_STATE_READY | 0 | | 405 | 76 | DEV_SERDES_10G1_IP3_LN2_TXFCLK | CLK_STATE_READY | 0 | | 405 | 77 | DEV_SERDES_10G1_IP3_LN2_TXMCLK | CLK_STATE_READY | 0 | | 405 | 78 | DEV_SERDES_10G1_IP3_LN3_REFCLK | CLK_STATE_READY | 0 | | 405 | 79 | DEV_SERDES_10G1_IP3_LN3_RXCLK | CLK_STATE_READY | 0 | | 405 | 80 | DEV_SERDES_10G1_IP3_LN3_RXFCLK | CLK_STATE_READY | 0 | | 405 | 81 | DEV_SERDES_10G1_IP3_LN3_TXCLK | CLK_STATE_READY | 0 | | 405 | 82 | DEV_SERDES_10G1_IP3_LN3_TXFCLK | CLK_STATE_READY | 0 | | 405 | 83 | DEV_SERDES_10G1_IP3_LN3_TXMCLK | CLK_STATE_READY | 0 | | 405 | 124 | DEV_SERDES_10G1_REF_DER_OUT_CLK | CLK_STATE_READY | 0 | | 405 | 125 | DEV_SERDES_10G1_REF_OUT_CLK | CLK_STATE_READY | 0 | | 405 | 129 | DEV_SERDES_10G1_TAP_TCK | CLK_STATE_READY | 0 | | 406 | 2 | DEV_SERDES_10G2_CLK | CLK_STATE_READY | 125000000 | | 406 | 3 | DEV_SERDES_10G2_CMN_REFCLK_M | CLK_STATE_READY | 0 | | 406 | 3 | DEV_SERDES_10G2_CMN_REFCLK_M | CLK_STATE_READY | 0 | | 406 | 4 | DEV_SERDES_10G2_CMN_REFCLK_P | CLK_STATE_READY | 0 | | 406 | 5 | DEV_SERDES_10G2_CORE_REF1_CLK | CLK_STATE_READY | 156250000 | | 406 | 6 | DEV_SERDES_10G2_CORE_REF_CLK | CLK_STATE_READY | 24000000 | | 406 | 7 | DEV_SERDES_10G2_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 24000000 | | 406 | 8 | DEV_SERDES_10G2_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 406 | 9 | DEV_SERDES_10G2_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK | CLK_STATE_READY | 156250000 | | 406 | 10 | DEV_SERDES_10G2_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK | CLK_STATE_READY | 100000000 | | 406 | 12 | DEV_SERDES_10G2_IP1_LN0_REFCLK | CLK_STATE_READY | 0 | | 406 | 13 | DEV_SERDES_10G2_IP1_LN0_RXCLK | CLK_STATE_READY | 0 | | 406 | 14 | DEV_SERDES_10G2_IP1_LN0_RXFCLK | CLK_STATE_READY | 0 | | 406 | 15 | DEV_SERDES_10G2_IP1_LN0_TXCLK | CLK_STATE_READY | 0 | | 406 | 16 | DEV_SERDES_10G2_IP1_LN0_TXFCLK | CLK_STATE_READY | 0 | | 406 | 17 | DEV_SERDES_10G2_IP1_LN0_TXMCLK | CLK_STATE_READY | 0 | | 406 | 18 | DEV_SERDES_10G2_IP1_LN1_REFCLK | CLK_STATE_READY | 0 | | 406 | 19 | DEV_SERDES_10G2_IP1_LN1_RXCLK | CLK_STATE_READY | 0 | | 406 | 20 | DEV_SERDES_10G2_IP1_LN1_RXFCLK | CLK_STATE_READY | 0 | | 406 | 21 | DEV_SERDES_10G2_IP1_LN1_TXCLK | CLK_STATE_READY | 0 | | 406 | 22 | DEV_SERDES_10G2_IP1_LN1_TXFCLK | CLK_STATE_READY | 0 | | 406 | 23 | DEV_SERDES_10G2_IP1_LN1_TXMCLK | CLK_STATE_READY | 0 | | 406 | 24 | DEV_SERDES_10G2_IP1_LN2_REFCLK | CLK_STATE_READY | 0 | | 406 | 25 | DEV_SERDES_10G2_IP1_LN2_RXCLK | CLK_STATE_READY | 0 | | 406 | 26 | DEV_SERDES_10G2_IP1_LN2_RXFCLK | CLK_STATE_READY | 0 | | 406 | 27 | DEV_SERDES_10G2_IP1_LN2_TXCLK | CLK_STATE_READY | 0 | | 406 | 28 | DEV_SERDES_10G2_IP1_LN2_TXFCLK | CLK_STATE_READY | 0 | | 406 | 29 | DEV_SERDES_10G2_IP1_LN2_TXMCLK | CLK_STATE_READY | 0 | | 406 | 30 | DEV_SERDES_10G2_IP1_LN3_REFCLK | CLK_STATE_READY | 0 | | 406 | 31 | DEV_SERDES_10G2_IP1_LN3_RXCLK | CLK_STATE_READY | 0 | | 406 | 32 | DEV_SERDES_10G2_IP1_LN3_RXFCLK | CLK_STATE_READY | 0 | | 406 | 33 | DEV_SERDES_10G2_IP1_LN3_TXCLK | CLK_STATE_READY | 0 | | 406 | 34 | DEV_SERDES_10G2_IP1_LN3_TXFCLK | CLK_STATE_READY | 0 | | 406 | 35 | DEV_SERDES_10G2_IP1_LN3_TXMCLK | CLK_STATE_READY | 0 | | 406 | 48 | DEV_SERDES_10G2_IP2_LN2_REFCLK | CLK_STATE_READY | 0 | | 406 | 49 | DEV_SERDES_10G2_IP2_LN2_RXCLK | CLK_STATE_READY | 0 | | 406 | 50 | DEV_SERDES_10G2_IP2_LN2_RXFCLK | CLK_STATE_READY | 0 | | 406 | 51 | DEV_SERDES_10G2_IP2_LN2_TXCLK | CLK_STATE_READY | 0 | | 406 | 52 | DEV_SERDES_10G2_IP2_LN2_TXFCLK | CLK_STATE_READY | 0 | | 406 | 53 | DEV_SERDES_10G2_IP2_LN2_TXMCLK | CLK_STATE_READY | 0 | | 406 | 54 | DEV_SERDES_10G2_IP2_LN3_REFCLK | CLK_STATE_READY | 0 | | 406 | 55 | DEV_SERDES_10G2_IP2_LN3_RXCLK | CLK_STATE_READY | 0 | | 406 | 56 | DEV_SERDES_10G2_IP2_LN3_RXFCLK | CLK_STATE_READY | 0 | | 406 | 57 | DEV_SERDES_10G2_IP2_LN3_TXCLK | CLK_STATE_READY | 0 | | 406 | 58 | DEV_SERDES_10G2_IP2_LN3_TXFCLK | CLK_STATE_READY | 0 | | 406 | 59 | DEV_SERDES_10G2_IP2_LN3_TXMCLK | CLK_STATE_READY | 0 | | 406 | 129 | DEV_SERDES_10G2_TAP_TCK | CLK_STATE_READY | 0 | | 407 | 2 | DEV_SERDES_10G4_CLK | CLK_STATE_READY | 125000000 | | 407 | 3 | DEV_SERDES_10G4_CMN_REFCLK_M | CLK_STATE_READY | 0 | | 407 | 3 | DEV_SERDES_10G4_CMN_REFCLK_M | CLK_STATE_READY | 0 | | 407 | 4 | DEV_SERDES_10G4_CMN_REFCLK_P | CLK_STATE_READY | 0 | | 407 | 4 | DEV_SERDES_10G4_CMN_REFCLK_P | CLK_STATE_READY | 0 | | 407 | 5 | DEV_SERDES_10G4_CORE_REF1_CLK | CLK_STATE_READY | 156250000 | | 407 | 6 | DEV_SERDES_10G4_CORE_REF_CLK | CLK_STATE_READY | 100000000 | | 407 | 7 | DEV_SERDES_10G4_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 24000000 | | 407 | 8 | DEV_SERDES_10G4_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 407 | 9 | DEV_SERDES_10G4_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK | CLK_STATE_READY | 156250000 | | 407 | 10 | DEV_SERDES_10G4_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK | CLK_STATE_READY | 100000000 | | 407 | 12 | DEV_SERDES_10G4_IP1_LN0_REFCLK | CLK_STATE_READY | 0 | | 407 | 13 | DEV_SERDES_10G4_IP1_LN0_RXCLK | CLK_STATE_READY | 0 | | 407 | 14 | DEV_SERDES_10G4_IP1_LN0_RXFCLK | CLK_STATE_READY | 0 | | 407 | 15 | DEV_SERDES_10G4_IP1_LN0_TXCLK | CLK_STATE_READY | 0 | | 407 | 16 | DEV_SERDES_10G4_IP1_LN0_TXFCLK | CLK_STATE_READY | 0 | | 407 | 17 | DEV_SERDES_10G4_IP1_LN0_TXMCLK | CLK_STATE_READY | 0 | | 407 | 18 | DEV_SERDES_10G4_IP1_LN1_REFCLK | CLK_STATE_READY | 0 | | 407 | 19 | DEV_SERDES_10G4_IP1_LN1_RXCLK | CLK_STATE_READY | 0 | | 407 | 20 | DEV_SERDES_10G4_IP1_LN1_RXFCLK | CLK_STATE_READY | 0 | | 407 | 21 | DEV_SERDES_10G4_IP1_LN1_TXCLK | CLK_STATE_READY | 0 | | 407 | 22 | DEV_SERDES_10G4_IP1_LN1_TXFCLK | CLK_STATE_READY | 0 | | 407 | 23 | DEV_SERDES_10G4_IP1_LN1_TXMCLK | CLK_STATE_READY | 0 | | 407 | 24 | DEV_SERDES_10G4_IP1_LN2_REFCLK | CLK_STATE_READY | 0 | | 407 | 25 | DEV_SERDES_10G4_IP1_LN2_RXCLK | CLK_STATE_READY | 0 | | 407 | 26 | DEV_SERDES_10G4_IP1_LN2_RXFCLK | CLK_STATE_READY | 0 | | 407 | 27 | DEV_SERDES_10G4_IP1_LN2_TXCLK | CLK_STATE_READY | 0 | | 407 | 28 | DEV_SERDES_10G4_IP1_LN2_TXFCLK | CLK_STATE_READY | 0 | | 407 | 29 | DEV_SERDES_10G4_IP1_LN2_TXMCLK | CLK_STATE_READY | 0 | | 407 | 30 | DEV_SERDES_10G4_IP1_LN3_REFCLK | CLK_STATE_READY | 0 | | 407 | 31 | DEV_SERDES_10G4_IP1_LN3_RXCLK | CLK_STATE_READY | 0 | | 407 | 32 | DEV_SERDES_10G4_IP1_LN3_RXFCLK | CLK_STATE_READY | 0 | | 407 | 33 | DEV_SERDES_10G4_IP1_LN3_TXCLK | CLK_STATE_READY | 0 | | 407 | 34 | DEV_SERDES_10G4_IP1_LN3_TXFCLK | CLK_STATE_READY | 0 | | 407 | 35 | DEV_SERDES_10G4_IP1_LN3_TXMCLK | CLK_STATE_READY | 0 | | 407 | 36 | DEV_SERDES_10G4_IP2_LN0_REFCLK | CLK_STATE_READY | 0 | | 407 | 37 | DEV_SERDES_10G4_IP2_LN0_RXCLK | CLK_STATE_READY | 0 | | 407 | 38 | DEV_SERDES_10G4_IP2_LN0_RXFCLK | CLK_STATE_READY | 0 | | 407 | 39 | DEV_SERDES_10G4_IP2_LN0_TXCLK | CLK_STATE_READY | 0 | | 407 | 40 | DEV_SERDES_10G4_IP2_LN0_TXFCLK | CLK_STATE_READY | 0 | | 407 | 41 | DEV_SERDES_10G4_IP2_LN0_TXMCLK | CLK_STATE_READY | 0 | | 407 | 42 | DEV_SERDES_10G4_IP2_LN1_REFCLK | CLK_STATE_READY | 0 | | 407 | 43 | DEV_SERDES_10G4_IP2_LN1_RXCLK | CLK_STATE_READY | 0 | | 407 | 44 | DEV_SERDES_10G4_IP2_LN1_RXFCLK | CLK_STATE_READY | 0 | | 407 | 45 | DEV_SERDES_10G4_IP2_LN1_TXCLK | CLK_STATE_READY | 0 | | 407 | 46 | DEV_SERDES_10G4_IP2_LN1_TXFCLK | CLK_STATE_READY | 0 | | 407 | 47 | DEV_SERDES_10G4_IP2_LN1_TXMCLK | CLK_STATE_READY | 0 | | 407 | 48 | DEV_SERDES_10G4_IP2_LN2_REFCLK | CLK_STATE_READY | 0 | | 407 | 49 | DEV_SERDES_10G4_IP2_LN2_RXCLK | CLK_STATE_READY | 0 | | 407 | 50 | DEV_SERDES_10G4_IP2_LN2_RXFCLK | CLK_STATE_READY | 0 | | 407 | 51 | DEV_SERDES_10G4_IP2_LN2_TXCLK | CLK_STATE_READY | 0 | | 407 | 52 | DEV_SERDES_10G4_IP2_LN2_TXFCLK | CLK_STATE_READY | 0 | | 407 | 53 | DEV_SERDES_10G4_IP2_LN2_TXMCLK | CLK_STATE_READY | 0 | | 407 | 54 | DEV_SERDES_10G4_IP2_LN3_REFCLK | CLK_STATE_READY | 0 | | 407 | 55 | DEV_SERDES_10G4_IP2_LN3_RXCLK | CLK_STATE_READY | 0 | | 407 | 56 | DEV_SERDES_10G4_IP2_LN3_RXFCLK | CLK_STATE_READY | 0 | | 407 | 57 | DEV_SERDES_10G4_IP2_LN3_TXCLK | CLK_STATE_READY | 0 | | 407 | 58 | DEV_SERDES_10G4_IP2_LN3_TXFCLK | CLK_STATE_READY | 0 | | 407 | 59 | DEV_SERDES_10G4_IP2_LN3_TXMCLK | CLK_STATE_READY | 0 | | 407 | 78 | DEV_SERDES_10G4_IP3_LN3_REFCLK | CLK_STATE_READY | 0 | | 407 | 79 | DEV_SERDES_10G4_IP3_LN3_RXCLK | CLK_STATE_READY | 0 | | 407 | 80 | DEV_SERDES_10G4_IP3_LN3_RXFCLK | CLK_STATE_READY | 0 | | 407 | 81 | DEV_SERDES_10G4_IP3_LN3_TXCLK | CLK_STATE_READY | 0 | | 407 | 82 | DEV_SERDES_10G4_IP3_LN3_TXFCLK | CLK_STATE_READY | 0 | | 407 | 83 | DEV_SERDES_10G4_IP3_LN3_TXMCLK | CLK_STATE_READY | 0 | | 407 | 84 | DEV_SERDES_10G4_IP4_LN0_REFCLK | CLK_STATE_READY | 0 | | 407 | 85 | DEV_SERDES_10G4_IP4_LN0_RXCLK | CLK_STATE_READY | 0 | | 407 | 86 | DEV_SERDES_10G4_IP4_LN0_RXFCLK | CLK_STATE_READY | 0 | | 407 | 87 | DEV_SERDES_10G4_IP4_LN0_TXCLK | CLK_STATE_READY | 0 | | 407 | 88 | DEV_SERDES_10G4_IP4_LN0_TXFCLK | CLK_STATE_READY | 0 | | 407 | 89 | DEV_SERDES_10G4_IP4_LN0_TXMCLK | CLK_STATE_READY | 0 | | 407 | 90 | DEV_SERDES_10G4_IP4_LN1_REFCLK | CLK_STATE_READY | 0 | | 407 | 91 | DEV_SERDES_10G4_IP4_LN1_RXCLK | CLK_STATE_READY | 0 | | 407 | 92 | DEV_SERDES_10G4_IP4_LN1_RXFCLK | CLK_STATE_READY | 0 | | 407 | 93 | DEV_SERDES_10G4_IP4_LN1_TXCLK | CLK_STATE_READY | 0 | | 407 | 94 | DEV_SERDES_10G4_IP4_LN1_TXFCLK | CLK_STATE_READY | 0 | | 407 | 95 | DEV_SERDES_10G4_IP4_LN1_TXMCLK | CLK_STATE_READY | 0 | | 407 | 96 | DEV_SERDES_10G4_IP4_LN2_REFCLK | CLK_STATE_READY | 0 | | 407 | 97 | DEV_SERDES_10G4_IP4_LN2_RXCLK | CLK_STATE_READY | 0 | | 407 | 98 | DEV_SERDES_10G4_IP4_LN2_RXFCLK | CLK_STATE_READY | 0 | | 407 | 99 | DEV_SERDES_10G4_IP4_LN2_TXCLK | CLK_STATE_READY | 0 | | 407 | 100 | DEV_SERDES_10G4_IP4_LN2_TXFCLK | CLK_STATE_READY | 0 | | 407 | 101 | DEV_SERDES_10G4_IP4_LN2_TXMCLK | CLK_STATE_READY | 0 | | 407 | 102 | DEV_SERDES_10G4_IP4_LN3_REFCLK | CLK_STATE_READY | 0 | | 407 | 103 | DEV_SERDES_10G4_IP4_LN3_RXCLK | CLK_STATE_READY | 0 | | 407 | 104 | DEV_SERDES_10G4_IP4_LN3_RXFCLK | CLK_STATE_READY | 0 | | 407 | 105 | DEV_SERDES_10G4_IP4_LN3_TXCLK | CLK_STATE_READY | 0 | | 407 | 106 | DEV_SERDES_10G4_IP4_LN3_TXFCLK | CLK_STATE_READY | 0 | | 407 | 107 | DEV_SERDES_10G4_IP4_LN3_TXMCLK | CLK_STATE_READY | 0 | | 77 | 0 | DEV_STM0_ATB_CLK | CLK_STATE_READY | 250000000 | | 77 | 1 | DEV_STM0_CORE_CLK | CLK_STATE_READY | 250000000 | | 77 | 2 | DEV_STM0_VBUSP_CLK | CLK_STATE_READY | 125000000 | | 97 | 0 | DEV_TIMER0_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | 97 | 1 | DEV_TIMER0_TIMER_PWM | CLK_STATE_READY | 0 | | 97 | 2 | DEV_TIMER0_TIMER_TCLK_CLK | CLK_STATE_READY | 24000000 | | 97 | 3 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 24000000 | | 97 | 4 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 97 | 5 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK | CLK_STATE_READY | 250000000 | | 97 | 6 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | 97 | 7 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | CLK_STATE_READY | 250000000 | | 97 | 8 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 97 | 9 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | 97 | 10 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | CLK_STATE_READY | 32768 | | 97 | 11 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | 97 | 12 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | CLK_STATE_READY | 192000000 | | 97 | 13 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | CLK_STATE_READY | 225000000 | | 97 | 14 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | 97 | 15 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | 97 | 16 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | 97 | 17 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0 | CLK_STATE_READY | 0 | | 97 | 18 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_J7AM_MAIN_0_CPTS_GENF0 | CLK_STATE_READY | 0 | | 98 | 0 | DEV_TIMER1_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | 98 | 2 | DEV_TIMER1_TIMER_TCLK_CLK | CLK_STATE_READY | 24000000 | | 98 | 3 | DEV_TIMER1_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT1 | CLK_STATE_READY | 24000000 | | 98 | 4 | DEV_TIMER1_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_0_TIMER_PWM | CLK_STATE_READY | 0 | | 107 | 0 | DEV_TIMER10_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | 107 | 1 | DEV_TIMER10_TIMER_PWM | CLK_STATE_READY | 0 | | 107 | 2 | DEV_TIMER10_TIMER_TCLK_CLK | CLK_STATE_READY | 24000000 | | 107 | 3 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 24000000 | | 107 | 4 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 107 | 5 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK | CLK_STATE_READY | 250000000 | | 107 | 6 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | 107 | 7 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | CLK_STATE_READY | 250000000 | | 107 | 8 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 107 | 9 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | 107 | 10 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | CLK_STATE_READY | 32768 | | 107 | 11 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | 107 | 12 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | CLK_STATE_READY | 192000000 | | 107 | 13 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | CLK_STATE_READY | 225000000 | | 107 | 14 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | 107 | 15 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | 107 | 16 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | 107 | 17 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0 | CLK_STATE_READY | 0 | | 107 | 18 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_J7AM_MAIN_0_CPTS_GENF0 | CLK_STATE_READY | 0 | | 108 | 0 | DEV_TIMER11_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | 108 | 2 | DEV_TIMER11_TIMER_TCLK_CLK | CLK_STATE_READY | 24000000 | | 108 | 3 | DEV_TIMER11_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT11 | CLK_STATE_READY | 24000000 | | 108 | 4 | DEV_TIMER11_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_10_TIMER_PWM | CLK_STATE_NOT_READY | 0 | | 109 | 0 | DEV_TIMER12_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | 109 | 1 | DEV_TIMER12_TIMER_PWM | CLK_STATE_READY | 0 | | 109 | 2 | DEV_TIMER12_TIMER_TCLK_CLK | CLK_STATE_READY | 24000000 | | 109 | 3 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 24000000 | | 109 | 4 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 109 | 5 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK | CLK_STATE_READY | 250000000 | | 109 | 6 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | 109 | 7 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | CLK_STATE_READY | 250000000 | | 109 | 8 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 109 | 9 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | 109 | 10 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | CLK_STATE_READY | 32768 | | 109 | 11 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | 109 | 12 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | CLK_STATE_READY | 192000000 | | 109 | 13 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | CLK_STATE_READY | 225000000 | | 109 | 14 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | 109 | 15 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | 109 | 16 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | 109 | 17 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0 | CLK_STATE_READY | 0 | | 109 | 18 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_J7AM_MAIN_0_CPTS_GENF0 | CLK_STATE_READY | 0 | | 110 | 0 | DEV_TIMER13_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | 110 | 2 | DEV_TIMER13_TIMER_TCLK_CLK | CLK_STATE_READY | 24000000 | | 110 | 3 | DEV_TIMER13_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT13 | CLK_STATE_READY | 24000000 | | 110 | 4 | DEV_TIMER13_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_12_TIMER_PWM | CLK_STATE_NOT_READY | 0 | | 111 | 0 | DEV_TIMER14_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | 111 | 1 | DEV_TIMER14_TIMER_PWM | CLK_STATE_READY | 0 | | 111 | 2 | DEV_TIMER14_TIMER_TCLK_CLK | CLK_STATE_READY | 24000000 | | 111 | 3 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 24000000 | | 111 | 4 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 111 | 5 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK | CLK_STATE_READY | 250000000 | | 111 | 6 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | 111 | 7 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | CLK_STATE_READY | 250000000 | | 111 | 8 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 111 | 9 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | 111 | 10 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | CLK_STATE_READY | 32768 | | 111 | 11 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | 111 | 12 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | CLK_STATE_READY | 192000000 | | 111 | 13 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | CLK_STATE_READY | 225000000 | | 111 | 14 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | 111 | 15 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | 111 | 16 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | 111 | 17 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0 | CLK_STATE_READY | 0 | | 111 | 18 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_J7AM_MAIN_0_CPTS_GENF0 | CLK_STATE_READY | 0 | | 112 | 0 | DEV_TIMER15_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | 112 | 2 | DEV_TIMER15_TIMER_TCLK_CLK | CLK_STATE_READY | 24000000 | | 112 | 3 | DEV_TIMER15_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT15 | CLK_STATE_READY | 24000000 | | 112 | 4 | DEV_TIMER15_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_14_TIMER_PWM | CLK_STATE_NOT_READY | 0 | | 113 | 0 | DEV_TIMER16_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | 113 | 1 | DEV_TIMER16_TIMER_PWM | CLK_STATE_READY | 0 | | 113 | 2 | DEV_TIMER16_TIMER_TCLK_CLK | CLK_STATE_READY | 24000000 | | 113 | 3 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT16 | CLK_STATE_READY | 24000000 | | 113 | 4 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_MAIN_TIMER16_AFS_SEL_OUT0 | CLK_STATE_READY | 0 | | 114 | 0 | DEV_TIMER17_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | 114 | 2 | DEV_TIMER17_TIMER_TCLK_CLK | CLK_STATE_READY | 24000000 | | 114 | 3 | DEV_TIMER17_TIMER_TCLK_CLK_PARENT_MAIN_TIMER17_AFS_EN_OUT0 | CLK_STATE_READY | 24000000 | | 114 | 4 | DEV_TIMER17_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_16_TIMER_PWM | CLK_STATE_NOT_READY | 0 | | 115 | 0 | DEV_TIMER18_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | 115 | 1 | DEV_TIMER18_TIMER_PWM | CLK_STATE_READY | 0 | | 115 | 2 | DEV_TIMER18_TIMER_TCLK_CLK | CLK_STATE_READY | 24000000 | | 115 | 3 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT18 | CLK_STATE_READY | 24000000 | | 115 | 4 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_MAIN_TIMER18_AFS_SEL_OUT0 | CLK_STATE_READY | 0 | | 116 | 0 | DEV_TIMER19_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | 116 | 2 | DEV_TIMER19_TIMER_TCLK_CLK | CLK_STATE_READY | 24000000 | | 116 | 3 | DEV_TIMER19_TIMER_TCLK_CLK_PARENT_MAIN_TIMER19_AFS_EN_OUT0 | CLK_STATE_READY | 24000000 | | 116 | 4 | DEV_TIMER19_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_18_TIMER_PWM | CLK_STATE_NOT_READY | 0 | | 99 | 0 | DEV_TIMER2_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | 99 | 1 | DEV_TIMER2_TIMER_PWM | CLK_STATE_READY | 0 | | 99 | 2 | DEV_TIMER2_TIMER_TCLK_CLK | CLK_STATE_READY | 24000000 | | 99 | 3 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 24000000 | | 99 | 4 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 99 | 5 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK | CLK_STATE_READY | 250000000 | | 99 | 6 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | 99 | 7 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | CLK_STATE_READY | 250000000 | | 99 | 8 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 99 | 9 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | 99 | 10 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | CLK_STATE_READY | 32768 | | 99 | 11 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | 99 | 12 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | CLK_STATE_READY | 192000000 | | 99 | 13 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | CLK_STATE_READY | 225000000 | | 99 | 14 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | 99 | 15 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | 99 | 16 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | 99 | 17 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0 | CLK_STATE_READY | 0 | | 99 | 18 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_J7AM_MAIN_0_CPTS_GENF0 | CLK_STATE_READY | 0 | | 100 | 0 | DEV_TIMER3_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | 100 | 2 | DEV_TIMER3_TIMER_TCLK_CLK | CLK_STATE_READY | 24000000 | | 100 | 3 | DEV_TIMER3_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT3 | CLK_STATE_READY | 24000000 | | 100 | 4 | DEV_TIMER3_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_2_TIMER_PWM | CLK_STATE_READY | 0 | | 101 | 0 | DEV_TIMER4_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | 101 | 1 | DEV_TIMER4_TIMER_PWM | CLK_STATE_READY | 0 | | 101 | 2 | DEV_TIMER4_TIMER_TCLK_CLK | CLK_STATE_READY | 24000000 | | 101 | 3 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 24000000 | | 101 | 4 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 101 | 5 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK | CLK_STATE_READY | 250000000 | | 101 | 6 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | 101 | 7 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | CLK_STATE_READY | 250000000 | | 101 | 8 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 101 | 9 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | 101 | 10 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | CLK_STATE_READY | 32768 | | 101 | 11 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | 101 | 12 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | CLK_STATE_READY | 192000000 | | 101 | 13 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | CLK_STATE_READY | 225000000 | | 101 | 14 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | 101 | 15 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | 101 | 16 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | 101 | 17 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0 | CLK_STATE_READY | 0 | | 101 | 18 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_J7AM_MAIN_0_CPTS_GENF0 | CLK_STATE_READY | 0 | | 102 | 0 | DEV_TIMER5_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | 102 | 2 | DEV_TIMER5_TIMER_TCLK_CLK | CLK_STATE_READY | 24000000 | | 102 | 3 | DEV_TIMER5_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT5 | CLK_STATE_READY | 24000000 | | 102 | 4 | DEV_TIMER5_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_4_TIMER_PWM | CLK_STATE_READY | 0 | | 103 | 0 | DEV_TIMER6_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | 103 | 1 | DEV_TIMER6_TIMER_PWM | CLK_STATE_READY | 0 | | 103 | 2 | DEV_TIMER6_TIMER_TCLK_CLK | CLK_STATE_READY | 24000000 | | 103 | 3 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 24000000 | | 103 | 4 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 103 | 5 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK | CLK_STATE_READY | 250000000 | | 103 | 6 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | 103 | 7 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | CLK_STATE_READY | 250000000 | | 103 | 8 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 103 | 9 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | 103 | 10 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | CLK_STATE_READY | 32768 | | 103 | 11 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | 103 | 12 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | CLK_STATE_READY | 192000000 | | 103 | 13 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | CLK_STATE_READY | 225000000 | | 103 | 14 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | 103 | 15 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | 103 | 16 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | 103 | 17 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0 | CLK_STATE_READY | 0 | | 103 | 18 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_J7AM_MAIN_0_CPTS_GENF0 | CLK_STATE_READY | 0 | | 104 | 0 | DEV_TIMER7_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | 104 | 2 | DEV_TIMER7_TIMER_TCLK_CLK | CLK_STATE_READY | 24000000 | | 104 | 3 | DEV_TIMER7_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT7 | CLK_STATE_READY | 24000000 | | 104 | 4 | DEV_TIMER7_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_6_TIMER_PWM | CLK_STATE_READY | 0 | | 105 | 0 | DEV_TIMER8_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | 105 | 1 | DEV_TIMER8_TIMER_PWM | CLK_STATE_READY | 0 | | 105 | 2 | DEV_TIMER8_TIMER_TCLK_CLK | CLK_STATE_READY | 24000000 | | 105 | 3 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 24000000 | | 105 | 4 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 105 | 5 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK | CLK_STATE_READY | 250000000 | | 105 | 6 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | 105 | 7 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | CLK_STATE_READY | 250000000 | | 105 | 8 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 105 | 9 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | 105 | 10 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | CLK_STATE_READY | 32768 | | 105 | 11 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | 105 | 12 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | CLK_STATE_READY | 192000000 | | 105 | 13 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | CLK_STATE_READY | 225000000 | | 105 | 14 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | 105 | 15 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | 105 | 16 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | 105 | 17 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0 | CLK_STATE_READY | 0 | | 105 | 18 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_J7AM_MAIN_0_CPTS_GENF0 | CLK_STATE_READY | 0 | | 106 | 0 | DEV_TIMER9_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | 106 | 2 | DEV_TIMER9_TIMER_TCLK_CLK | CLK_STATE_READY | 24000000 | | 106 | 3 | DEV_TIMER9_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT9 | CLK_STATE_READY | 24000000 | | 106 | 4 | DEV_TIMER9_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_8_TIMER_PWM | CLK_STATE_NOT_READY | 0 | | 176 | 0 | DEV_TIMESYNC_INTRTR0_INTR_CLK | CLK_STATE_READY | 125000000 | | 146 | 0 | DEV_UART0_FCLK_CLK | CLK_STATE_READY | 48000000 | | 146 | 3 | DEV_UART0_VBUSP_CLK | CLK_STATE_READY | 125000000 | | 388 | 0 | DEV_UART1_FCLK_CLK | CLK_STATE_READY | 48000000 | | 388 | 3 | DEV_UART1_VBUSP_CLK | CLK_STATE_READY | 125000000 | | 389 | 0 | DEV_UART2_FCLK_CLK | CLK_STATE_READY | 48000000 | | 389 | 3 | DEV_UART2_VBUSP_CLK | CLK_STATE_READY | 125000000 | | 390 | 0 | DEV_UART3_FCLK_CLK | CLK_STATE_READY | 48000000 | | 390 | 3 | DEV_UART3_VBUSP_CLK | CLK_STATE_READY | 125000000 | | 391 | 0 | DEV_UART4_FCLK_CLK | CLK_STATE_READY | 48000000 | | 391 | 3 | DEV_UART4_VBUSP_CLK | CLK_STATE_READY | 125000000 | | 392 | 0 | DEV_UART5_FCLK_CLK | CLK_STATE_READY | 48000000 | | 392 | 3 | DEV_UART5_VBUSP_CLK | CLK_STATE_READY | 125000000 | | 393 | 0 | DEV_UART6_FCLK_CLK | CLK_STATE_READY | 48000000 | | 393 | 3 | DEV_UART6_VBUSP_CLK | CLK_STATE_READY | 125000000 | | 394 | 0 | DEV_UART7_FCLK_CLK | CLK_STATE_READY | 48000000 | | 394 | 3 | DEV_UART7_VBUSP_CLK | CLK_STATE_READY | 125000000 | | 395 | 0 | DEV_UART8_FCLK_CLK | CLK_STATE_READY | 48000000 | | 395 | 3 | DEV_UART8_VBUSP_CLK | CLK_STATE_READY | 125000000 | | 396 | 0 | DEV_UART9_FCLK_CLK | CLK_STATE_READY | 48000000 | | 396 | 3 | DEV_UART9_VBUSP_CLK | CLK_STATE_READY | 125000000 | | 387 | 1 | DEV_UFS0_UFSHCI_HCLK_CLK | CLK_STATE_READY | 250000000 | | 387 | 3 | DEV_UFS0_UFSHCI_MCLK_CLK | CLK_STATE_READY | 24000000 | | 387 | 4 | DEV_UFS0_UFSHCI_MCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 24000000 | | 387 | 5 | DEV_UFS0_UFSHCI_MCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 387 | 6 | DEV_UFS0_UFSHCI_MCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_1_HSDIVOUT6_CLK | CLK_STATE_READY | 19200000 | | 387 | 7 | DEV_UFS0_UFSHCI_MCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | 387 | 8 | DEV_UFS0_UFSHCI_MPHY_REFCLK | CLK_STATE_READY | 0 | | 387 | 23 | DEV_UFS0_UFSHCI_MPHY_TX_REF_SYMBOLCLK | CLK_STATE_READY | 0 | | 387 | 24 | DEV_UFS0_UFSHCI_MPHY_M31_VCO_19P2M_CLK | CLK_STATE_READY | 0 | | 387 | 25 | DEV_UFS0_UFSHCI_MPHY_M31_VCO_26M_CLK | CLK_STATE_READY | 0 | | 398 | 0 | DEV_USB0_ACLK_CLK | CLK_STATE_READY | 500000000 | | 398 | 1 | DEV_USB0_BUF_CLK | CLK_STATE_READY | 250000000 | | 398 | 2 | DEV_USB0_CLK_LPM_CLK | CLK_STATE_READY | 24000000 | | 398 | 3 | DEV_USB0_PCLK_CLK | CLK_STATE_READY | 125000000 | | 398 | 4 | DEV_USB0_PIPE_REFCLK | CLK_STATE_READY | 0 | | 398 | 5 | DEV_USB0_PIPE_REFCLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP3_LN3_REFCLK | CLK_STATE_READY | 0 | | 398 | 6 | DEV_USB0_PIPE_REFCLK_PARENT_WIZ16B8M4CT3_MAIN_4_IP3_LN3_REFCLK | CLK_STATE_READY | 0 | | 398 | 7 | DEV_USB0_PIPE_RXCLK | CLK_STATE_READY | 0 | | 398 | 8 | DEV_USB0_PIPE_RXCLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP3_LN3_RXCLK | CLK_STATE_READY | 0 | | 398 | 9 | DEV_USB0_PIPE_RXCLK_PARENT_WIZ16B8M4CT3_MAIN_4_IP3_LN3_RXCLK | CLK_STATE_READY | 0 | | 398 | 10 | DEV_USB0_PIPE_RXFCLK | CLK_STATE_READY | 0 | | 398 | 11 | DEV_USB0_PIPE_RXFCLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP3_LN3_RXFCLK | CLK_STATE_READY | 0 | | 398 | 12 | DEV_USB0_PIPE_RXFCLK_PARENT_WIZ16B8M4CT3_MAIN_4_IP3_LN3_RXFCLK | CLK_STATE_READY | 0 | | 398 | 13 | DEV_USB0_PIPE_TXCLK | CLK_STATE_READY | 0 | | 398 | 14 | DEV_USB0_PIPE_TXFCLK | CLK_STATE_READY | 0 | | 398 | 15 | DEV_USB0_PIPE_TXFCLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP3_LN3_TXFCLK | CLK_STATE_READY | 0 | | 398 | 16 | DEV_USB0_PIPE_TXFCLK_PARENT_WIZ16B8M4CT3_MAIN_4_IP3_LN3_TXFCLK | CLK_STATE_READY | 0 | | 398 | 17 | DEV_USB0_PIPE_TXMCLK | CLK_STATE_READY | 0 | | 398 | 18 | DEV_USB0_PIPE_TXMCLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP3_LN3_TXMCLK | CLK_STATE_READY | 0 | | 398 | 19 | DEV_USB0_PIPE_TXMCLK_PARENT_WIZ16B8M4CT3_MAIN_4_IP3_LN3_TXMCLK | CLK_STATE_READY | 0 | | 398 | 20 | DEV_USB0_USB2_APB_PCLK_CLK | CLK_STATE_READY | 125000000 | | 398 | 21 | DEV_USB0_USB2_REFCLOCK_CLK | CLK_STATE_READY | 24000000 | | 398 | 22 | DEV_USB0_USB2_REFCLOCK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 24000000 | | 398 | 23 | DEV_USB0_USB2_REFCLOCK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 398 | 28 | DEV_USB0_USB2_TAP_TCK | CLK_STATE_READY | 0 | | 399 | 0 | DEV_VPAC0_LDC0_CLK_CLK | CLK_STATE_READY | 720000000 | | 399 | 1 | DEV_VPAC0_MAIN_CLK | CLK_STATE_READY | 720000000 | | 399 | 2 | DEV_VPAC0_MAIN_CLK_PARENT_HSDIV1_16FFT_MAIN_25_HSDIVOUT1_CLK | CLK_STATE_READY | 720000000 | | 399 | 3 | DEV_VPAC0_MAIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK | CLK_STATE_READY | 600000000 | | 399 | 4 | DEV_VPAC0_MSC_CLK | CLK_STATE_READY | 720000000 | | 399 | 5 | DEV_VPAC0_NF_CLK_CLK | CLK_STATE_READY | 720000000 | | 399 | 6 | DEV_VPAC0_PSIL_LEAF_CLK | CLK_STATE_READY | 500000000 | | 399 | 7 | DEV_VPAC0_VISS0_CLK_CLK | CLK_STATE_READY | 720000000 | | 400 | 0 | DEV_VPAC1_LDC0_CLK_CLK | CLK_STATE_READY | 720000000 | | 400 | 1 | DEV_VPAC1_MAIN_CLK | CLK_STATE_READY | 720000000 | | 400 | 2 | DEV_VPAC1_MAIN_CLK_PARENT_HSDIV1_16FFT_MAIN_25_HSDIVOUT1_CLK | CLK_STATE_READY | 720000000 | | 400 | 3 | DEV_VPAC1_MAIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK | CLK_STATE_READY | 600000000 | | 400 | 4 | DEV_VPAC1_MSC_CLK | CLK_STATE_READY | 720000000 | | 400 | 5 | DEV_VPAC1_NF_CLK_CLK | CLK_STATE_READY | 720000000 | | 400 | 6 | DEV_VPAC1_PSIL_LEAF_CLK | CLK_STATE_READY | 500000000 | | 400 | 7 | DEV_VPAC1_VISS0_CLK_CLK | CLK_STATE_READY | 720000000 | | 401 | 0 | DEV_VUSR_DUAL0_V0_CLK | CLK_STATE_READY | 500000000 | | 401 | 1 | DEV_VUSR_DUAL0_V0_RXFL_CLK | CLK_STATE_READY | 0 | | 401 | 2 | DEV_VUSR_DUAL0_V0_RXPM_CLK | CLK_STATE_READY | 0 | | 401 | 3 | DEV_VUSR_DUAL0_V0_TXFL_CLK | CLK_STATE_READY | 0 | | 401 | 4 | DEV_VUSR_DUAL0_V0_TXPM_CLK | CLK_STATE_READY | 0 | | 401 | 5 | DEV_VUSR_DUAL0_V1_CLK | CLK_STATE_READY | 500000000 | | 401 | 6 | DEV_VUSR_DUAL0_V1_RXFL_CLK | CLK_STATE_READY | 0 | | 401 | 7 | DEV_VUSR_DUAL0_V1_RXPM_CLK | CLK_STATE_READY | 0 | | 401 | 8 | DEV_VUSR_DUAL0_V1_TXFL_CLK | CLK_STATE_READY | 0 | | 401 | 9 | DEV_VUSR_DUAL0_V1_TXPM_CLK | CLK_STATE_READY | 0 | | 401 | 10 | DEV_VUSR_DUAL0_VUSRX_LN0_REFCLK | CLK_STATE_READY | 0 | | 401 | 11 | DEV_VUSR_DUAL0_VUSRX_LN0_RXCLK | CLK_STATE_READY | 0 | | 401 | 12 | DEV_VUSR_DUAL0_VUSRX_LN0_RXFCLK | CLK_STATE_READY | 0 | | 401 | 13 | DEV_VUSR_DUAL0_VUSRX_LN0_TXCLK | CLK_STATE_READY | 0 | | 401 | 14 | DEV_VUSR_DUAL0_VUSRX_LN0_TXFCLK | CLK_STATE_READY | 0 | | 401 | 15 | DEV_VUSR_DUAL0_VUSRX_LN0_TXMCLK | CLK_STATE_READY | 0 | | 401 | 16 | DEV_VUSR_DUAL0_VUSRX_LN1_REFCLK | CLK_STATE_READY | 0 | | 401 | 17 | DEV_VUSR_DUAL0_VUSRX_LN1_RXCLK | CLK_STATE_READY | 0 | | 401 | 18 | DEV_VUSR_DUAL0_VUSRX_LN1_RXFCLK | CLK_STATE_READY | 0 | | 401 | 19 | DEV_VUSR_DUAL0_VUSRX_LN1_TXCLK | CLK_STATE_READY | 0 | | 401 | 20 | DEV_VUSR_DUAL0_VUSRX_LN1_TXFCLK | CLK_STATE_READY | 0 | | 401 | 21 | DEV_VUSR_DUAL0_VUSRX_LN1_TXMCLK | CLK_STATE_READY | 0 | | 401 | 22 | DEV_VUSR_DUAL0_VUSRX_LN2_REFCLK | CLK_STATE_READY | 0 | | 401 | 23 | DEV_VUSR_DUAL0_VUSRX_LN2_RXCLK | CLK_STATE_READY | 0 | | 401 | 24 | DEV_VUSR_DUAL0_VUSRX_LN2_RXFCLK | CLK_STATE_READY | 0 | | 401 | 25 | DEV_VUSR_DUAL0_VUSRX_LN2_TXCLK | CLK_STATE_READY | 0 | | 401 | 26 | DEV_VUSR_DUAL0_VUSRX_LN2_TXFCLK | CLK_STATE_READY | 0 | | 401 | 27 | DEV_VUSR_DUAL0_VUSRX_LN2_TXMCLK | CLK_STATE_READY | 0 | | 401 | 28 | DEV_VUSR_DUAL0_VUSRX_LN3_REFCLK | CLK_STATE_READY | 0 | | 401 | 29 | DEV_VUSR_DUAL0_VUSRX_LN3_RXCLK | CLK_STATE_READY | 0 | | 401 | 30 | DEV_VUSR_DUAL0_VUSRX_LN3_RXFCLK | CLK_STATE_READY | 0 | | 401 | 31 | DEV_VUSR_DUAL0_VUSRX_LN3_TXCLK | CLK_STATE_READY | 0 | | 401 | 32 | DEV_VUSR_DUAL0_VUSRX_LN3_TXFCLK | CLK_STATE_READY | 0 | | 401 | 33 | DEV_VUSR_DUAL0_VUSRX_LN3_TXMCLK | CLK_STATE_READY | 0 | | 211 | 0 | DEV_WKUP_DDPA0_DDPA_CLK | CLK_STATE_READY | 166666666 | | 147 | 0 | DEV_WKUP_ESM0_CLK | CLK_STATE_READY | 166666666 | | 167 | 0 | DEV_WKUP_GPIO0_MMR_CLK | CLK_STATE_READY | 27777777 | | 168 | 0 | DEV_WKUP_GPIO1_MMR_CLK | CLK_STATE_READY | 27777777 | | 177 | 0 | DEV_WKUP_GPIOMUX_INTRTR0_INTR_CLK | CLK_STATE_READY | 166666666 | | 371 | 0 | DEV_WKUP_HSM0_DAP_CLK | CLK_STATE_READY | 1000000000 | | 279 | 0 | DEV_WKUP_I2C0_CLK | CLK_STATE_READY | 166666666 | | 279 | 1 | DEV_WKUP_I2C0_PISCL | CLK_STATE_READY | 0 | | 279 | 2 | DEV_WKUP_I2C0_PISYS_CLK | CLK_STATE_READY | 96000000 | | 279 | 3 | DEV_WKUP_I2C0_PISYS_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT3_CLK | CLK_STATE_READY | 96000000 | | 279 | 4 | DEV_WKUP_I2C0_PISYS_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 24000000 | | 279 | 5 | DEV_WKUP_I2C0_PORSCL | CLK_STATE_READY | 0 | | 9 | 0 | DEV_WKUP_J7AM_WAKEUP_16FF0_PLL_CTRL_WKUP_CLK24_CLK | CLK_STATE_READY | 1000000000 | | 9 | 1 | DEV_WKUP_J7AM_WAKEUP_16FF0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | 9 | 2 | DEV_WKUP_J7AM_WAKEUP_16FF0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32000 | | 175 | 0 | DEV_WKUP_PORZ_SYNC0_CLK_12M_RC_CLK | CLK_STATE_READY | 12500000 | | 178 | 0 | DEV_WKUP_PSC0_CLK | CLK_STATE_READY | 166666666 | | 178 | 1 | DEV_WKUP_PSC0_SLOW_CLK | CLK_STATE_READY | 41666666 | | 397 | 0 | DEV_WKUP_UART0_FCLK_CLK | CLK_STATE_READY | 96000000 | | 397 | 1 | DEV_WKUP_UART0_FCLK_CLK_PARENT_WKUP_USART_CLKSEL_OUT0 | CLK_STATE_READY | 96000000 | | 397 | 2 | DEV_WKUP_UART0_FCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 24000000 | | 397 | 7 | DEV_WKUP_UART0_VBUSP_CLK | CLK_STATE_READY | 166666666 | | 243 | 0 | DEV_WKUP_VTM0_FIX_REF2_CLK | CLK_STATE_READY | 12500000 | | 243 | 1 | DEV_WKUP_VTM0_FIX_REF_CLK | CLK_STATE_READY | 24000000 | | 243 | 2 | DEV_WKUP_VTM0_VBUSP_CLK | CLK_STATE_READY | 166666666 | |----------------------------------------------------------------------------------------------------------------------------------------------------|
Kind regards,
Emanuele