AM69: SERDES external reference clock selection not working

Emanuele Ghidoli

Part Number: AM69

Tool/software:

Hello,
I am trying to use the external reference clock for serdes1 but if I check the clock configuration (see below) nothing changes from the default configuration.

&serdes1 {
	status = "okay";
	assigned-clock-parents = <&serdes_refclk>,
				 <&serdes_refclk>,
				 <&serdes_refclk>;
	...

I followed this documentation:
https://software-dl.ti.com/jacinto7/esd/processor-sdk-linux-am69/09_01_00_06/exports/docs/linux/Foundational_Components/Kernel/Kernel_Drivers/SERDES/SERDES.html#selecting-between-internal-and-external-reference-clock

This is the output of k3config dump clock (it does not change anything although I changed the device tree):


data-mode="text">|------------------------------------------------------------------------------| | ------------------------------------------------------------| (version 0.3-nogit built Wed Mar 06 14:29:58 UTC 2024)              | | ABI: 3.1 (firmware version 0x0009 '9.2.4--v09.02.04 (Kool Koala))') | ------------------------------------------------------------| ----------------------------------------------------------------------------------------------------------------------------------| | Clock ID | Clock Name                                                                          | Status              | Clock Frequency | ----------------------------------------------------------------------------------------------------------------------------------| 0    | DEV_A72SS0_ARM0_CLK_CLK                                                             | CLK_STATE_READY     | 2000000001      | 2    | DEV_A72SS0_ARM0_DIVH_CLK8_OBSCLK_OUT_CLK                                            | CLK_STATE_READY     | 0               | 3    | DEV_A72SS0_ARM0_MSMC_CLK_CLK                                                        | CLK_STATE_READY     | 1000000000      | 4    | DEV_A72SS0_ARM0_PLL_CTRL_CLK_CLK                                                    | CLK_STATE_READY     | 500000000       | 0    | DEV_A72SS0_CORE0_ARM0_CLK_CLK                                                       | CLK_STATE_READY     | 2000000001      | 0    | DEV_A72SS0_CORE1_ARM0_CLK_CLK                                                       | CLK_STATE_READY     | 2000000001      | 0    | DEV_A72SS0_CORE2_ARM0_CLK_CLK                                                       | CLK_STATE_READY     | 2000000001      | 0    | DEV_A72SS0_CORE3_ARM0_CLK_CLK                                                       | CLK_STATE_READY     | 2000000001      | 0    | DEV_A72SS1_ARM1_CLK_CLK                                                             | CLK_STATE_READY     | 2000000001      | 2    | DEV_A72SS1_ARM1_DIVH_CLK8_OBSCLK_OUT_CLK                                            | CLK_STATE_READY     | 0               | 6    | DEV_A72SS1_ARM1_PLL_CTRL_CLK_CLK                                                    | CLK_STATE_READY     | 500000000       | 0    | DEV_A72SS1_CORE0_ARM1_CLK_CLK                                                       | CLK_STATE_READY     | 2000000001      | 0    | DEV_A72SS1_CORE1_ARM1_CLK_CLK                                                       | CLK_STATE_READY     | 2000000001      | 0    | DEV_A72SS1_CORE2_ARM1_CLK_CLK                                                       | CLK_STATE_READY     | 2000000001      | 0    | DEV_A72SS1_CORE3_ARM1_CLK_CLK                                                       | CLK_STATE_READY     | 2000000001      | 0    | DEV_AGGR_ATB0_DBG_CLK                                                               | CLK_STATE_READY     | 250000000       | 0    | DEV_ATL0_ATL_CLK                                                                    | CLK_STATE_READY     | 294912000       | 1    | DEV_ATL0_ATL_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT1_CLK                           | CLK_STATE_READY     | 294912000       | 2    | DEV_ATL0_ATL_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK                           | CLK_STATE_READY     | 200000000       | 5    | DEV_ATL0_ATL_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT7_CLK                         | CLK_STATE_READY     | 200000000       | 6    | DEV_ATL0_ATL_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                                 | CLK_STATE_READY     | 0               | 7    | DEV_ATL0_ATL_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT                                     | CLK_STATE_READY     | 0               | 9    | DEV_ATL0_ATL_IO_PORT_ATCLK_OUT                                                      | CLK_STATE_READY     | 0               | 10    | DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_1                                                    | CLK_STATE_READY     | 0               | 11    | DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_2                                                    | CLK_STATE_READY     | 0               | 12    | DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_3                                                    | CLK_STATE_READY     | 0               | 13    | DEV_ATL0_ATL_IO_PORT_AWS                                                            | CLK_STATE_READY     | 0               | 14    | DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT                        | CLK_STATE_READY     | 0               | 15    | DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT                        | CLK_STATE_READY     | 0               | 16    | DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT_DUP0                   | CLK_STATE_READY     | 0               | 17    | DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT_DUP0                   | CLK_STATE_READY     | 0               | 18    | DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT_DUP0                   | CLK_STATE_READY     | 0               | 26    | DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT_DUP0                   | CLK_STATE_READY     | 0               | 27    | DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT_DUP0                   | CLK_STATE_READY     | 0               | 28    | DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT                        | CLK_STATE_READY     | 0               | 29    | DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT                        | CLK_STATE_READY     | 0               | 30    | DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT                        | CLK_STATE_READY     | 0               | 38    | DEV_ATL0_ATL_IO_PORT_AWS_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT                       | CLK_STATE_READY     | 0               | 39    | DEV_ATL0_ATL_IO_PORT_AWS_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT                       | CLK_STATE_READY     | 0               | 46    | DEV_ATL0_ATL_IO_PORT_AWS_1                                                          | CLK_STATE_READY     | 0               | 47    | DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT                      | CLK_STATE_READY     | 0               | 48    | DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT                      | CLK_STATE_READY     | 0               | 49    | DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT_DUP0                 | CLK_STATE_READY     | 0               | 50    | DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT_DUP0                 | CLK_STATE_READY     | 0               | 51    | DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT_DUP0                 | CLK_STATE_READY     | 0               | 59    | DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT_DUP0                 | CLK_STATE_READY     | 0               | 60    | DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT_DUP0                 | CLK_STATE_READY     | 0               | 61    | DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT                      | CLK_STATE_READY     | 0               | 62    | DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT                      | CLK_STATE_READY     | 0               | 63    | DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT                      | CLK_STATE_READY     | 0               | 71    | DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT                     | CLK_STATE_READY     | 0               | 72    | DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT                     | CLK_STATE_READY     | 0               | 85    | DEV_ATL0_ATL_IO_PORT_AWS_2                                                          | CLK_STATE_READY     | 0               | 86    | DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT                      | CLK_STATE_READY     | 0               | 87    | DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT                      | CLK_STATE_READY     | 0               | 88    | DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT_DUP0                 | CLK_STATE_READY     | 0               | 89    | DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT_DUP0                 | CLK_STATE_READY     | 0               | 90    | DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT_DUP0                 | CLK_STATE_READY     | 0               | 98    | DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT_DUP0                 | CLK_STATE_READY     | 0               | 99    | DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT_DUP0                 | CLK_STATE_READY     | 0               | | DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT                      | CLK_STATE_READY     | 0               | | DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT                      | CLK_STATE_READY     | 0               | | DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT                      | CLK_STATE_READY     | 0               | | DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT                     | CLK_STATE_READY     | 0               | | DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT                     | CLK_STATE_READY     | 0               | | DEV_ATL0_ATL_IO_PORT_AWS_3                                                          | CLK_STATE_READY     | 0               | | DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT                      | CLK_STATE_READY     | 0               | | DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT                      | CLK_STATE_READY     | 0               | | DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT_DUP0                 | CLK_STATE_READY     | 0               | | DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT_DUP0                 | CLK_STATE_READY     | 0               | | DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT_DUP0                 | CLK_STATE_READY     | 0               | | DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT_DUP0                 | CLK_STATE_READY     | 0               | | DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT_DUP0                 | CLK_STATE_READY     | 0               | | DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT                      | CLK_STATE_READY     | 0               | | DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT                      | CLK_STATE_READY     | 0               | | DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT                      | CLK_STATE_READY     | 0               | | DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT                     | CLK_STATE_READY     | 0               | | DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT                     | CLK_STATE_READY     | 0               | | DEV_ATL0_ATL_IO_PORT_BWS                                                            | CLK_STATE_READY     | 0               | | DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_0_MCASP_AFSR_POUT                        | CLK_STATE_READY     | 0               | | DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_1_MCASP_AFSR_POUT                        | CLK_STATE_READY     | 0               | | DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_2_MCASP_AFSR_POUT                        | CLK_STATE_READY     | 0               | | DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_3_MCASP_AFSR_POUT                        | CLK_STATE_READY     | 0               | | DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_4_MCASP_AFSR_POUT                        | CLK_STATE_READY     | 0               | | DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT                        | CLK_STATE_READY     | 0               | | DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT                        | CLK_STATE_READY     | 0               | | DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT                        | CLK_STATE_READY     | 0               | | DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT                        | CLK_STATE_READY     | 0               | | DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT                        | CLK_STATE_READY     | 0               | | DEV_ATL0_ATL_IO_PORT_BWS_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT                       | CLK_STATE_READY     | 0               | | DEV_ATL0_ATL_IO_PORT_BWS_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT                       | CLK_STATE_READY     | 0               | | DEV_ATL0_ATL_IO_PORT_BWS_1                                                          | CLK_STATE_READY     | 0               | | DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_0_MCASP_AFSR_POUT                      | CLK_STATE_READY     | 0               | | DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_1_MCASP_AFSR_POUT                      | CLK_STATE_READY     | 0               | | DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_2_MCASP_AFSR_POUT                      | CLK_STATE_READY     | 0               | | DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_3_MCASP_AFSR_POUT                      | CLK_STATE_READY     | 0               | | DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_4_MCASP_AFSR_POUT                      | CLK_STATE_READY     | 0               | | DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT                      | CLK_STATE_READY     | 0               | | DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT                      | CLK_STATE_READY     | 0               | | DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT                      | CLK_STATE_READY     | 0               | | DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT                      | CLK_STATE_READY     | 0               | | DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT                      | CLK_STATE_READY     | 0               | | DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT                     | CLK_STATE_READY     | 0               | | DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT                     | CLK_STATE_READY     | 0               | | DEV_ATL0_ATL_IO_PORT_BWS_2                                                          | CLK_STATE_READY     | 0               | | DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_0_MCASP_AFSR_POUT                      | CLK_STATE_READY     | 0               | | DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_1_MCASP_AFSR_POUT                      | CLK_STATE_READY     | 0               | | DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_2_MCASP_AFSR_POUT                      | CLK_STATE_READY     | 0               | | DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_3_MCASP_AFSR_POUT                      | CLK_STATE_READY     | 0               | | DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_4_MCASP_AFSR_POUT                      | CLK_STATE_READY     | 0               | | DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT                      | CLK_STATE_READY     | 0               | | DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT                      | CLK_STATE_READY     | 0               | | DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT                      | CLK_STATE_READY     | 0               | | DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT                      | CLK_STATE_READY     | 0               | | DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT                      | CLK_STATE_READY     | 0               | | DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT                     | CLK_STATE_READY     | 0               | | DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT                     | CLK_STATE_READY     | 0               | | DEV_ATL0_ATL_IO_PORT_BWS_3                                                          | CLK_STATE_READY     | 0               | | DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_0_MCASP_AFSR_POUT                      | CLK_STATE_READY     | 0               | | DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_1_MCASP_AFSR_POUT                      | CLK_STATE_READY     | 0               | | DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_2_MCASP_AFSR_POUT                      | CLK_STATE_READY     | 0               | | DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_3_MCASP_AFSR_POUT                      | CLK_STATE_READY     | 0               | | DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_4_MCASP_AFSR_POUT                      | CLK_STATE_READY     | 0               | | DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT                      | CLK_STATE_READY     | 0               | | DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT                      | CLK_STATE_READY     | 0               | | DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT                      | CLK_STATE_READY     | 0               | | DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT                      | CLK_STATE_READY     | 0               | | DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT                      | CLK_STATE_READY     | 0               | | DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT                     | CLK_STATE_READY     | 0               | | DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT                     | CLK_STATE_READY     | 0               | | DEV_ATL0_VBUS_CLK                                                                   | CLK_STATE_READY     | 250000000       | 0    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN                                                     | CLK_STATE_NOT_READY | 0               | 1    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT               | CLK_STATE_READY     | 0               | 2    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT               | CLK_STATE_READY     | 0               | 3    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT               | CLK_STATE_READY     | 0               | 4    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT               | CLK_STATE_READY     | 0               | 5    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT               | CLK_STATE_READY     | 0               | 13    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT               | CLK_STATE_READY     | 0               | 14    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT               | CLK_STATE_READY     | 0               | 15    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT               | CLK_STATE_READY     | 0               | 16    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT               | CLK_STATE_READY     | 0               | 17    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT               | CLK_STATE_READY     | 0               | 25    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT             | CLK_STATE_NOT_READY | 0               | 26    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1           | CLK_STATE_NOT_READY | 0               | 27    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2           | CLK_STATE_NOT_READY | 0               | 28    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3           | CLK_STATE_NOT_READY | 0               | 29    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK            | CLK_STATE_READY     | 196608000       | 33    | DEV_BOARD0_AUDIO_EXT_REFCLK0_OUT                                                    | CLK_STATE_READY     | 0               | 34    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN                                                     | CLK_STATE_NOT_READY | 0               | 35    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT               | CLK_STATE_READY     | 0               | 36    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT               | CLK_STATE_READY     | 0               | 37    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT               | CLK_STATE_READY     | 0               | 38    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT               | CLK_STATE_READY     | 0               | 39    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT               | CLK_STATE_READY     | 0               | 47    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT               | CLK_STATE_READY     | 0               | 48    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT               | CLK_STATE_READY     | 0               | 49    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT               | CLK_STATE_READY     | 0               | 50    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT               | CLK_STATE_READY     | 0               | 51    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT               | CLK_STATE_READY     | 0               | 59    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT             | CLK_STATE_NOT_READY | 0               | 60    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1           | CLK_STATE_NOT_READY | 0               | 61    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2           | CLK_STATE_NOT_READY | 0               | 62    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3           | CLK_STATE_NOT_READY | 0               | 63    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK            | CLK_STATE_READY     | 196608000       | 67    | DEV_BOARD0_AUDIO_EXT_REFCLK1_OUT                                                    | CLK_STATE_READY     | 0               | 68    | DEV_BOARD0_CPTS0_RFT_CLK_OUT                                                        | CLK_STATE_READY     | 0               | 69    | DEV_BOARD0_CSI0_RXCLKN_OUT                                                          | CLK_STATE_READY     | 0               | 70    | DEV_BOARD0_CSI0_RXCLKP_OUT                                                          | CLK_STATE_READY     | 0               | 71    | DEV_BOARD0_CSI0_TXCLKN_IN                                                           | CLK_STATE_READY     | 0               | 72    | DEV_BOARD0_CSI0_TXCLKP_IN                                                           | CLK_STATE_READY     | 0               | 73    | DEV_BOARD0_CSI1_RXCLKN_OUT                                                          | CLK_STATE_READY     | 0               | 74    | DEV_BOARD0_CSI1_RXCLKP_OUT                                                          | CLK_STATE_READY     | 0               | 75    | DEV_BOARD0_CSI1_TXCLKN_IN                                                           | CLK_STATE_READY     | 0               | 76    | DEV_BOARD0_CSI1_TXCLKP_IN                                                           | CLK_STATE_READY     | 0               | 77    | DEV_BOARD0_CSI2_RXCLKN_OUT                                                          | CLK_STATE_READY     | 0               | 78    | DEV_BOARD0_CSI2_RXCLKP_OUT                                                          | CLK_STATE_READY     | 0               | 95    | DEV_BOARD0_DSI0_TXCLKN_IN                                                           | CLK_STATE_READY     | 0               | 96    | DEV_BOARD0_DSI0_TXCLKP_IN                                                           | CLK_STATE_READY     | 0               | 97    | DEV_BOARD0_DSI1_TXCLKN_IN                                                           | CLK_STATE_READY     | 0               | 98    | DEV_BOARD0_DSI1_TXCLKP_IN                                                           | CLK_STATE_READY     | 0               | 99    | DEV_BOARD0_EXT_REFCLK1_OUT                                                          | CLK_STATE_READY     | 0               | | DEV_BOARD0_GPMC0_CLKOUT_IN                                                          | CLK_STATE_READY     | 0               | | DEV_BOARD0_GPMC0_CLK_OUT                                                            | CLK_STATE_READY     | 0               | | DEV_BOARD0_GPMC0_FCLK_MUX_IN                                                        | CLK_STATE_READY     | 133333333       | | DEV_BOARD0_HYP0_RXFLCLK_IN                                                          | CLK_STATE_READY     | 0               | | DEV_BOARD0_HYP0_RXPMCLK_OUT                                                         | CLK_STATE_READY     | 0               | | DEV_BOARD0_HYP0_TXFLCLK_OUT                                                         | CLK_STATE_READY     | 0               | | DEV_BOARD0_HYP0_TXPMCLK_IN                                                          | CLK_STATE_READY     | 0               | | DEV_BOARD0_HYP1_RXFLCLK_IN                                                          | CLK_STATE_READY     | 0               | | DEV_BOARD0_HYP1_RXPMCLK_OUT                                                         | CLK_STATE_READY     | 0               | | DEV_BOARD0_HYP1_TXFLCLK_OUT                                                         | CLK_STATE_READY     | 0               | | DEV_BOARD0_HYP1_TXPMCLK_IN                                                          | CLK_STATE_READY     | 0               | | DEV_BOARD0_I2C0_SCL_IN                                                              | CLK_STATE_READY     | 0               | | DEV_BOARD0_I2C0_SCL_OUT                                                             | CLK_STATE_READY     | 0               | | DEV_BOARD0_I2C1_SCL_IN                                                              | CLK_STATE_READY     | 0               | | DEV_BOARD0_I2C1_SCL_OUT                                                             | CLK_STATE_READY     | 0               | | DEV_BOARD0_I2C2_SCL_IN                                                              | CLK_STATE_READY     | 0               | | DEV_BOARD0_I2C2_SCL_OUT                                                             | CLK_STATE_READY     | 0               | | DEV_BOARD0_I2C3_SCL_IN                                                              | CLK_STATE_READY     | 0               | | DEV_BOARD0_I2C3_SCL_OUT                                                             | CLK_STATE_READY     | 0               | | DEV_BOARD0_I2C4_SCL_IN                                                              | CLK_STATE_READY     | 0               | | DEV_BOARD0_I2C4_SCL_OUT                                                             | CLK_STATE_READY     | 0               | | DEV_BOARD0_I2C5_SCL_IN                                                              | CLK_STATE_READY     | 0               | | DEV_BOARD0_I2C5_SCL_OUT                                                             | CLK_STATE_READY     | 0               | | DEV_BOARD0_I2C6_SCL_IN                                                              | CLK_STATE_READY     | 0               | | DEV_BOARD0_I2C6_SCL_OUT                                                             | CLK_STATE_READY     | 0               | | DEV_BOARD0_LED_CLK_OUT                                                              | CLK_STATE_READY     | 0               | | DEV_BOARD0_MCAN0_RX_OUT                                                             | CLK_STATE_READY     | 0               | | DEV_BOARD0_MCAN10_RX_OUT                                                            | CLK_STATE_READY     | 0               | | DEV_BOARD0_MCAN11_RX_OUT                                                            | CLK_STATE_READY     | 0               | | DEV_BOARD0_MCAN12_RX_OUT                                                            | CLK_STATE_READY     | 0               | | DEV_BOARD0_MCAN13_RX_OUT                                                            | CLK_STATE_READY     | 0               | | DEV_BOARD0_MCAN14_RX_OUT                                                            | CLK_STATE_READY     | 0               | | DEV_BOARD0_MCAN15_RX_OUT                                                            | CLK_STATE_READY     | 0               | | DEV_BOARD0_MCAN16_RX_OUT                                                            | CLK_STATE_READY     | 0               | | DEV_BOARD0_MCAN17_RX_OUT                                                            | CLK_STATE_READY     | 0               | | DEV_BOARD0_MCAN1_RX_OUT                                                             | CLK_STATE_READY     | 0               | | DEV_BOARD0_MCAN2_RX_OUT                                                             | CLK_STATE_READY     | 0               | | DEV_BOARD0_MCAN3_RX_OUT                                                             | CLK_STATE_READY     | 0               | | DEV_BOARD0_MCAN4_RX_OUT                                                             | CLK_STATE_READY     | 0               | | DEV_BOARD0_MCAN5_RX_OUT                                                             | CLK_STATE_READY     | 0               | | DEV_BOARD0_MCAN6_RX_OUT                                                             | CLK_STATE_READY     | 0               | | DEV_BOARD0_MCAN7_RX_OUT                                                             | CLK_STATE_READY     | 0               | | DEV_BOARD0_MCAN8_RX_OUT                                                             | CLK_STATE_READY     | 0               | | DEV_BOARD0_MCAN9_RX_OUT                                                             | CLK_STATE_READY     | 0               | | DEV_BOARD0_MCASP0_ACLKR_IN                                                          | CLK_STATE_READY     | 0               | | DEV_BOARD0_MCASP0_ACLKR_OUT                                                         | CLK_STATE_READY     | 0               | | DEV_BOARD0_MCASP0_ACLKX_IN                                                          | CLK_STATE_READY     | 0               | | DEV_BOARD0_MCASP0_ACLKX_OUT                                                         | CLK_STATE_READY     | 0               | | DEV_BOARD0_MCASP0_AFSR_OUT                                                          | CLK_STATE_READY     | 0               | | DEV_BOARD0_MCASP0_AFSX_OUT                                                          | CLK_STATE_READY     | 0               | | DEV_BOARD0_MCASP1_ACLKR_IN                                                          | CLK_STATE_READY     | 0               | | DEV_BOARD0_MCASP1_ACLKR_OUT                                                         | CLK_STATE_READY     | 0               | | DEV_BOARD0_MCASP1_ACLKX_IN                                                          | CLK_STATE_READY     | 0               | | DEV_BOARD0_MCASP1_ACLKX_OUT                                                         | CLK_STATE_READY     | 0               | | DEV_BOARD0_MCASP1_AFSR_OUT                                                          | CLK_STATE_READY     | 0               | | DEV_BOARD0_MCASP1_AFSX_OUT                                                          | CLK_STATE_READY     | 0               | | DEV_BOARD0_MCASP2_ACLKR_IN                                                          | CLK_STATE_READY     | 0               | | DEV_BOARD0_MCASP2_ACLKR_OUT                                                         | CLK_STATE_READY     | 0               | | DEV_BOARD0_MCASP2_ACLKX_IN                                                          | CLK_STATE_READY     | 0               | | DEV_BOARD0_MCASP2_ACLKX_OUT                                                         | CLK_STATE_READY     | 0               | | DEV_BOARD0_MCASP2_AFSR_OUT                                                          | CLK_STATE_READY     | 0               | | DEV_BOARD0_MCASP2_AFSX_OUT                                                          | CLK_STATE_READY     | 0               | | DEV_BOARD0_MCASP3_ACLKR_IN                                                          | CLK_STATE_READY     | 0               | | DEV_BOARD0_MCASP3_ACLKR_OUT                                                         | CLK_STATE_READY     | 0               | | DEV_BOARD0_MCASP3_ACLKX_IN                                                          | CLK_STATE_READY     | 0               | | DEV_BOARD0_MCASP3_ACLKX_OUT                                                         | CLK_STATE_READY     | 0               | | DEV_BOARD0_MCASP3_AFSR_OUT                                                          | CLK_STATE_READY     | 0               | | DEV_BOARD0_MCASP3_AFSX_OUT                                                          | CLK_STATE_READY     | 0               | | DEV_BOARD0_MCASP4_ACLKR_IN                                                          | CLK_STATE_READY     | 0               | | DEV_BOARD0_MCASP4_ACLKR_OUT                                                         | CLK_STATE_READY     | 0               | | DEV_BOARD0_MCASP4_ACLKX_IN                                                          | CLK_STATE_READY     | 0               | | DEV_BOARD0_MCASP4_ACLKX_OUT                                                         | CLK_STATE_READY     | 0               | | DEV_BOARD0_MCASP4_AFSR_OUT                                                          | CLK_STATE_READY     | 0               | | DEV_BOARD0_MCASP4_AFSX_OUT                                                          | CLK_STATE_READY     | 0               | | DEV_BOARD0_MCU_CLKOUT0_IN                                                           | CLK_STATE_READY     | 25000000        | | DEV_BOARD0_MCU_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT0_CLK5                  | CLK_STATE_READY     | 50000000        | | DEV_BOARD0_MCU_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT0_CLK10                 | CLK_STATE_READY     | 25000000        | | DEV_BOARD0_MCU_CPTS0_RFT_CLK_OUT                                                    | CLK_STATE_READY     | 0               | | DEV_BOARD0_MCU_EXT_REFCLK0_OUT                                                      | CLK_STATE_READY     | 0               | | DEV_BOARD0_MCU_HYPERBUS0_CK_IN                                                      | CLK_STATE_READY     | 0               | | DEV_BOARD0_MCU_HYPERBUS0_CKN_IN                                                     | CLK_STATE_READY     | 0               | | DEV_BOARD0_MCU_I2C0_SCL_IN                                                          | CLK_STATE_READY     | 0               | | DEV_BOARD0_MCU_I2C0_SCL_OUT                                                         | CLK_STATE_READY     | 0               | | DEV_BOARD0_MCU_I2C1_SCL_IN                                                          | CLK_STATE_READY     | 0               | | DEV_BOARD0_MCU_I2C1_SCL_OUT                                                         | CLK_STATE_READY     | 0               | | DEV_BOARD0_MCU_I3C0_SCL_IN                                                          | CLK_STATE_READY     | 0               | | DEV_BOARD0_MCU_I3C0_SCL_OUT                                                         | CLK_STATE_READY     | 0               | | DEV_BOARD0_MCU_I3C0_SDA_OUT                                                         | CLK_STATE_READY     | 0               | | DEV_BOARD0_MCU_MCAN0_RX_OUT                                                         | CLK_STATE_READY     | 0               | | DEV_BOARD0_MCU_MCAN1_RX_OUT                                                         | CLK_STATE_READY     | 0               | | DEV_BOARD0_MCU_MDIO0_MDC_IN                                                         | CLK_STATE_READY     | 0               | | DEV_BOARD0_MCU_OBSCLK0_IN                                                           | CLK_STATE_READY     | 1000000000      | | DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_MCU_OBSCLK_DIV_OUT0                                | CLK_STATE_READY     | 1000000000      | | DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT                            | CLK_STATE_READY     | 24000000        | | DEV_BOARD0_MCU_OSPI0_CLK_IN                                                         | CLK_STATE_READY     | 0               | | DEV_BOARD0_MCU_OSPI0_DQS_OUT                                                        | CLK_STATE_READY     | 0               | | DEV_BOARD0_MCU_OSPI0_LBCLKO_IN                                                      | CLK_STATE_READY     | 0               | | DEV_BOARD0_MCU_OSPI0_LBCLKO_OUT                                                     | CLK_STATE_READY     | 0               | | DEV_BOARD0_MCU_OSPI1_CLK_IN                                                         | CLK_STATE_READY     | 0               | | DEV_BOARD0_MCU_OSPI1_DQS_OUT                                                        | CLK_STATE_READY     | 0               | | DEV_BOARD0_MCU_OSPI1_LBCLKO_IN                                                      | CLK_STATE_READY     | 0               | | DEV_BOARD0_MCU_OSPI1_LBCLKO_OUT                                                     | CLK_STATE_READY     | 0               | | DEV_BOARD0_MCU_RGMII1_RXC_OUT                                                       | CLK_STATE_READY     | 0               | | DEV_BOARD0_MCU_RGMII1_TXC_IN                                                        | CLK_STATE_READY     | 0               | | DEV_BOARD0_MCU_RMII1_REF_CLK_OUT                                                    | CLK_STATE_READY     | 0               | | DEV_BOARD0_MCU_SPI0_CLK_IN                                                          | CLK_STATE_READY     | 0               | | DEV_BOARD0_MCU_SPI0_CLK_OUT                                                         | CLK_STATE_READY     | 0               | | DEV_BOARD0_MCU_SPI1_CLK_IN                                                          | CLK_STATE_READY     | 0               | | DEV_BOARD0_MCU_SPI1_CLK_OUT                                                         | CLK_STATE_READY     | 0               | | DEV_BOARD0_MCU_SYSCLKOUT0_IN                                                        | CLK_STATE_READY     | 250000000       | | DEV_BOARD0_MDIO0_MDC_IN                                                             | CLK_STATE_READY     | 0               | | DEV_BOARD0_MDIO1_MDC_IN                                                             | CLK_STATE_READY     | 0               | | DEV_BOARD0_MMC1_CLKLB_IN                                                            | CLK_STATE_READY     | 0               | | DEV_BOARD0_MMC1_CLKLB_OUT                                                           | CLK_STATE_READY     | 0               | | DEV_BOARD0_MMC1_CLK_IN                                                              | CLK_STATE_READY     | 0               | | DEV_BOARD0_MMC1_CLK_OUT                                                             | CLK_STATE_READY     | 0               | | DEV_BOARD0_OBSCLK0_IN                                                               | CLK_STATE_READY     | 500000000       | | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK                      | CLK_STATE_READY     | 500000000       | | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT0_CLK                      | CLK_STATE_READY     | 192000000       | | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK                      | CLK_STATE_READY     | 600000000       | | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT0_CLK                      | CLK_STATE_READY     | 250000000       | | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK                      | CLK_STATE_READY     | 196608000       | | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_5_HSDIVOUT0_CLK                      | CLK_STATE_READY     | 400000000       | | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_6_HSDIVOUT0_CLK                      | CLK_STATE_READY     | 800000000       | | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_26_HSDIVOUT0_CLK                     | CLK_STATE_READY     | 1066500000      | | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_27_HSDIVOUT0_CLK                     | CLK_STATE_READY     | 1066500000      | | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_28_HSDIVOUT0_CLK                     | CLK_STATE_READY     | 1066500000      | | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_12_HSDIVOUT0_CLK                     | CLK_STATE_READY     | 1066500000      | | DEV_BOARD0_OBSCLK0_IN_PARENT_OBSCLK1_MUX_OUT0                                       | CLK_STATE_NOT_READY | 0               | | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV2_16FFT_MAIN_14_HSDIVOUT0_CLK                     | CLK_STATE_READY     | 1000000000      | | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK                     | CLK_STATE_READY     | 594000000       | | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT0_CLK                     | CLK_STATE_READY     | 594000000       | | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_19_HSDIVOUT0_CLK                     | CLK_STATE_READY     | 600000000       | | DEV_BOARD0_OBSCLK0_IN_PARENT_UFSHCI2P1SS_16FFC_MAIN_0_UFSHCI_MPHY_TX_REF_SYMBOLCLK  | CLK_STATE_NOT_READY | 0               | | DEV_BOARD0_OBSCLK0_IN_PARENT_UFSHCI2P1SS_16FFC_MAIN_0_UFSHCI_MPHY_M31_VCO_19P2M_CLK | CLK_STATE_NOT_READY | 0               | | DEV_BOARD0_OBSCLK0_IN_PARENT_UFSHCI2P1SS_16FFC_MAIN_0_UFSHCI_MPHY_M31_VCO_26M_CLK   | CLK_STATE_NOT_READY | 0               | | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_25_HSDIVOUT0_CLK                     | CLK_STATE_READY     | 480000000       | | DEV_BOARD0_OBSCLK0_IN_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3                        | CLK_STATE_READY     | 0               | | DEV_BOARD0_OBSCLK0_IN_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK           | CLK_STATE_READY     | 12500000        | | DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_LPXOSC_CLKOUT                                | CLK_STATE_READY     | 32768           | | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK_DUP0                 | CLK_STATE_READY     | 500000000       | | DEV_BOARD0_OBSCLK0_IN_PARENT_BOARD_0_HFOSC1_CLK_OUT                                 | CLK_STATE_READY     | 0               | | DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT                                | CLK_STATE_READY     | 24000000        | | DEV_BOARD0_OBSCLK1_IN                                                               | CLK_STATE_READY     | 500000000       | | DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK                      | CLK_STATE_READY     | 500000000       | | DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT0_CLK                      | CLK_STATE_READY     | 192000000       | | DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK                      | CLK_STATE_READY     | 600000000       | | DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT0_CLK                      | CLK_STATE_READY     | 250000000       | | DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK                      | CLK_STATE_READY     | 196608000       | | DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV1_16FFT_MAIN_5_HSDIVOUT0_CLK                      | CLK_STATE_READY     | 400000000       | | DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV0_16FFT_MAIN_6_HSDIVOUT0_CLK                      | CLK_STATE_READY     | 800000000       | | DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV0_16FFT_MAIN_26_HSDIVOUT0_CLK                     | CLK_STATE_READY     | 1066500000      | | DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV0_16FFT_MAIN_27_HSDIVOUT0_CLK                     | CLK_STATE_READY     | 1066500000      | | DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV0_16FFT_MAIN_28_HSDIVOUT0_CLK                     | CLK_STATE_READY     | 1066500000      | | DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV0_16FFT_MAIN_12_HSDIVOUT0_CLK                     | CLK_STATE_READY     | 1066500000      | | DEV_BOARD0_OBSCLK1_IN_PARENT_OBSCLK1_MUX_OUT0                                       | CLK_STATE_NOT_READY | 0               | | DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV2_16FFT_MAIN_14_HSDIVOUT0_CLK                     | CLK_STATE_READY     | 1000000000      | | DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK                     | CLK_STATE_READY     | 594000000       | | DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT0_CLK                     | CLK_STATE_READY     | 594000000       | | DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV1_16FFT_MAIN_19_HSDIVOUT0_CLK                     | CLK_STATE_READY     | 600000000       | | DEV_BOARD0_OBSCLK1_IN_PARENT_UFSHCI2P1SS_16FFC_MAIN_0_UFSHCI_MPHY_TX_REF_SYMBOLCLK  | CLK_STATE_NOT_READY | 0               | | DEV_BOARD0_OBSCLK1_IN_PARENT_UFSHCI2P1SS_16FFC_MAIN_0_UFSHCI_MPHY_M31_VCO_19P2M_CLK | CLK_STATE_NOT_READY | 0               | | DEV_BOARD0_OBSCLK1_IN_PARENT_UFSHCI2P1SS_16FFC_MAIN_0_UFSHCI_MPHY_M31_VCO_26M_CLK   | CLK_STATE_NOT_READY | 0               | | DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV1_16FFT_MAIN_25_HSDIVOUT0_CLK                     | CLK_STATE_READY     | 480000000       | | DEV_BOARD0_OBSCLK1_IN_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3                        | CLK_STATE_READY     | 0               | | DEV_BOARD0_OBSCLK1_IN_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK           | CLK_STATE_READY     | 12500000        | | DEV_BOARD0_OBSCLK1_IN_PARENT_GLUELOGIC_LPXOSC_CLKOUT                                | CLK_STATE_READY     | 32768           | | DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK_DUP0                 | CLK_STATE_READY     | 500000000       | | DEV_BOARD0_OBSCLK1_IN_PARENT_BOARD_0_HFOSC1_CLK_OUT                                 | CLK_STATE_READY     | 0               | | DEV_BOARD0_OBSCLK1_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT                                | CLK_STATE_READY     | 24000000        | | DEV_BOARD0_PCIE_REFCLK0_N_OUT_IN                                                    | CLK_STATE_READY     | 0               | | DEV_BOARD0_PCIE_REFCLK0_P_OUT_IN                                                    | CLK_STATE_READY     | 0               | | DEV_BOARD0_PCIE_REFCLK1_N_OUT_IN                                                    | CLK_STATE_READY     | 0               | | DEV_BOARD0_PCIE_REFCLK1_P_OUT_IN                                                    | CLK_STATE_READY     | 0               | | DEV_BOARD0_PCIE_REFCLK2_N_OUT_IN                                                    | CLK_STATE_READY     | 0               | | DEV_BOARD0_PCIE_REFCLK2_P_OUT_IN                                                    | CLK_STATE_READY     | 0               | | DEV_BOARD0_PCIE_REFCLK3_N_OUT_IN                                                    | CLK_STATE_READY     | 0               | | DEV_BOARD0_PCIE_REFCLK3_P_OUT_IN                                                    | CLK_STATE_READY     | 0               | | DEV_BOARD0_RGMII1_RXC_OUT                                                           | CLK_STATE_READY     | 0               | | DEV_BOARD0_RGMII1_TXC_IN                                                            | CLK_STATE_READY     | 0               | | DEV_BOARD0_RMII_REF_CLK_OUT                                                         | CLK_STATE_READY     | 0               | | DEV_BOARD0_SERDES0_REFCLK_N_IN                                                      | CLK_STATE_READY     | 0               | | DEV_BOARD0_SERDES0_REFCLK_N_OUT                                                     | CLK_STATE_READY     | 0               | | DEV_BOARD0_SERDES0_REFCLK_P_IN                                                      | CLK_STATE_READY     | 0               | | DEV_BOARD0_SERDES0_REFCLK_P_OUT                                                     | CLK_STATE_READY     | 0               | | DEV_BOARD0_SERDES1_REFCLK_N_IN                                                      | CLK_STATE_READY     | 0               | | DEV_BOARD0_SERDES1_REFCLK_N_OUT                                                     | CLK_STATE_READY     | 0               | | DEV_BOARD0_SERDES1_REFCLK_P_IN                                                      | CLK_STATE_READY     | 0               | | DEV_BOARD0_SERDES1_REFCLK_P_OUT                                                     | CLK_STATE_READY     | 0               | | DEV_BOARD0_SERDES2_REFCLK_N_IN                                                      | CLK_STATE_READY     | 0               | | DEV_BOARD0_SERDES2_REFCLK_N_OUT                                                     | CLK_STATE_READY     | 0               | | DEV_BOARD0_SERDES2_REFCLK_P_IN                                                      | CLK_STATE_READY     | 0               | | DEV_BOARD0_SERDES2_REFCLK_P_OUT                                                     | CLK_STATE_READY     | 0               | | DEV_BOARD0_SERDES4_REFCLK_N_IN                                                      | CLK_STATE_READY     | 0               | | DEV_BOARD0_SERDES4_REFCLK_N_OUT                                                     | CLK_STATE_READY     | 0               | | DEV_BOARD0_SERDES4_REFCLK_P_IN                                                      | CLK_STATE_READY     | 0               | | DEV_BOARD0_SERDES4_REFCLK_P_OUT                                                     | CLK_STATE_READY     | 0               | | DEV_BOARD0_SPI0_CLK_IN                                                              | CLK_STATE_READY     | 0               | | DEV_BOARD0_SPI0_CLK_OUT                                                             | CLK_STATE_READY     | 0               | | DEV_BOARD0_SPI1_CLK_IN                                                              | CLK_STATE_READY     | 0               | | DEV_BOARD0_SPI1_CLK_OUT                                                             | CLK_STATE_READY     | 0               | | DEV_BOARD0_SPI2_CLK_IN                                                              | CLK_STATE_READY     | 0               | | DEV_BOARD0_SPI2_CLK_OUT                                                             | CLK_STATE_READY     | 0               | | DEV_BOARD0_SPI3_CLK_IN                                                              | CLK_STATE_READY     | 0               | | DEV_BOARD0_SPI3_CLK_OUT                                                             | CLK_STATE_READY     | 0               | | DEV_BOARD0_SPI5_CLK_IN                                                              | CLK_STATE_READY     | 0               | | DEV_BOARD0_SPI5_CLK_OUT                                                             | CLK_STATE_READY     | 0               | | DEV_BOARD0_SPI6_CLK_IN                                                              | CLK_STATE_READY     | 0               | | DEV_BOARD0_SPI6_CLK_OUT                                                             | CLK_STATE_READY     | 0               | | DEV_BOARD0_SPI7_CLK_IN                                                              | CLK_STATE_READY     | 0               | | DEV_BOARD0_SPI7_CLK_OUT                                                             | CLK_STATE_READY     | 0               | | DEV_BOARD0_SYSCLKOUT0_IN                                                            | CLK_STATE_READY     | 125000000       | | DEV_BOARD0_TCK_OUT                                                                  | CLK_STATE_READY     | 0               | | DEV_BOARD0_TRC_CLK_IN                                                               | CLK_STATE_READY     | 0               | | DEV_BOARD0_UFS0_REF_CLK_IN                                                          | CLK_STATE_READY     | 0               | | DEV_BOARD0_VOUT0_EXTPCLKIN_OUT                                                      | CLK_STATE_READY     | 0               | | DEV_BOARD0_VOUT0_PCLK_IN                                                            | CLK_STATE_READY     | 600000000       | | DEV_BOARD0_WKUP_I2C0_SCL_IN                                                         | CLK_STATE_READY     | 0               | | DEV_BOARD0_WKUP_I2C0_SCL_OUT                                                        | CLK_STATE_READY     | 0               | | DEV_BOARD0_HFOSC1_CLK_OUT                                                           | CLK_STATE_READY     | 0               | 0    | DEV_CMPEVENT_INTRTR0_INTR_CLK                                                       | CLK_STATE_READY     | 125000000       | 0    | DEV_CODEC0_VPU_ACLK_CLK                                                             | CLK_STATE_READY     | 600000000       | 1    | DEV_CODEC0_VPU_BCLK_CLK                                                             | CLK_STATE_READY     | 400000000       | 2    | DEV_CODEC0_VPU_CCLK_CLK                                                             | CLK_STATE_READY     | 600000000       | 3    | DEV_CODEC0_VPU_PCLK_CLK                                                             | CLK_STATE_READY     | 600000000       | 0    | DEV_CODEC1_VPU_ACLK_CLK                                                             | CLK_STATE_READY     | 600000000       | 1    | DEV_CODEC1_VPU_BCLK_CLK                                                             | CLK_STATE_READY     | 400000000       | 2    | DEV_CODEC1_VPU_CCLK_CLK                                                             | CLK_STATE_READY     | 600000000       | 3    | DEV_CODEC1_VPU_PCLK_CLK                                                             | CLK_STATE_READY     | 600000000       | 3    | DEV_COMPUTE_CLUSTER0_C71SS0_C7X_CLK                                                 | CLK_STATE_READY     | 1000000000      | 4    | DEV_COMPUTE_CLUSTER0_C71SS0_C7X_DIVH_CLK4_OBSCLK_OUT_CLK                            | CLK_STATE_READY     | 0               | 0    | DEV_COMPUTE_CLUSTER0_C71SS0_CORE0_C7X_CLK                                           | CLK_STATE_READY     | 1000000000      | 2    | DEV_COMPUTE_CLUSTER0_C71SS0_CORE0_PLL_CTRL_CLK_CLK                                  | CLK_STATE_READY     | 500000000       | 3    | DEV_COMPUTE_CLUSTER0_C71SS1_C7X_CLK                                                 | CLK_STATE_READY     | 1000000000      | 0    | DEV_COMPUTE_CLUSTER0_C71SS1_CORE0_C7X_CLK                                           | CLK_STATE_READY     | 1000000000      | 2    | DEV_COMPUTE_CLUSTER0_C71SS1_CORE0_PLL_CTRL_CLK_CLK                                  | CLK_STATE_READY     | 500000000       | 3    | DEV_COMPUTE_CLUSTER0_C71SS2_C7X_CLK                                                 | CLK_STATE_READY     | 1000000000      | 0    | DEV_COMPUTE_CLUSTER0_C71SS2_CORE0_C7X_CLK                                           | CLK_STATE_READY     | 1000000000      | 3    | DEV_COMPUTE_CLUSTER0_C71SS3_C7X_CLK                                                 | CLK_STATE_READY     | 1000000000      | 0    | DEV_COMPUTE_CLUSTER0_C71SS3_CORE0_C7X_CLK                                           | CLK_STATE_READY     | 1000000000      | 1    | DEV_COMPUTE_CLUSTER0_CORE_CORE_PSIL_LEAF_CLK                                        | CLK_STATE_READY     | 500000000       | 0    | DEV_COMPUTE_CLUSTER0_DEBUG_WRAP_0_CLK1_CLK_CLK                                      | CLK_STATE_READY     | 1000000000      | 1    | DEV_COMPUTE_CLUSTER0_DEBUG_WRAP_0_CLK2_CLK_CLK                                      | CLK_STATE_READY     | 500000000       | 0    | DEV_COMPUTE_CLUSTER0_GIC500SS_VCLK_CLK                                              | CLK_STATE_READY     | 500000000       | 0    | DEV_CPSW1_CPPI_CLK_CLK                                                              | CLK_STATE_READY     | 320000000       | 1    | DEV_CPSW1_CPTS_GENF0                                                                | CLK_STATE_READY     | 0               | 3    | DEV_CPSW1_CPTS_RFT_CLK                                                              | CLK_STATE_READY     | 200000000       | 4    | DEV_CPSW1_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK                     | CLK_STATE_READY     | 250000000       | 5    | DEV_CPSW1_CPTS_RFT_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK                   | CLK_STATE_READY     | 200000000       | 6    | DEV_CPSW1_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT                         | CLK_STATE_READY     | 0               | 7    | DEV_CPSW1_CPTS_RFT_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT                             | CLK_STATE_READY     | 0               | 8    | DEV_CPSW1_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                           | CLK_STATE_READY     | 0               | 9    | DEV_CPSW1_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT                               | CLK_STATE_READY     | 0               | 10    | DEV_CPSW1_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN0_TXMCLK                    | CLK_STATE_READY     | 0               | 11    | DEV_CPSW1_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN1_TXMCLK                    | CLK_STATE_READY     | 0               | 12    | DEV_CPSW1_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN2_TXMCLK                    | CLK_STATE_READY     | 0               | 13    | DEV_CPSW1_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN3_TXMCLK                    | CLK_STATE_READY     | 0               | 14    | DEV_CPSW1_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN0_TXMCLK                    | CLK_STATE_READY     | 0               | 15    | DEV_CPSW1_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN1_TXMCLK                    | CLK_STATE_READY     | 0               | 16    | DEV_CPSW1_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP1_LN2_TXMCLK                    | CLK_STATE_READY     | 0               | 17    | DEV_CPSW1_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP3_LN2_TXMCLK                    | CLK_STATE_READY     | 0               | 18    | DEV_CPSW1_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK                      | CLK_STATE_READY     | 500000000       | 19    | DEV_CPSW1_CPTS_RFT_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK             | CLK_STATE_READY     | 500000000       | 20    | DEV_CPSW1_GMII1_MR_CLK                                                              | CLK_STATE_READY     | 25000000        | 21    | DEV_CPSW1_GMII1_MT_CLK                                                              | CLK_STATE_READY     | 25000000        | 22    | DEV_CPSW1_GMII_RFT_CLK                                                              | CLK_STATE_READY     | 125000000       | 23    | DEV_CPSW1_MDIO_MDCLK_O                                                              | CLK_STATE_READY     | 0               | 24    | DEV_CPSW1_RGMII1_RXC_I                                                              | CLK_STATE_READY     | 0               | 26    | DEV_CPSW1_RGMII1_TXC_O                                                              | CLK_STATE_READY     | 0               | 27    | DEV_CPSW1_RGMII_MHZ_250_CLK                                                         | CLK_STATE_READY     | 250000000       | 28    | DEV_CPSW1_RGMII_MHZ_50_CLK                                                          | CLK_STATE_READY     | 50000000        | 29    | DEV_CPSW1_RGMII_MHZ_5_CLK                                                           | CLK_STATE_READY     | 5000000         | 30    | DEV_CPSW1_RMII_MHZ_50_CLK                                                           | CLK_STATE_READY     | 0               | 0    | DEV_CPSW_9XUSS_J7AM0_CPPI_CLK_CLK                                                   | CLK_STATE_READY     | 320000000       | 1    | DEV_CPSW_9XUSS_J7AM0_CPTS_GENF0                                                     | CLK_STATE_READY     | 0               | 3    | DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK                                                   | CLK_STATE_READY     | 250000000       | 4    | DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK          | CLK_STATE_READY     | 250000000       | 5    | DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK        | CLK_STATE_READY     | 200000000       | 6    | DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT              | CLK_STATE_READY     | 0               | 7    | DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT                  | CLK_STATE_READY     | 0               | 8    | DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                | CLK_STATE_READY     | 0               | 9    | DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT                    | CLK_STATE_READY     | 0               | 10    | DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN0_TXMCLK         | CLK_STATE_READY     | 0               | 11    | DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN1_TXMCLK         | CLK_STATE_READY     | 0               | 12    | DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN2_TXMCLK         | CLK_STATE_READY     | 0               | 13    | DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN3_TXMCLK         | CLK_STATE_READY     | 0               | 14    | DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN0_TXMCLK         | CLK_STATE_READY     | 0               | 15    | DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN1_TXMCLK         | CLK_STATE_READY     | 0               | 16    | DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP1_LN2_TXMCLK         | CLK_STATE_READY     | 0               | 17    | DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP3_LN2_TXMCLK         | CLK_STATE_READY     | 0               | 18    | DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK           | CLK_STATE_READY     | 500000000       | 19    | DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK  | CLK_STATE_READY     | 500000000       | 22    | DEV_CPSW_9XUSS_J7AM0_GMII1_MR_CLK                                                   | CLK_STATE_READY     | 25000000        | 23    | DEV_CPSW_9XUSS_J7AM0_GMII1_MT_CLK                                                   | CLK_STATE_READY     | 25000000        | 24    | DEV_CPSW_9XUSS_J7AM0_GMII2_MR_CLK                                                   | CLK_STATE_READY     | 25000000        | 25    | DEV_CPSW_9XUSS_J7AM0_GMII2_MT_CLK                                                   | CLK_STATE_READY     | 25000000        | 26    | DEV_CPSW_9XUSS_J7AM0_GMII3_MR_CLK                                                   | CLK_STATE_READY     | 25000000        | 27    | DEV_CPSW_9XUSS_J7AM0_GMII3_MT_CLK                                                   | CLK_STATE_READY     | 25000000        | 28    | DEV_CPSW_9XUSS_J7AM0_GMII4_MR_CLK                                                   | CLK_STATE_READY     | 25000000        | 29    | DEV_CPSW_9XUSS_J7AM0_GMII4_MT_CLK                                                   | CLK_STATE_READY     | 25000000        | 30    | DEV_CPSW_9XUSS_J7AM0_GMII5_MR_CLK                                                   | CLK_STATE_READY     | 25000000        | 31    | DEV_CPSW_9XUSS_J7AM0_GMII5_MT_CLK                                                   | CLK_STATE_READY     | 25000000        | 32    | DEV_CPSW_9XUSS_J7AM0_GMII6_MR_CLK                                                   | CLK_STATE_READY     | 25000000        | 33    | DEV_CPSW_9XUSS_J7AM0_GMII6_MT_CLK                                                   | CLK_STATE_READY     | 25000000        | 34    | DEV_CPSW_9XUSS_J7AM0_GMII7_MR_CLK                                                   | CLK_STATE_READY     | 25000000        | 35    | DEV_CPSW_9XUSS_J7AM0_GMII7_MT_CLK                                                   | CLK_STATE_READY     | 25000000        | 36    | DEV_CPSW_9XUSS_J7AM0_GMII8_MR_CLK                                                   | CLK_STATE_READY     | 25000000        | 37    | DEV_CPSW_9XUSS_J7AM0_GMII8_MT_CLK                                                   | CLK_STATE_READY     | 25000000        | 38    | DEV_CPSW_9XUSS_J7AM0_GMII_RFT_CLK                                                   | CLK_STATE_READY     | 125000000       | 39    | DEV_CPSW_9XUSS_J7AM0_MDIO_MDCLK_O                                                   | CLK_STATE_READY     | 0               | 56    | DEV_CPSW_9XUSS_J7AM0_RGMII_MHZ_250_CLK                                              | CLK_STATE_READY     | 250000000       | 57    | DEV_CPSW_9XUSS_J7AM0_RGMII_MHZ_50_CLK                                               | CLK_STATE_READY     | 50000000        | 58    | DEV_CPSW_9XUSS_J7AM0_RGMII_MHZ_5_CLK                                                | CLK_STATE_READY     | 5000000         | 59    | DEV_CPSW_9XUSS_J7AM0_RMII_MHZ_50_CLK                                                | CLK_STATE_READY     | 0               | 60    | DEV_CPSW_9XUSS_J7AM0_SERDES1_REFCLK                                                 | CLK_STATE_READY     | 0               | 61    | DEV_CPSW_9XUSS_J7AM0_SERDES1_RXCLK                                                  | CLK_STATE_READY     | 0               | 62    | DEV_CPSW_9XUSS_J7AM0_SERDES1_RXFCLK                                                 | CLK_STATE_READY     | 0               | 63    | DEV_CPSW_9XUSS_J7AM0_SERDES1_TXCLK                                                  | CLK_STATE_READY     | 0               | 64    | DEV_CPSW_9XUSS_J7AM0_SERDES1_TXFCLK                                                 | CLK_STATE_READY     | 0               | 65    | DEV_CPSW_9XUSS_J7AM0_SERDES1_TXMCLK                                                 | CLK_STATE_READY     | 0               | 66    | DEV_CPSW_9XUSS_J7AM0_SERDES2_REFCLK                                                 | CLK_STATE_READY     | 0               | 67    | DEV_CPSW_9XUSS_J7AM0_SERDES2_RXCLK                                                  | CLK_STATE_READY     | 0               | 68    | DEV_CPSW_9XUSS_J7AM0_SERDES2_RXFCLK                                                 | CLK_STATE_READY     | 0               | 69    | DEV_CPSW_9XUSS_J7AM0_SERDES2_TXCLK                                                  | CLK_STATE_READY     | 0               | 70    | DEV_CPSW_9XUSS_J7AM0_SERDES2_TXFCLK                                                 | CLK_STATE_READY     | 0               | 71    | DEV_CPSW_9XUSS_J7AM0_SERDES2_TXMCLK                                                 | CLK_STATE_READY     | 0               | 72    | DEV_CPSW_9XUSS_J7AM0_SERDES3_REFCLK                                                 | CLK_STATE_READY     | 0               | 73    | DEV_CPSW_9XUSS_J7AM0_SERDES3_RXCLK                                                  | CLK_STATE_READY     | 0               | 74    | DEV_CPSW_9XUSS_J7AM0_SERDES3_RXFCLK                                                 | CLK_STATE_READY     | 0               | 75    | DEV_CPSW_9XUSS_J7AM0_SERDES3_TXCLK                                                  | CLK_STATE_READY     | 0               | 76    | DEV_CPSW_9XUSS_J7AM0_SERDES3_TXFCLK                                                 | CLK_STATE_READY     | 0               | 77    | DEV_CPSW_9XUSS_J7AM0_SERDES3_TXMCLK                                                 | CLK_STATE_READY     | 0               | 78    | DEV_CPSW_9XUSS_J7AM0_SERDES4_REFCLK                                                 | CLK_STATE_READY     | 0               | 79    | DEV_CPSW_9XUSS_J7AM0_SERDES4_RXCLK                                                  | CLK_STATE_READY     | 0               | 80    | DEV_CPSW_9XUSS_J7AM0_SERDES4_RXFCLK                                                 | CLK_STATE_READY     | 0               | 81    | DEV_CPSW_9XUSS_J7AM0_SERDES4_TXCLK                                                  | CLK_STATE_READY     | 0               | 82    | DEV_CPSW_9XUSS_J7AM0_SERDES4_TXFCLK                                                 | CLK_STATE_READY     | 0               | 83    | DEV_CPSW_9XUSS_J7AM0_SERDES4_TXMCLK                                                 | CLK_STATE_READY     | 0               | 84    | DEV_CPSW_9XUSS_J7AM0_SERDES5_REFCLK                                                 | CLK_STATE_READY     | 0               | 85    | DEV_CPSW_9XUSS_J7AM0_SERDES5_RXCLK                                                  | CLK_STATE_READY     | 0               | 86    | DEV_CPSW_9XUSS_J7AM0_SERDES5_RXFCLK                                                 | CLK_STATE_READY     | 0               | 87    | DEV_CPSW_9XUSS_J7AM0_SERDES5_TXCLK                                                  | CLK_STATE_READY     | 0               | 88    | DEV_CPSW_9XUSS_J7AM0_SERDES5_TXFCLK                                                 | CLK_STATE_READY     | 0               | 89    | DEV_CPSW_9XUSS_J7AM0_SERDES5_TXMCLK                                                 | CLK_STATE_READY     | 0               | 90    | DEV_CPSW_9XUSS_J7AM0_SERDES6_REFCLK                                                 | CLK_STATE_READY     | 0               | 91    | DEV_CPSW_9XUSS_J7AM0_SERDES6_RXCLK                                                  | CLK_STATE_READY     | 0               | 92    | DEV_CPSW_9XUSS_J7AM0_SERDES6_RXFCLK                                                 | CLK_STATE_READY     | 0               | 93    | DEV_CPSW_9XUSS_J7AM0_SERDES6_TXCLK                                                  | CLK_STATE_READY     | 0               | 94    | DEV_CPSW_9XUSS_J7AM0_SERDES6_TXFCLK                                                 | CLK_STATE_READY     | 0               | 95    | DEV_CPSW_9XUSS_J7AM0_SERDES6_TXMCLK                                                 | CLK_STATE_READY     | 0               | 96    | DEV_CPSW_9XUSS_J7AM0_SERDES7_REFCLK                                                 | CLK_STATE_READY     | 0               | 97    | DEV_CPSW_9XUSS_J7AM0_SERDES7_RXCLK                                                  | CLK_STATE_READY     | 0               | 98    | DEV_CPSW_9XUSS_J7AM0_SERDES7_RXFCLK                                                 | CLK_STATE_READY     | 0               | 99    | DEV_CPSW_9XUSS_J7AM0_SERDES7_TXCLK                                                  | CLK_STATE_READY     | 0               | | DEV_CPSW_9XUSS_J7AM0_SERDES7_TXFCLK                                                 | CLK_STATE_READY     | 0               | | DEV_CPSW_9XUSS_J7AM0_SERDES7_TXMCLK                                                 | CLK_STATE_READY     | 0               | | DEV_CPSW_9XUSS_J7AM0_SERDES8_REFCLK                                                 | CLK_STATE_READY     | 0               | | DEV_CPSW_9XUSS_J7AM0_SERDES8_RXCLK                                                  | CLK_STATE_READY     | 0               | | DEV_CPSW_9XUSS_J7AM0_SERDES8_RXFCLK                                                 | CLK_STATE_READY     | 0               | | DEV_CPSW_9XUSS_J7AM0_SERDES8_TXCLK                                                  | CLK_STATE_READY     | 0               | | DEV_CPSW_9XUSS_J7AM0_SERDES8_TXFCLK                                                 | CLK_STATE_READY     | 0               | | DEV_CPSW_9XUSS_J7AM0_SERDES8_TXMCLK                                                 | CLK_STATE_READY     | 0               | 0    | DEV_CPT2_AGGR0_VCLK_CLK                                                             | CLK_STATE_READY     | 250000000       | 0    | DEV_CPT2_AGGR1_VCLK_CLK                                                             | CLK_STATE_READY     | 250000000       | 0    | DEV_CPT2_AGGR2_VCLK_CLK                                                             | CLK_STATE_READY     | 250000000       | 0    | DEV_CPT2_AGGR3_VCLK_CLK                                                             | CLK_STATE_READY     | 250000000       | 0    | DEV_CPT2_AGGR4_VCLK_CLK                                                             | CLK_STATE_READY     | 250000000       | 0    | DEV_CPT2_AGGR5_VCLK_CLK                                                             | CLK_STATE_READY     | 250000000       | 0    | DEV_CSI_PSILSS0_MAIN_CLK                                                            | CLK_STATE_READY     | 125000000       | 0    | DEV_CSI_RX_IF0_MAIN_CLK_CLK                                                         | CLK_STATE_READY     | 500000000       | 1    | DEV_CSI_RX_IF0_PPI_D_RX_ULPS_ESC                                                    | CLK_STATE_READY     | 0               | 2    | DEV_CSI_RX_IF0_PPI_RX_BYTE_CLK                                                      | CLK_STATE_READY     | 0               | 3    | DEV_CSI_RX_IF0_VBUS_CLK_CLK                                                         | CLK_STATE_READY     | 250000000       | 4    | DEV_CSI_RX_IF0_VP_CLK_CLK                                                           | CLK_STATE_READY     | 720000000       | 0    | DEV_CSI_RX_IF1_MAIN_CLK_CLK                                                         | CLK_STATE_READY     | 500000000       | 1    | DEV_CSI_RX_IF1_PPI_D_RX_ULPS_ESC                                                    | CLK_STATE_READY     | 0               | 2    | DEV_CSI_RX_IF1_PPI_RX_BYTE_CLK                                                      | CLK_STATE_READY     | 0               | 3    | DEV_CSI_RX_IF1_VBUS_CLK_CLK                                                         | CLK_STATE_READY     | 250000000       | 4    | DEV_CSI_RX_IF1_VP_CLK_CLK                                                           | CLK_STATE_READY     | 720000000       | 0    | DEV_CSI_RX_IF2_MAIN_CLK_CLK                                                         | CLK_STATE_READY     | 500000000       | 1    | DEV_CSI_RX_IF2_PPI_D_RX_ULPS_ESC                                                    | CLK_STATE_READY     | 0               | 2    | DEV_CSI_RX_IF2_PPI_RX_BYTE_CLK                                                      | CLK_STATE_READY     | 0               | 3    | DEV_CSI_RX_IF2_VBUS_CLK_CLK                                                         | CLK_STATE_READY     | 250000000       | 4    | DEV_CSI_RX_IF2_VP_CLK_CLK                                                           | CLK_STATE_READY     | 720000000       | 2    | DEV_CSI_TX_IF_V2_0_DPHY_TXBYTECLKHS_CL_CLK                                          | CLK_STATE_READY     | 0               | 3    | DEV_CSI_TX_IF_V2_0_ESC_CLK_CLK                                                      | CLK_STATE_READY     | 20000000        | 4    | DEV_CSI_TX_IF_V2_0_MAIN_CLK_CLK                                                     | CLK_STATE_READY     | 500000000       | 5    | DEV_CSI_TX_IF_V2_0_VBUS_CLK_CLK                                                     | CLK_STATE_READY     | 250000000       | 2    | DEV_CSI_TX_IF_V2_1_DPHY_TXBYTECLKHS_CL_CLK                                          | CLK_STATE_READY     | 0               | 3    | DEV_CSI_TX_IF_V2_1_ESC_CLK_CLK                                                      | CLK_STATE_READY     | 20000000        | 4    | DEV_CSI_TX_IF_V2_1_MAIN_CLK_CLK                                                     | CLK_STATE_READY     | 500000000       | 5    | DEV_CSI_TX_IF_V2_1_VBUS_CLK_CLK                                                     | CLK_STATE_READY     | 250000000       | 0    | DEV_DCC0_DCC_CLKSRC0_CLK                                                            | CLK_STATE_READY     | 250000000       | 1    | DEV_DCC0_DCC_CLKSRC1_CLK                                                            | CLK_STATE_READY     | 200000000       | 2    | DEV_DCC0_DCC_CLKSRC2_CLK                                                            | CLK_STATE_READY     | 133333333       | 3    | DEV_DCC0_DCC_CLKSRC3_CLK                                                            | CLK_STATE_READY     | 80000000        | 4    | DEV_DCC0_DCC_CLKSRC4_CLK                                                            | CLK_STATE_READY     | 24000000        | 5    | DEV_DCC0_DCC_CLKSRC5_CLK                                                            | CLK_STATE_READY     | 0               | 6    | DEV_DCC0_DCC_CLKSRC6_CLK                                                            | CLK_STATE_READY     | 500000000       | 7    | DEV_DCC0_DCC_CLKSRC7_CLK                                                            | CLK_STATE_READY     | 0               | 8    | DEV_DCC0_DCC_INPUT00_CLK                                                            | CLK_STATE_READY     | 24000000        | 9    | DEV_DCC0_DCC_INPUT01_CLK                                                            | CLK_STATE_READY     | 0               | 10    | DEV_DCC0_DCC_INPUT02_CLK                                                            | CLK_STATE_READY     | 12500000        | 11    | DEV_DCC0_DCC_INPUT10_CLK                                                            | CLK_STATE_READY     | 250000000       | 12    | DEV_DCC0_VBUS_CLK                                                                   | CLK_STATE_READY     | 125000000       | 0    | DEV_DCC1_DCC_CLKSRC0_CLK                                                            | CLK_STATE_READY     | 50000000        | 1    | DEV_DCC1_DCC_CLKSRC1_CLK                                                            | CLK_STATE_READY     | 200000000       | 2    | DEV_DCC1_DCC_CLKSRC2_CLK                                                            | CLK_STATE_READY     | 200000000       | 3    | DEV_DCC1_DCC_CLKSRC3_CLK                                                            | CLK_STATE_READY     | 192000000       | 4    | DEV_DCC1_DCC_CLKSRC4_CLK                                                            | CLK_STATE_READY     | 320000000       | 5    | DEV_DCC1_DCC_CLKSRC5_CLK                                                            | CLK_STATE_READY     | 192000000       | 6    | DEV_DCC1_DCC_CLKSRC6_CLK                                                            | CLK_STATE_READY     | 192000000       | 7    | DEV_DCC1_DCC_CLKSRC7_CLK                                                            | CLK_STATE_READY     | 19200000        | 8    | DEV_DCC1_DCC_INPUT00_CLK                                                            | CLK_STATE_READY     | 24000000        | 9    | DEV_DCC1_DCC_INPUT01_CLK                                                            | CLK_STATE_READY     | 0               | 10    | DEV_DCC1_DCC_INPUT02_CLK                                                            | CLK_STATE_READY     | 12500000        | 11    | DEV_DCC1_DCC_INPUT10_CLK                                                            | CLK_STATE_READY     | 125000000       | 12    | DEV_DCC1_VBUS_CLK                                                                   | CLK_STATE_READY     | 125000000       | 0    | DEV_DCC2_DCC_CLKSRC0_CLK                                                            | CLK_STATE_READY     | 24000000        | 1    | DEV_DCC2_DCC_CLKSRC1_CLK                                                            | CLK_STATE_READY     | 20000000        | 3    | DEV_DCC2_DCC_CLKSRC3_CLK                                                            | CLK_STATE_READY     | 100000000       | 4    | DEV_DCC2_DCC_CLKSRC4_CLK                                                            | CLK_STATE_READY     | 225000000       | 5    | DEV_DCC2_DCC_CLKSRC5_CLK                                                            | CLK_STATE_READY     | 300000000       | 6    | DEV_DCC2_DCC_CLKSRC6_CLK                                                            | CLK_STATE_READY     | 200000000       | 7    | DEV_DCC2_DCC_CLKSRC7_CLK                                                            | CLK_STATE_READY     | 250000000       | 8    | DEV_DCC2_DCC_INPUT00_CLK                                                            | CLK_STATE_READY     | 24000000        | 9    | DEV_DCC2_DCC_INPUT01_CLK                                                            | CLK_STATE_READY     | 0               | 10    | DEV_DCC2_DCC_INPUT02_CLK                                                            | CLK_STATE_READY     | 12500000        | 11    | DEV_DCC2_DCC_INPUT10_CLK                                                            | CLK_STATE_READY     | 125000000       | 12    | DEV_DCC2_VBUS_CLK                                                                   | CLK_STATE_READY     | 125000000       | 0    | DEV_DCC3_DCC_CLKSRC0_CLK                                                            | CLK_STATE_READY     | 196608000       | 1    | DEV_DCC3_DCC_CLKSRC1_CLK                                                            | CLK_STATE_READY     | 200000000       | 2    | DEV_DCC3_DCC_CLKSRC2_CLK                                                            | CLK_STATE_READY     | 300000000       | 3    | DEV_DCC3_DCC_CLKSRC3_CLK                                                            | CLK_STATE_READY     | 500000000       | 5    | DEV_DCC3_DCC_CLKSRC5_CLK                                                            | CLK_STATE_READY     | 200000000       | 6    | DEV_DCC3_DCC_CLKSRC6_CLK                                                            | CLK_STATE_READY     | 250000000       | 7    | DEV_DCC3_DCC_CLKSRC7_CLK                                                            | CLK_STATE_READY     | 500000000       | 8    | DEV_DCC3_DCC_INPUT00_CLK                                                            | CLK_STATE_READY     | 24000000        | 9    | DEV_DCC3_DCC_INPUT01_CLK                                                            | CLK_STATE_READY     | 0               | 10    | DEV_DCC3_DCC_INPUT02_CLK                                                            | CLK_STATE_READY     | 12500000        | 11    | DEV_DCC3_DCC_INPUT10_CLK                                                            | CLK_STATE_READY     | 125000000       | 12    | DEV_DCC3_VBUS_CLK                                                                   | CLK_STATE_READY     | 125000000       | 0    | DEV_DCC4_DCC_CLKSRC0_CLK                                                            | CLK_STATE_READY     | 200000000       | 1    | DEV_DCC4_DCC_CLKSRC1_CLK                                                            | CLK_STATE_READY     | 266625000       | 2    | DEV_DCC4_DCC_CLKSRC2_CLK                                                            | CLK_STATE_READY     | 266625000       | 3    | DEV_DCC4_DCC_CLKSRC3_CLK                                                            | CLK_STATE_READY     | 266625000       | 4    | DEV_DCC4_DCC_CLKSRC4_CLK                                                            | CLK_STATE_READY     | 250000000       | 5    | DEV_DCC4_DCC_CLKSRC5_CLK                                                            | CLK_STATE_READY     | 250000000       | 6    | DEV_DCC4_DCC_CLKSRC6_CLK                                                            | CLK_STATE_READY     | 266625000       | 7    | DEV_DCC4_DCC_CLKSRC7_CLK                                                            | CLK_STATE_READY     | 297000000       | 8    | DEV_DCC4_DCC_INPUT00_CLK                                                            | CLK_STATE_READY     | 24000000        | 9    | DEV_DCC4_DCC_INPUT01_CLK                                                            | CLK_STATE_READY     | 0               | 10    | DEV_DCC4_DCC_INPUT02_CLK                                                            | CLK_STATE_READY     | 12500000        | 11    | DEV_DCC4_DCC_INPUT10_CLK                                                            | CLK_STATE_READY     | 250000000       | 12    | DEV_DCC4_VBUS_CLK                                                                   | CLK_STATE_READY     | 125000000       | 1    | DEV_DCC5_DCC_CLKSRC1_CLK                                                            | CLK_STATE_READY     | 300000000       | 2    | DEV_DCC5_DCC_CLKSRC2_CLK                                                            | CLK_STATE_READY     | 297000000       | 3    | DEV_DCC5_DCC_CLKSRC3_CLK                                                            | CLK_STATE_READY     | 240000000       | 4    | DEV_DCC5_DCC_CLKSRC4_CLK                                                            | CLK_STATE_READY     | 360000000       | 6    | DEV_DCC5_DCC_CLKSRC6_CLK                                                            | CLK_STATE_READY     | 0               | 7    | DEV_DCC5_DCC_CLKSRC7_CLK                                                            | CLK_STATE_READY     | 0               | 8    | DEV_DCC5_DCC_INPUT00_CLK                                                            | CLK_STATE_READY     | 24000000        | 9    | DEV_DCC5_DCC_INPUT01_CLK                                                            | CLK_STATE_READY     | 0               | 10    | DEV_DCC5_DCC_INPUT02_CLK                                                            | CLK_STATE_READY     | 12500000        | 11    | DEV_DCC5_DCC_INPUT10_CLK                                                            | CLK_STATE_READY     | 500000000       | 12    | DEV_DCC5_VBUS_CLK                                                                   | CLK_STATE_READY     | 125000000       | 0    | DEV_DCC6_DCC_CLKSRC0_CLK                                                            | CLK_STATE_READY     | 0               | 1    | DEV_DCC6_DCC_CLKSRC1_CLK                                                            | CLK_STATE_READY     | 0               | 2    | DEV_DCC6_DCC_CLKSRC2_CLK                                                            | CLK_STATE_READY     | 0               | 3    | DEV_DCC6_DCC_CLKSRC3_CLK                                                            | CLK_STATE_READY     | 0               | 4    | DEV_DCC6_DCC_CLKSRC4_CLK                                                            | CLK_STATE_READY     | 0               | 5    | DEV_DCC6_DCC_CLKSRC5_CLK                                                            | CLK_STATE_READY     | 0               | 6    | DEV_DCC6_DCC_CLKSRC6_CLK                                                            | CLK_STATE_READY     | 0               | 7    | DEV_DCC6_DCC_CLKSRC7_CLK                                                            | CLK_STATE_READY     | 0               | 8    | DEV_DCC6_DCC_INPUT00_CLK                                                            | CLK_STATE_READY     | 24000000        | 9    | DEV_DCC6_DCC_INPUT01_CLK                                                            | CLK_STATE_READY     | 0               | 10    | DEV_DCC6_DCC_INPUT02_CLK                                                            | CLK_STATE_READY     | 12500000        | 11    | DEV_DCC6_DCC_INPUT10_CLK                                                            | CLK_STATE_READY     | 125000000       | 12    | DEV_DCC6_VBUS_CLK                                                                   | CLK_STATE_READY     | 125000000       | 0    | DEV_DCC7_DCC_CLKSRC0_CLK                                                            | CLK_STATE_READY     | 0               | 1    | DEV_DCC7_DCC_CLKSRC1_CLK                                                            | CLK_STATE_READY     | 0               | 2    | DEV_DCC7_DCC_CLKSRC2_CLK                                                            | CLK_STATE_READY     | 250000000       | 5    | DEV_DCC7_DCC_CLKSRC5_CLK                                                            | CLK_STATE_READY     | 0               | 6    | DEV_DCC7_DCC_CLKSRC6_CLK                                                            | CLK_STATE_READY     | 120000000       | 7    | DEV_DCC7_DCC_CLKSRC7_CLK                                                            | CLK_STATE_READY     | 0               | 8    | DEV_DCC7_DCC_INPUT00_CLK                                                            | CLK_STATE_READY     | 24000000        | 9    | DEV_DCC7_DCC_INPUT01_CLK                                                            | CLK_STATE_READY     | 0               | 10    | DEV_DCC7_DCC_INPUT02_CLK                                                            | CLK_STATE_READY     | 12500000        | 11    | DEV_DCC7_DCC_INPUT10_CLK                                                            | CLK_STATE_READY     | 250000000       | 12    | DEV_DCC7_VBUS_CLK                                                                   | CLK_STATE_READY     | 125000000       | 0    | DEV_DCC8_DCC_CLKSRC0_CLK                                                            | CLK_STATE_READY     | 32000           | 1    | DEV_DCC8_DCC_CLKSRC1_CLK                                                            | CLK_STATE_READY     | 32768           | 2    | DEV_DCC8_DCC_CLKSRC2_CLK                                                            | CLK_STATE_READY     | 0               | 3    | DEV_DCC8_DCC_CLKSRC3_CLK                                                            | CLK_STATE_READY     | 0               | 4    | DEV_DCC8_DCC_CLKSRC4_CLK                                                            | CLK_STATE_READY     | 0               | 5    | DEV_DCC8_DCC_CLKSRC5_CLK                                                            | CLK_STATE_READY     | 0               | 6    | DEV_DCC8_DCC_CLKSRC6_CLK                                                            | CLK_STATE_READY     | 250000000       | 7    | DEV_DCC8_DCC_CLKSRC7_CLK                                                            | CLK_STATE_READY     | 192307692       | 8    | DEV_DCC8_DCC_INPUT00_CLK                                                            | CLK_STATE_READY     | 24000000        | 9    | DEV_DCC8_DCC_INPUT01_CLK                                                            | CLK_STATE_READY     | 0               | 10    | DEV_DCC8_DCC_INPUT02_CLK                                                            | CLK_STATE_READY     | 12500000        | 11    | DEV_DCC8_DCC_INPUT10_CLK                                                            | CLK_STATE_READY     | 250000000       | 12    | DEV_DCC8_VBUS_CLK                                                                   | CLK_STATE_READY     | 125000000       | 0    | DEV_DCC9_DCC_CLKSRC0_CLK                                                            | CLK_STATE_READY     | 250000000       | 1    | DEV_DCC9_DCC_CLKSRC1_CLK                                                            | CLK_STATE_READY     | 156250000       | 2    | DEV_DCC9_DCC_CLKSRC2_CLK                                                            | CLK_STATE_READY     | 0               | 3    | DEV_DCC9_DCC_CLKSRC3_CLK                                                            | CLK_STATE_READY     | 0               | 4    | DEV_DCC9_DCC_CLKSRC4_CLK                                                            | CLK_STATE_READY     | 0               | 5    | DEV_DCC9_DCC_CLKSRC5_CLK                                                            | CLK_STATE_READY     | 294912000       | 6    | DEV_DCC9_DCC_CLKSRC6_CLK                                                            | CLK_STATE_READY     | 196608000       | 8    | DEV_DCC9_DCC_INPUT00_CLK                                                            | CLK_STATE_READY     | 24000000        | 9    | DEV_DCC9_DCC_INPUT01_CLK                                                            | CLK_STATE_READY     | 0               | 10    | DEV_DCC9_DCC_INPUT02_CLK                                                            | CLK_STATE_READY     | 12500000        | 11    | DEV_DCC9_DCC_INPUT10_CLK                                                            | CLK_STATE_READY     | 250000000       | 12    | DEV_DCC9_VBUS_CLK                                                                   | CLK_STATE_READY     | 125000000       | 0    | DEV_DDR0_DDRSS_CFG_CLK                                                              | CLK_STATE_READY     | 125000000       | 1    | DEV_DDR0_DDRSS_DDR_PLL_CLK                                                          | CLK_STATE_READY     | 1066500000      | 4    | DEV_DDR0_DDRSS_VBUS_CLK                                                             | CLK_STATE_READY     | 250000000       | 5    | DEV_DDR0_PLL_CTRL_CLK                                                               | CLK_STATE_READY     | 500000000       | 0    | DEV_DDR1_DDRSS_CFG_CLK                                                              | CLK_STATE_READY     | 125000000       | 1    | DEV_DDR1_DDRSS_DDR_PLL_CLK                                                          | CLK_STATE_READY     | 1066500000      | 4    | DEV_DDR1_DDRSS_VBUS_CLK                                                             | CLK_STATE_READY     | 250000000       | 5    | DEV_DDR1_PLL_CTRL_CLK                                                               | CLK_STATE_READY     | 500000000       | 0    | DEV_DDR2_DDRSS_CFG_CLK                                                              | CLK_STATE_READY     | 125000000       | 1    | DEV_DDR2_DDRSS_DDR_PLL_CLK                                                          | CLK_STATE_READY     | 1066500000      | 4    | DEV_DDR2_DDRSS_VBUS_CLK                                                             | CLK_STATE_READY     | 250000000       | 5    | DEV_DDR2_PLL_CTRL_CLK                                                               | CLK_STATE_READY     | 500000000       | 0    | DEV_DDR3_DDRSS_CFG_CLK                                                              | CLK_STATE_READY     | 125000000       | 1    | DEV_DDR3_DDRSS_DDR_PLL_CLK                                                          | CLK_STATE_READY     | 1066500000      | 4    | DEV_DDR3_DDRSS_VBUS_CLK                                                             | CLK_STATE_READY     | 250000000       | 5    | DEV_DDR3_PLL_CTRL_CLK                                                               | CLK_STATE_READY     | 500000000       | 0    | DEV_DEBUGSS_WRAP0_ATB_CLK                                                           | CLK_STATE_READY     | 250000000       | 1    | DEV_DEBUGSS_WRAP0_CORE_CLK                                                          | CLK_STATE_READY     | 125000000       | 2    | DEV_DEBUGSS_WRAP0_CSTPIU_TRACECLK                                                   | CLK_STATE_READY     | 0               | 20    | DEV_DEBUGSS_WRAP0_JTAG_TCK                                                          | CLK_STATE_READY     | 0               | 22    | DEV_DEBUGSS_WRAP0_TREXPT_CLK                                                        | CLK_STATE_READY     | 300000000       | 0    | DEV_DEBUGSUSPENDRTR0_INTR_CLK                                                       | CLK_STATE_READY     | 125000000       | 0    | DEV_DMPAC0_CLK                                                                      | CLK_STATE_READY     | 480000000       | 0    | DEV_DMPAC0_SDE_0_CLK                                                                | CLK_STATE_READY     | 480000000       | 0    | DEV_DMPAC0_UTC_0_PSIL_LEAF_CLK                                                      | CLK_STATE_READY     | 480000000       | 0    | DEV_DMPAC_VPAC_PSILSS0_MAIN_CLK                                                     | CLK_STATE_READY     | 250000000       | 2    | DEV_DPHY_RX0_IO_RX_CL_L_M                                                           | CLK_STATE_READY     | 0               | 3    | DEV_DPHY_RX0_IO_RX_CL_L_P                                                           | CLK_STATE_READY     | 0               | 4    | DEV_DPHY_RX0_JTAG_TCK                                                               | CLK_STATE_READY     | 0               | 5    | DEV_DPHY_RX0_MAIN_CLK_CLK                                                           | CLK_STATE_READY     | 125000000       | 6    | DEV_DPHY_RX0_PPI_D_RX_ULPS_ESC                                                      | CLK_STATE_READY     | 0               | 7    | DEV_DPHY_RX0_PPI_RX_BYTE_CLK                                                        | CLK_STATE_READY     | 0               | 2    | DEV_DPHY_RX1_IO_RX_CL_L_M                                                           | CLK_STATE_READY     | 0               | 3    | DEV_DPHY_RX1_IO_RX_CL_L_P                                                           | CLK_STATE_READY     | 0               | 4    | DEV_DPHY_RX1_JTAG_TCK                                                               | CLK_STATE_READY     | 0               | 5    | DEV_DPHY_RX1_MAIN_CLK_CLK                                                           | CLK_STATE_READY     | 125000000       | 6    | DEV_DPHY_RX1_PPI_D_RX_ULPS_ESC                                                      | CLK_STATE_READY     | 0               | 7    | DEV_DPHY_RX1_PPI_RX_BYTE_CLK                                                        | CLK_STATE_READY     | 0               | 2    | DEV_DPHY_RX2_IO_RX_CL_L_M                                                           | CLK_STATE_READY     | 0               | 3    | DEV_DPHY_RX2_IO_RX_CL_L_P                                                           | CLK_STATE_READY     | 0               | 4    | DEV_DPHY_RX2_JTAG_TCK                                                               | CLK_STATE_READY     | 0               | 5    | DEV_DPHY_RX2_MAIN_CLK_CLK                                                           | CLK_STATE_READY     | 125000000       | 6    | DEV_DPHY_RX2_PPI_D_RX_ULPS_ESC                                                      | CLK_STATE_READY     | 0               | 7    | DEV_DPHY_RX2_PPI_RX_BYTE_CLK                                                        | CLK_STATE_READY     | 0               | 0    | DEV_DPHY_TX0_CK_M                                                                   | CLK_STATE_READY     | 0               | 1    | DEV_DPHY_TX0_CK_P                                                                   | CLK_STATE_READY     | 0               | 2    | DEV_DPHY_TX0_CLK                                                                    | CLK_STATE_READY     | 125000000       | 3    | DEV_DPHY_TX0_DPHY_REF_CLK                                                           | CLK_STATE_READY     | 24000000        | 4    | DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                            | CLK_STATE_READY     | 24000000        | 5    | DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                             | CLK_STATE_READY     | 0               | 6    | DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK                  | CLK_STATE_READY     | 156250000       | 7    | DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK                  | CLK_STATE_READY     | 100000000       | 8    | DEV_DPHY_TX0_IP1_PPI_M_RXCLKESC_CLK                                                 | CLK_STATE_READY     | 0               | 9    | DEV_DPHY_TX0_IP1_PPI_M_TXCLKESC_CLK                                                 | CLK_STATE_READY     | 20000000        | 10    | DEV_DPHY_TX0_IP1_PPI_TXBYTECLKHS_CL_CLK                                             | CLK_STATE_READY     | 0               | 12    | DEV_DPHY_TX0_IP2_PPI_M_TXCLKESC_CLK                                                 | CLK_STATE_READY     | 20000000        | 13    | DEV_DPHY_TX0_IP2_PPI_TXBYTECLKHS_CL_CLK                                             | CLK_STATE_READY     | 0               | 20    | DEV_DPHY_TX0_PSM_CLK                                                                | CLK_STATE_READY     | 20000000        | 24    | DEV_DPHY_TX0_TAP_TCK                                                                | CLK_STATE_READY     | 0               | 0    | DEV_DPHY_TX1_CK_M                                                                   | CLK_STATE_READY     | 0               | 1    | DEV_DPHY_TX1_CK_P                                                                   | CLK_STATE_READY     | 0               | 2    | DEV_DPHY_TX1_CLK                                                                    | CLK_STATE_READY     | 125000000       | 3    | DEV_DPHY_TX1_DPHY_REF_CLK                                                           | CLK_STATE_READY     | 24000000        | 4    | DEV_DPHY_TX1_DPHY_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                            | CLK_STATE_READY     | 24000000        | 5    | DEV_DPHY_TX1_DPHY_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                             | CLK_STATE_READY     | 0               | 6    | DEV_DPHY_TX1_DPHY_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK                  | CLK_STATE_READY     | 156250000       | 7    | DEV_DPHY_TX1_DPHY_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK                  | CLK_STATE_READY     | 100000000       | 8    | DEV_DPHY_TX1_IP1_PPI_M_RXCLKESC_CLK                                                 | CLK_STATE_READY     | 0               | 9    | DEV_DPHY_TX1_IP1_PPI_M_TXCLKESC_CLK                                                 | CLK_STATE_READY     | 20000000        | 10    | DEV_DPHY_TX1_IP1_PPI_TXBYTECLKHS_CL_CLK                                             | CLK_STATE_READY     | 0               | 13    | DEV_DPHY_TX1_IP2_PPI_TXBYTECLKHS_CL_CLK                                             | CLK_STATE_READY     | 0               | 20    | DEV_DPHY_TX1_PSM_CLK                                                                | CLK_STATE_READY     | 20000000        | 24    | DEV_DPHY_TX1_TAP_TCK                                                                | CLK_STATE_READY     | 0               | 0    | DEV_DSS0_DSS_FUNC_CLK                                                               | CLK_STATE_READY     | 600000000       | 1    | DEV_DSS0_DSS_INST0_DPI_0_IN_CLK                                                     | CLK_STATE_READY     | 297000000       | 2    | DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK                                                  | CLK_STATE_READY     | 594000000       | 3    | DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK        | CLK_STATE_READY     | 594000000       | 4    | DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK_PARENT_DPI_1_PCLK_SEL_OUT0                       | CLK_STATE_READY     | 600000000       | 5    | DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK                                                  | CLK_STATE_READY     | 600000000       | 6    | DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT0_CLK        | CLK_STATE_READY     | 594000000       | 7    | DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0                      | CLK_STATE_READY     | 600000000       | 8    | DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0_DUP0                 | CLK_STATE_READY     | 600000000       | 9    | DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK        | CLK_STATE_READY     | 594000000       | 10    | DEV_DSS0_DSS_INST0_DPI_2_IN_CLK                                                     | CLK_STATE_READY     | 297000000       | 11    | DEV_DSS0_DSS_INST0_DPI_2_IN_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK           | CLK_STATE_READY     | 297000000       | 12    | DEV_DSS0_DSS_INST0_DPI_2_IN_CLK_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT0_CLK           | CLK_STATE_READY     | 297000000       | 13    | DEV_DSS0_DSS_INST0_DPI_2_IN_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0                         | CLK_STATE_READY     | 300000000       | 14    | DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK                                                  | CLK_STATE_READY     | 594000000       | 15    | DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK        | CLK_STATE_READY     | 594000000       | 16    | DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT0_CLK        | CLK_STATE_READY     | 594000000       | 17    | DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0                      | CLK_STATE_READY     | 600000000       | 18    | DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK                                                  | CLK_STATE_READY     | 600000000       | 19    | DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT1_CLK        | CLK_STATE_READY     | 594000000       | 20    | DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT1_CLK        | CLK_STATE_READY     | 594000000       | 21    | DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT1_CLK_DUP0   | CLK_STATE_READY     | 594000000       | 22    | DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0                      | CLK_STATE_READY     | 600000000       | 23    | DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0_DUP0                 | CLK_STATE_READY     | 600000000       | 24    | DEV_DSS0_DSS_INST0_PARA_1_OUT_CLK                                                   | CLK_STATE_READY     | 0               | 25    | DEV_DSS0_DSS_INST0_PARA_3_OUT_CLK                                                   | CLK_STATE_READY     | 0               | 26    | DEV_DSS0_DSS_INST0_DPI_0_OUT_CLK                                                    | CLK_STATE_READY     | 0               | 27    | DEV_DSS0_DSS_INST0_DPI_1_OUT_CLK                                                    | CLK_STATE_READY     | 0               | 28    | DEV_DSS0_DSS_INST0_DPI_2_OUT_CLK                                                    | CLK_STATE_READY     | 0               | 29    | DEV_DSS0_DSS_INST0_DPI_3_OUT_CLK                                                    | CLK_STATE_READY     | 0               | 30    | DEV_DSS0_DSS_INST0_DPI_0_OUT_2X_CLK                                                 | CLK_STATE_READY     | 0               | 0    | DEV_DSS_DSI0_DPHY_0_RX_ESC_CLK                                                      | CLK_STATE_READY     | 0               | 1    | DEV_DSS_DSI0_DPHY_0_TX_ESC_CLK                                                      | CLK_STATE_READY     | 20000000        | 2    | DEV_DSS_DSI0_DPI_0_CLK                                                              | CLK_STATE_READY     | 0               | 3    | DEV_DSS_DSI0_PLL_CTRL_CLK                                                           | CLK_STATE_READY     | 500000000       | 4    | DEV_DSS_DSI0_PPI_0_TXBYTECLKHS_CL_CLK                                               | CLK_STATE_READY     | 0               | 5    | DEV_DSS_DSI0_SYS_CLK                                                                | CLK_STATE_READY     | 250000000       | 0    | DEV_DSS_DSI1_DPHY_0_RX_ESC_CLK                                                      | CLK_STATE_READY     | 0               | 1    | DEV_DSS_DSI1_DPHY_0_TX_ESC_CLK                                                      | CLK_STATE_READY     | 20000000        | 2    | DEV_DSS_DSI1_DPI_0_CLK                                                              | CLK_STATE_READY     | 0               | 3    | DEV_DSS_DSI1_PLL_CTRL_CLK                                                           | CLK_STATE_READY     | 500000000       | 4    | DEV_DSS_DSI1_PPI_0_TXBYTECLKHS_CL_CLK                                               | CLK_STATE_READY     | 0               | 5    | DEV_DSS_DSI1_SYS_CLK                                                                | CLK_STATE_READY     | 250000000       | 0    | DEV_DSS_EDP0_AIF_I2S_CLK                                                            | CLK_STATE_READY     | 0               | 6    | DEV_DSS_EDP0_DPI_2_2X_CLK                                                           | CLK_STATE_READY     | 0               | 7    | DEV_DSS_EDP0_DPI_2_CLK                                                              | CLK_STATE_READY     | 0               | 8    | DEV_DSS_EDP0_DPI_3_CLK                                                              | CLK_STATE_READY     | 0               | 9    | DEV_DSS_EDP0_DPI_4_CLK                                                              | CLK_STATE_READY     | 0               | 10    | DEV_DSS_EDP0_DPI_5_CLK                                                              | CLK_STATE_READY     | 0               | 11    | DEV_DSS_EDP0_DPTX_MOD_CLK                                                           | CLK_STATE_READY     | 125000000       | 12    | DEV_DSS_EDP0_PHY_LN0_REFCLK                                                         | CLK_STATE_READY     | 0               | 13    | DEV_DSS_EDP0_PHY_LN0_RXCLK                                                          | CLK_STATE_READY     | 0               | 14    | DEV_DSS_EDP0_PHY_LN0_RXFCLK                                                         | CLK_STATE_READY     | 0               | 15    | DEV_DSS_EDP0_PHY_LN0_TXCLK                                                          | CLK_STATE_READY     | 0               | 16    | DEV_DSS_EDP0_PHY_LN0_TXFCLK                                                         | CLK_STATE_READY     | 0               | 17    | DEV_DSS_EDP0_PHY_LN0_TXMCLK                                                         | CLK_STATE_READY     | 0               | 18    | DEV_DSS_EDP0_PHY_LN1_REFCLK                                                         | CLK_STATE_READY     | 0               | 19    | DEV_DSS_EDP0_PHY_LN1_RXCLK                                                          | CLK_STATE_READY     | 0               | 20    | DEV_DSS_EDP0_PHY_LN1_RXFCLK                                                         | CLK_STATE_READY     | 0               | 21    | DEV_DSS_EDP0_PHY_LN1_TXCLK                                                          | CLK_STATE_READY     | 0               | 22    | DEV_DSS_EDP0_PHY_LN1_TXFCLK                                                         | CLK_STATE_READY     | 0               | 23    | DEV_DSS_EDP0_PHY_LN1_TXMCLK                                                         | CLK_STATE_READY     | 0               | 24    | DEV_DSS_EDP0_PHY_LN2_REFCLK                                                         | CLK_STATE_READY     | 0               | 25    | DEV_DSS_EDP0_PHY_LN2_RXCLK                                                          | CLK_STATE_READY     | 0               | 26    | DEV_DSS_EDP0_PHY_LN2_RXFCLK                                                         | CLK_STATE_READY     | 0               | 27    | DEV_DSS_EDP0_PHY_LN2_TXCLK                                                          | CLK_STATE_READY     | 0               | 28    | DEV_DSS_EDP0_PHY_LN2_TXFCLK                                                         | CLK_STATE_READY     | 0               | 29    | DEV_DSS_EDP0_PHY_LN2_TXMCLK                                                         | CLK_STATE_READY     | 0               | 30    | DEV_DSS_EDP0_PHY_LN3_REFCLK                                                         | CLK_STATE_READY     | 0               | 31    | DEV_DSS_EDP0_PHY_LN3_RXCLK                                                          | CLK_STATE_READY     | 0               | 32    | DEV_DSS_EDP0_PHY_LN3_RXFCLK                                                         | CLK_STATE_READY     | 0               | 33    | DEV_DSS_EDP0_PHY_LN3_TXCLK                                                          | CLK_STATE_READY     | 0               | 34    | DEV_DSS_EDP0_PHY_LN3_TXFCLK                                                         | CLK_STATE_READY     | 0               | 35    | DEV_DSS_EDP0_PHY_LN3_TXMCLK                                                         | CLK_STATE_READY     | 0               | 36    | DEV_DSS_EDP0_PLL_CTRL_CLK                                                           | CLK_STATE_READY     | 500000000       | 0    | DEV_ECAP0_VBUS_CLK                                                                  | CLK_STATE_READY     | 125000000       | 0    | DEV_ECAP1_VBUS_CLK                                                                  | CLK_STATE_READY     | 125000000       | 0    | DEV_ECAP2_VBUS_CLK                                                                  | CLK_STATE_READY     | 125000000       | 0    | DEV_ELM0_VBUSP_CLK                                                                  | CLK_STATE_READY     | 125000000       | 0    | DEV_EPWM0_VBUSP_CLK                                                                 | CLK_STATE_READY     | 125000000       | 0    | DEV_EPWM1_VBUSP_CLK                                                                 | CLK_STATE_READY     | 125000000       | 0    | DEV_EPWM2_VBUSP_CLK                                                                 | CLK_STATE_READY     | 125000000       | 0    | DEV_EPWM3_VBUSP_CLK                                                                 | CLK_STATE_READY     | 125000000       | 0    | DEV_EPWM4_VBUSP_CLK                                                                 | CLK_STATE_READY     | 125000000       | 0    | DEV_EPWM5_VBUSP_CLK                                                                 | CLK_STATE_READY     | 125000000       | 0    | DEV_EQEP0_VBUS_CLK                                                                  | CLK_STATE_READY     | 125000000       | 0    | DEV_EQEP1_VBUS_CLK                                                                  | CLK_STATE_READY     | 125000000       | 0    | DEV_EQEP2_VBUS_CLK                                                                  | CLK_STATE_READY     | 125000000       | 0    | DEV_ESM0_CLK                                                                        | CLK_STATE_READY     | 125000000       | 0    | DEV_GLUELOGIC_ACSPCIE0_BUFFER_CLKIN0                                                | CLK_STATE_READY     | 24000000        | 1    | DEV_GLUELOGIC_ACSPCIE0_BUFFER_CLKIN1                                                | CLK_STATE_READY     | 24000000        | 2    | DEV_GLUELOGIC_ACSPCIE0_BUFFER_PAD0_M                                                | CLK_STATE_READY     | 62500000        | 3    | DEV_GLUELOGIC_ACSPCIE0_BUFFER_PAD0_P                                                | CLK_STATE_READY     | 12500000        | 4    | DEV_GLUELOGIC_ACSPCIE0_BUFFER_PAD1_M                                                | CLK_STATE_READY     | 200000000       | 5    | DEV_GLUELOGIC_ACSPCIE0_BUFFER_PAD1_P                                                | CLK_STATE_READY     | 0               | 0    | DEV_GLUELOGIC_ACSPCIE1_BUFFER_CLKIN0                                                | CLK_STATE_READY     | 24000000        | 1    | DEV_GLUELOGIC_ACSPCIE1_BUFFER_CLKIN1                                                | CLK_STATE_READY     | 24000000        | 2    | DEV_GLUELOGIC_ACSPCIE1_BUFFER_PAD0_M                                                | CLK_STATE_READY     | 62500000        | 3    | DEV_GLUELOGIC_ACSPCIE1_BUFFER_PAD0_P                                                | CLK_STATE_READY     | 12500000        | 4    | DEV_GLUELOGIC_ACSPCIE1_BUFFER_PAD1_M                                                | CLK_STATE_READY     | 200000000       | 5    | DEV_GLUELOGIC_ACSPCIE1_BUFFER_PAD1_P                                                | CLK_STATE_READY     | 0               | 0    | DEV_GPIO0_MMR_CLK                                                                   | CLK_STATE_READY     | 125000000       | 0    | DEV_GPIO2_MMR_CLK                                                                   | CLK_STATE_READY     | 125000000       | 0    | DEV_GPIO4_MMR_CLK                                                                   | CLK_STATE_READY     | 125000000       | 0    | DEV_GPIO6_MMR_CLK                                                                   | CLK_STATE_READY     | 125000000       | 0    | DEV_GPIOMUX_INTRTR0_INTR_CLK                                                        | CLK_STATE_READY     | 125000000       | 0    | DEV_GPMC0_FUNC_CLK                                                                  | CLK_STATE_READY     | 133333333       | 1    | DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT3_CLK                         | CLK_STATE_READY     | 133333333       | 2    | DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK6                        | CLK_STATE_READY     | 100000000       | 3    | DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK4                        | CLK_STATE_READY     | 150000000       | 4    | DEV_GPMC0_FUNC_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK4                | CLK_STATE_READY     | 125000000       | 5    | DEV_GPMC0_PI_GPMC_RET_CLK                                                           | CLK_STATE_READY     | 0               | 6    | DEV_GPMC0_PO_GPMC_DEV_CLK                                                           | CLK_STATE_READY     | 0               | 7    | DEV_GPMC0_VBUSM_CLK                                                                 | CLK_STATE_READY     | 250000000       | 0    | DEV_GTC0_GTC_CLK                                                                    | CLK_STATE_READY     | 200000000       | 1    | DEV_GTC0_GTC_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK                           | CLK_STATE_READY     | 250000000       | 2    | DEV_GTC0_GTC_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK                         | CLK_STATE_READY     | 200000000       | 3    | DEV_GTC0_GTC_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT                               | CLK_STATE_READY     | 0               | 4    | DEV_GTC0_GTC_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT                                   | CLK_STATE_READY     | 0               | 5    | DEV_GTC0_GTC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                                 | CLK_STATE_READY     | 0               | 6    | DEV_GTC0_GTC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT                                     | CLK_STATE_READY     | 0               | 7    | DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN0_TXMCLK                          | CLK_STATE_READY     | 0               | 8    | DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN1_TXMCLK                          | CLK_STATE_READY     | 0               | 9    | DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN2_TXMCLK                          | CLK_STATE_READY     | 0               | 10    | DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN3_TXMCLK                          | CLK_STATE_READY     | 0               | 11    | DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN0_TXMCLK                          | CLK_STATE_READY     | 0               | 12    | DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN1_TXMCLK                          | CLK_STATE_READY     | 0               | 13    | DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP1_LN2_TXMCLK                          | CLK_STATE_READY     | 0               | 14    | DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP3_LN2_TXMCLK                          | CLK_STATE_READY     | 0               | 15    | DEV_GTC0_GTC_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK                            | CLK_STATE_READY     | 500000000       | 16    | DEV_GTC0_GTC_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK                   | CLK_STATE_READY     | 500000000       | 17    | DEV_GTC0_VBUSP_CLK                                                                  | CLK_STATE_READY     | 125000000       | 0    | DEV_I2C0_CLK                                                                        | CLK_STATE_READY     | 125000000       | 1    | DEV_I2C0_PISCL                                                                      | CLK_STATE_READY     | 0               | 2    | DEV_I2C0_PISYS_CLK                                                                  | CLK_STATE_READY     | 96000000        | 3    | DEV_I2C0_PORSCL                                                                     | CLK_STATE_READY     | 0               | 0    | DEV_I2C1_CLK                                                                        | CLK_STATE_READY     | 125000000       | 1    | DEV_I2C1_PISCL                                                                      | CLK_STATE_READY     | 0               | 2    | DEV_I2C1_PISYS_CLK                                                                  | CLK_STATE_READY     | 96000000        | 3    | DEV_I2C1_PORSCL                                                                     | CLK_STATE_READY     | 0               | 0    | DEV_I2C2_CLK                                                                        | CLK_STATE_READY     | 125000000       | 1    | DEV_I2C2_PISCL                                                                      | CLK_STATE_READY     | 0               | 2    | DEV_I2C2_PISYS_CLK                                                                  | CLK_STATE_READY     | 96000000        | 3    | DEV_I2C2_PORSCL                                                                     | CLK_STATE_READY     | 0               | 0    | DEV_I2C3_CLK                                                                        | CLK_STATE_READY     | 125000000       | 1    | DEV_I2C3_PISCL                                                                      | CLK_STATE_READY     | 0               | 2    | DEV_I2C3_PISYS_CLK                                                                  | CLK_STATE_READY     | 96000000        | 3    | DEV_I2C3_PORSCL                                                                     | CLK_STATE_READY     | 0               | 0    | DEV_I2C4_CLK                                                                        | CLK_STATE_READY     | 125000000       | 1    | DEV_I2C4_PISCL                                                                      | CLK_STATE_READY     | 0               | 2    | DEV_I2C4_PISYS_CLK                                                                  | CLK_STATE_READY     | 96000000        | 3    | DEV_I2C4_PORSCL                                                                     | CLK_STATE_READY     | 0               | 0    | DEV_I2C5_CLK                                                                        | CLK_STATE_READY     | 125000000       | 1    | DEV_I2C5_PISCL                                                                      | CLK_STATE_READY     | 0               | 2    | DEV_I2C5_PISYS_CLK                                                                  | CLK_STATE_READY     | 96000000        | 3    | DEV_I2C5_PORSCL                                                                     | CLK_STATE_READY     | 0               | 0    | DEV_I2C6_CLK                                                                        | CLK_STATE_READY     | 125000000       | 1    | DEV_I2C6_PISCL                                                                      | CLK_STATE_READY     | 0               | 2    | DEV_I2C6_PISYS_CLK                                                                  | CLK_STATE_READY     | 96000000        | 3    | DEV_I2C6_PORSCL                                                                     | CLK_STATE_READY     | 0               | 1    | DEV_J7AEP_GPU_BXS464_WRAP0_GPU_SS_0_GPU_PLL_CLK                                     | CLK_STATE_READY     | 800000000       | 4    | DEV_J7AEP_GPU_BXS464_WRAP0_GPU_SS_0_PLL_CTRL_CLK                                    | CLK_STATE_READY     | 500000000       | 0    | DEV_J7AM_32_64_ATB_FUNNEL0_DBG_CLK                                                  | CLK_STATE_READY     | 250000000       | 0    | DEV_J7AM_32_64_ATB_FUNNEL1_DBG_CLK                                                  | CLK_STATE_READY     | 250000000       | 0    | DEV_J7AM_32_64_ATB_FUNNEL2_DBG_CLK                                                  | CLK_STATE_READY     | 250000000       | 0    | DEV_J7AM_BOLT_PGD0_WKUP_OSC0_CLK                                                    | CLK_STATE_READY     | 24000000        | 0    | DEV_J7AM_BOLT_PSC_WRAP0_CLK                                                         | CLK_STATE_READY     | 125000000       | 1    | DEV_J7AM_BOLT_PSC_WRAP0_SLOW_CLK                                                    | CLK_STATE_READY     | 20833333        | 0    | DEV_J7AM_HWA_ATB_FUNNEL0_DBG_CLK                                                    | CLK_STATE_READY     | 250000000       | 0    | DEV_J7AM_MAIN_16FF0_WKUP_OSC0_CLK                                                   | CLK_STATE_READY     | 24000000        | 0    | DEV_J7AM_PULSAR_ATB_FUNNEL0_DBG_CLK                                                 | CLK_STATE_READY     | 250000000       | 0    | DEV_LED0_LED_CLK                                                                    | CLK_STATE_READY     | 0               | 1    | DEV_LED0_VBUS_CLK                                                                   | CLK_STATE_READY     | 250000000       | 0    | DEV_MAIN2MCU_LVL_INTRTR0_INTR_CLK                                                   | CLK_STATE_READY     | 125000000       | 0    | DEV_MAIN2MCU_PLS_INTRTR0_INTR_CLK                                                   | CLK_STATE_READY     | 125000000       | 0    | DEV_MCAN0_MCANSS_CAN_RXD                                                            | CLK_STATE_READY     | 0               | 1    | DEV_MCAN0_MCANSS_CCLK_CLK                                                           | CLK_STATE_READY     | 80000000        | 2    | DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK                  | CLK_STATE_READY     | 80000000        | 3    | DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                        | CLK_STATE_READY     | 0               | 4    | DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                             | CLK_STATE_READY     | 0               | 5    | DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                            | CLK_STATE_READY     | 24000000        | 6    | DEV_MCAN0_MCANSS_HCLK_CLK                                                           | CLK_STATE_READY     | 125000000       | 0    | DEV_MCAN1_MCANSS_CAN_RXD                                                            | CLK_STATE_READY     | 0               | 1    | DEV_MCAN1_MCANSS_CCLK_CLK                                                           | CLK_STATE_READY     | 80000000        | 2    | DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK                  | CLK_STATE_READY     | 80000000        | 3    | DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                        | CLK_STATE_READY     | 0               | 4    | DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                             | CLK_STATE_READY     | 0               | 5    | DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                            | CLK_STATE_READY     | 24000000        | 6    | DEV_MCAN1_MCANSS_HCLK_CLK                                                           | CLK_STATE_READY     | 125000000       | 0    | DEV_MCAN10_MCANSS_CAN_RXD                                                           | CLK_STATE_READY     | 0               | 1    | DEV_MCAN10_MCANSS_CCLK_CLK                                                          | CLK_STATE_READY     | 80000000        | 2    | DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK                 | CLK_STATE_READY     | 80000000        | 3    | DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                       | CLK_STATE_READY     | 0               | 4    | DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                            | CLK_STATE_READY     | 0               | 5    | DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                           | CLK_STATE_READY     | 24000000        | 6    | DEV_MCAN10_MCANSS_HCLK_CLK                                                          | CLK_STATE_READY     | 125000000       | 0    | DEV_MCAN11_MCANSS_CAN_RXD                                                           | CLK_STATE_READY     | 0               | 1    | DEV_MCAN11_MCANSS_CCLK_CLK                                                          | CLK_STATE_READY     | 80000000        | 2    | DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK                 | CLK_STATE_READY     | 80000000        | 3    | DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                       | CLK_STATE_READY     | 0               | 4    | DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                            | CLK_STATE_READY     | 0               | 5    | DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                           | CLK_STATE_READY     | 24000000        | 6    | DEV_MCAN11_MCANSS_HCLK_CLK                                                          | CLK_STATE_READY     | 125000000       | 0    | DEV_MCAN12_MCANSS_CAN_RXD                                                           | CLK_STATE_READY     | 0               | 1    | DEV_MCAN12_MCANSS_CCLK_CLK                                                          | CLK_STATE_READY     | 80000000        | 2    | DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK                 | CLK_STATE_READY     | 80000000        | 3    | DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                       | CLK_STATE_READY     | 0               | 4    | DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                            | CLK_STATE_READY     | 0               | 5    | DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                           | CLK_STATE_READY     | 24000000        | 6    | DEV_MCAN12_MCANSS_HCLK_CLK                                                          | CLK_STATE_READY     | 125000000       | 0    | DEV_MCAN13_MCANSS_CAN_RXD                                                           | CLK_STATE_READY     | 0               | 1    | DEV_MCAN13_MCANSS_CCLK_CLK                                                          | CLK_STATE_READY     | 80000000        | 2    | DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK                 | CLK_STATE_READY     | 80000000        | 3    | DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                       | CLK_STATE_READY     | 0               | 4    | DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                            | CLK_STATE_READY     | 0               | 5    | DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                           | CLK_STATE_READY     | 24000000        | 6    | DEV_MCAN13_MCANSS_HCLK_CLK                                                          | CLK_STATE_READY     | 125000000       | 0    | DEV_MCAN14_MCANSS_CAN_RXD                                                           | CLK_STATE_READY     | 0               | 1    | DEV_MCAN14_MCANSS_CCLK_CLK                                                          | CLK_STATE_READY     | 80000000        | 2    | DEV_MCAN14_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK                 | CLK_STATE_READY     | 80000000        | 3    | DEV_MCAN14_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                       | CLK_STATE_READY     | 0               | 4    | DEV_MCAN14_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                            | CLK_STATE_READY     | 0               | 5    | DEV_MCAN14_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                           | CLK_STATE_READY     | 24000000        | 6    | DEV_MCAN14_MCANSS_HCLK_CLK                                                          | CLK_STATE_READY     | 125000000       | 0    | DEV_MCAN15_MCANSS_CAN_RXD                                                           | CLK_STATE_READY     | 0               | 1    | DEV_MCAN15_MCANSS_CCLK_CLK                                                          | CLK_STATE_READY     | 80000000        | 2    | DEV_MCAN15_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK                 | CLK_STATE_READY     | 80000000        | 3    | DEV_MCAN15_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                       | CLK_STATE_READY     | 0               | 4    | DEV_MCAN15_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                            | CLK_STATE_READY     | 0               | 5    | DEV_MCAN15_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                           | CLK_STATE_READY     | 24000000        | 6    | DEV_MCAN15_MCANSS_HCLK_CLK                                                          | CLK_STATE_READY     | 125000000       | 0    | DEV_MCAN16_MCANSS_CAN_RXD                                                           | CLK_STATE_READY     | 0               | 1    | DEV_MCAN16_MCANSS_CCLK_CLK                                                          | CLK_STATE_READY     | 80000000        | 2    | DEV_MCAN16_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK                 | CLK_STATE_READY     | 80000000        | 3    | DEV_MCAN16_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                       | CLK_STATE_READY     | 0               | 4    | DEV_MCAN16_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                            | CLK_STATE_READY     | 0               | 5    | DEV_MCAN16_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                           | CLK_STATE_READY     | 24000000        | 6    | DEV_MCAN16_MCANSS_HCLK_CLK                                                          | CLK_STATE_READY     | 125000000       | 0    | DEV_MCAN17_MCANSS_CAN_RXD                                                           | CLK_STATE_READY     | 0               | 1    | DEV_MCAN17_MCANSS_CCLK_CLK                                                          | CLK_STATE_READY     | 80000000        | 2    | DEV_MCAN17_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK                 | CLK_STATE_READY     | 80000000        | 3    | DEV_MCAN17_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                       | CLK_STATE_READY     | 0               | 4    | DEV_MCAN17_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                            | CLK_STATE_READY     | 0               | 5    | DEV_MCAN17_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                           | CLK_STATE_READY     | 24000000        | 6    | DEV_MCAN17_MCANSS_HCLK_CLK                                                          | CLK_STATE_READY     | 125000000       | 0    | DEV_MCAN2_MCANSS_CAN_RXD                                                            | CLK_STATE_READY     | 0               | 1    | DEV_MCAN2_MCANSS_CCLK_CLK                                                           | CLK_STATE_READY     | 80000000        | 2    | DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK                  | CLK_STATE_READY     | 80000000        | 3    | DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                        | CLK_STATE_READY     | 0               | 4    | DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                             | CLK_STATE_READY     | 0               | 5    | DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                            | CLK_STATE_READY     | 24000000        | 6    | DEV_MCAN2_MCANSS_HCLK_CLK                                                           | CLK_STATE_READY     | 125000000       | 0    | DEV_MCAN3_MCANSS_CAN_RXD                                                            | CLK_STATE_READY     | 0               | 1    | DEV_MCAN3_MCANSS_CCLK_CLK                                                           | CLK_STATE_READY     | 80000000        | 2    | DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK                  | CLK_STATE_READY     | 80000000        | 3    | DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                        | CLK_STATE_READY     | 0               | 4    | DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                             | CLK_STATE_READY     | 0               | 5    | DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                            | CLK_STATE_READY     | 24000000        | 6    | DEV_MCAN3_MCANSS_HCLK_CLK                                                           | CLK_STATE_READY     | 125000000       | 0    | DEV_MCAN4_MCANSS_CAN_RXD                                                            | CLK_STATE_READY     | 0               | 1    | DEV_MCAN4_MCANSS_CCLK_CLK                                                           | CLK_STATE_READY     | 80000000        | 2    | DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK                  | CLK_STATE_READY     | 80000000        | 3    | DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                        | CLK_STATE_READY     | 0               | 4    | DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                             | CLK_STATE_READY     | 0               | 5    | DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                            | CLK_STATE_READY     | 24000000        | 6    | DEV_MCAN4_MCANSS_HCLK_CLK                                                           | CLK_STATE_READY     | 125000000       | 0    | DEV_MCAN5_MCANSS_CAN_RXD                                                            | CLK_STATE_READY     | 0               | 1    | DEV_MCAN5_MCANSS_CCLK_CLK                                                           | CLK_STATE_READY     | 80000000        | 2    | DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK                  | CLK_STATE_READY     | 80000000        | 3    | DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                        | CLK_STATE_READY     | 0               | 4    | DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                             | CLK_STATE_READY     | 0               | 5    | DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                            | CLK_STATE_READY     | 24000000        | 6    | DEV_MCAN5_MCANSS_HCLK_CLK                                                           | CLK_STATE_READY     | 125000000       | 0    | DEV_MCAN6_MCANSS_CAN_RXD                                                            | CLK_STATE_READY     | 0               | 1    | DEV_MCAN6_MCANSS_CCLK_CLK                                                           | CLK_STATE_READY     | 80000000        | 2    | DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK                  | CLK_STATE_READY     | 80000000        | 3    | DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                        | CLK_STATE_READY     | 0               | 4    | DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                             | CLK_STATE_READY     | 0               | 5    | DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                            | CLK_STATE_READY     | 24000000        | 6    | DEV_MCAN6_MCANSS_HCLK_CLK                                                           | CLK_STATE_READY     | 125000000       | 0    | DEV_MCAN7_MCANSS_CAN_RXD                                                            | CLK_STATE_READY     | 0               | 1    | DEV_MCAN7_MCANSS_CCLK_CLK                                                           | CLK_STATE_READY     | 80000000        | 2    | DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK                  | CLK_STATE_READY     | 80000000        | 3    | DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                        | CLK_STATE_READY     | 0               | 4    | DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                             | CLK_STATE_READY     | 0               | 5    | DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                            | CLK_STATE_READY     | 24000000        | 6    | DEV_MCAN7_MCANSS_HCLK_CLK                                                           | CLK_STATE_READY     | 125000000       | 0    | DEV_MCAN8_MCANSS_CAN_RXD                                                            | CLK_STATE_READY     | 0               | 1    | DEV_MCAN8_MCANSS_CCLK_CLK                                                           | CLK_STATE_READY     | 80000000        | 2    | DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK                  | CLK_STATE_READY     | 80000000        | 3    | DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                        | CLK_STATE_READY     | 0               | 4    | DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                             | CLK_STATE_READY     | 0               | 5    | DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                            | CLK_STATE_READY     | 24000000        | 6    | DEV_MCAN8_MCANSS_HCLK_CLK                                                           | CLK_STATE_READY     | 125000000       | 0    | DEV_MCAN9_MCANSS_CAN_RXD                                                            | CLK_STATE_READY     | 0               | 1    | DEV_MCAN9_MCANSS_CCLK_CLK                                                           | CLK_STATE_READY     | 80000000        | 2    | DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK                  | CLK_STATE_READY     | 80000000        | 3    | DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                        | CLK_STATE_READY     | 0               | 4    | DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                             | CLK_STATE_READY     | 0               | 5    | DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                            | CLK_STATE_READY     | 24000000        | 6    | DEV_MCAN9_MCANSS_HCLK_CLK                                                           | CLK_STATE_READY     | 125000000       | 0    | DEV_MCASP0_AUX_CLK                                                                  | CLK_STATE_READY     | 196608000       | 1    | DEV_MCASP0_AUX_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK                         | CLK_STATE_READY     | 196608000       | 2    | DEV_MCASP0_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK                         | CLK_STATE_READY     | 200000000       | 5    | DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT                          | CLK_STATE_NOT_READY | 0               | 6    | DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1                        | CLK_STATE_NOT_READY | 0               | 7    | DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2                        | CLK_STATE_NOT_READY | 0               | 8    | DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3                        | CLK_STATE_NOT_READY | 0               | 9    | DEV_MCASP0_MCASP_ACLKR_PIN                                                          | CLK_STATE_READY     | 0               | 10    | DEV_MCASP0_MCASP_ACLKR_POUT                                                         | CLK_STATE_READY     | 0               | 11    | DEV_MCASP0_MCASP_ACLKX_PIN                                                          | CLK_STATE_READY     | 0               | 12    | DEV_MCASP0_MCASP_ACLKX_POUT                                                         | CLK_STATE_READY     | 0               | 13    | DEV_MCASP0_MCASP_AFSR_POUT                                                          | CLK_STATE_READY     | 0               | 14    | DEV_MCASP0_MCASP_AFSX_POUT                                                          | CLK_STATE_READY     | 0               | 15    | DEV_MCASP0_MCASP_AHCLKR_PIN                                                         | CLK_STATE_READY     | 0               | 16    | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT                           | CLK_STATE_READY     | 0               | 17    | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT                          | CLK_STATE_READY     | 24000000        | 18    | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT                    | CLK_STATE_READY     | 0               | 19    | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT                    | CLK_STATE_READY     | 0               | 24    | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT                 | CLK_STATE_NOT_READY | 0               | 25    | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1               | CLK_STATE_NOT_READY | 0               | 26    | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2               | CLK_STATE_NOT_READY | 0               | 27    | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3               | CLK_STATE_NOT_READY | 0               | 32    | DEV_MCASP0_MCASP_AHCLKR_POUT                                                        | CLK_STATE_READY     | 0               | 33    | DEV_MCASP0_MCASP_AHCLKX_PIN                                                         | CLK_STATE_READY     | 0               | 34    | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT                           | CLK_STATE_READY     | 0               | 35    | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT                          | CLK_STATE_READY     | 24000000        | 36    | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT                    | CLK_STATE_READY     | 0               | 37    | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT                    | CLK_STATE_READY     | 0               | 42    | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT                 | CLK_STATE_NOT_READY | 0               | 43    | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1               | CLK_STATE_NOT_READY | 0               | 44    | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2               | CLK_STATE_NOT_READY | 0               | 45    | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3               | CLK_STATE_NOT_READY | 0               | 50    | DEV_MCASP0_MCASP_AHCLKX_POUT                                                        | CLK_STATE_READY     | 0               | 51    | DEV_MCASP0_VBUSP_CLK                                                                | CLK_STATE_READY     | 250000000       | 0    | DEV_MCASP1_AUX_CLK                                                                  | CLK_STATE_READY     | 196608000       | 1    | DEV_MCASP1_AUX_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK                         | CLK_STATE_READY     | 196608000       | 2    | DEV_MCASP1_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK                         | CLK_STATE_READY     | 200000000       | 5    | DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT                          | CLK_STATE_NOT_READY | 0               | 6    | DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1                        | CLK_STATE_NOT_READY | 0               | 7    | DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2                        | CLK_STATE_NOT_READY | 0               | 8    | DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3                        | CLK_STATE_NOT_READY | 0               | 9    | DEV_MCASP1_MCASP_ACLKR_PIN                                                          | CLK_STATE_READY     | 0               | 10    | DEV_MCASP1_MCASP_ACLKR_POUT                                                         | CLK_STATE_READY     | 0               | 11    | DEV_MCASP1_MCASP_ACLKX_PIN                                                          | CLK_STATE_READY     | 0               | 12    | DEV_MCASP1_MCASP_ACLKX_POUT                                                         | CLK_STATE_READY     | 0               | 13    | DEV_MCASP1_MCASP_AFSR_POUT                                                          | CLK_STATE_READY     | 0               | 14    | DEV_MCASP1_MCASP_AFSX_POUT                                                          | CLK_STATE_READY     | 0               | 15    | DEV_MCASP1_MCASP_AHCLKR_PIN                                                         | CLK_STATE_READY     | 0               | 16    | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT                           | CLK_STATE_READY     | 0               | 17    | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT                          | CLK_STATE_READY     | 24000000        | 18    | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT                    | CLK_STATE_READY     | 0               | 19    | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT                    | CLK_STATE_READY     | 0               | 24    | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT                 | CLK_STATE_NOT_READY | 0               | 25    | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1               | CLK_STATE_NOT_READY | 0               | 26    | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2               | CLK_STATE_NOT_READY | 0               | 27    | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3               | CLK_STATE_NOT_READY | 0               | 32    | DEV_MCASP1_MCASP_AHCLKR_POUT                                                        | CLK_STATE_READY     | 0               | 33    | DEV_MCASP1_MCASP_AHCLKX_PIN                                                         | CLK_STATE_READY     | 0               | 34    | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT                           | CLK_STATE_READY     | 0               | 35    | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT                          | CLK_STATE_READY     | 24000000        | 36    | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT                    | CLK_STATE_READY     | 0               | 37    | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT                    | CLK_STATE_READY     | 0               | 42    | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT                 | CLK_STATE_NOT_READY | 0               | 43    | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1               | CLK_STATE_NOT_READY | 0               | 44    | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2               | CLK_STATE_NOT_READY | 0               | 45    | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3               | CLK_STATE_NOT_READY | 0               | 50    | DEV_MCASP1_MCASP_AHCLKX_POUT                                                        | CLK_STATE_READY     | 0               | 51    | DEV_MCASP1_VBUSP_CLK                                                                | CLK_STATE_READY     | 250000000       | 0    | DEV_MCASP2_AUX_CLK                                                                  | CLK_STATE_READY     | 196608000       | 1    | DEV_MCASP2_AUX_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK                         | CLK_STATE_READY     | 196608000       | 2    | DEV_MCASP2_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK                         | CLK_STATE_READY     | 200000000       | 5    | DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT                          | CLK_STATE_NOT_READY | 0               | 6    | DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1                        | CLK_STATE_NOT_READY | 0               | 7    | DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2                        | CLK_STATE_NOT_READY | 0               | 8    | DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3                        | CLK_STATE_NOT_READY | 0               | 9    | DEV_MCASP2_MCASP_ACLKR_PIN                                                          | CLK_STATE_READY     | 0               | 10    | DEV_MCASP2_MCASP_ACLKR_POUT                                                         | CLK_STATE_READY     | 0               | 11    | DEV_MCASP2_MCASP_ACLKX_PIN                                                          | CLK_STATE_READY     | 0               | 12    | DEV_MCASP2_MCASP_ACLKX_POUT                                                         | CLK_STATE_READY     | 0               | 13    | DEV_MCASP2_MCASP_AFSR_POUT                                                          | CLK_STATE_READY     | 0               | 14    | DEV_MCASP2_MCASP_AFSX_POUT                                                          | CLK_STATE_READY     | 0               | 15    | DEV_MCASP2_MCASP_AHCLKR_PIN                                                         | CLK_STATE_READY     | 0               | 16    | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT                           | CLK_STATE_READY     | 0               | 17    | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT                          | CLK_STATE_READY     | 24000000        | 18    | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT                    | CLK_STATE_READY     | 0               | 19    | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT                    | CLK_STATE_READY     | 0               | 24    | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT                 | CLK_STATE_NOT_READY | 0               | 25    | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1               | CLK_STATE_NOT_READY | 0               | 26    | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2               | CLK_STATE_NOT_READY | 0               | 27    | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3               | CLK_STATE_NOT_READY | 0               | 32    | DEV_MCASP2_MCASP_AHCLKR_POUT                                                        | CLK_STATE_READY     | 0               | 33    | DEV_MCASP2_MCASP_AHCLKX_PIN                                                         | CLK_STATE_READY     | 0               | 34    | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT                           | CLK_STATE_READY     | 0               | 35    | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT                          | CLK_STATE_READY     | 24000000        | 36    | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT                    | CLK_STATE_READY     | 0               | 37    | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT                    | CLK_STATE_READY     | 0               | 42    | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT                 | CLK_STATE_NOT_READY | 0               | 43    | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1               | CLK_STATE_NOT_READY | 0               | 44    | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2               | CLK_STATE_NOT_READY | 0               | 45    | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3               | CLK_STATE_NOT_READY | 0               | 50    | DEV_MCASP2_MCASP_AHCLKX_POUT                                                        | CLK_STATE_READY     | 0               | 51    | DEV_MCASP2_VBUSP_CLK                                                                | CLK_STATE_READY     | 250000000       | 0    | DEV_MCASP3_AUX_CLK                                                                  | CLK_STATE_READY     | 196608000       | 1    | DEV_MCASP3_AUX_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK                         | CLK_STATE_READY     | 196608000       | 2    | DEV_MCASP3_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK                         | CLK_STATE_READY     | 200000000       | 5    | DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT                          | CLK_STATE_NOT_READY | 0               | 6    | DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1                        | CLK_STATE_NOT_READY | 0               | 7    | DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2                        | CLK_STATE_NOT_READY | 0               | 8    | DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3                        | CLK_STATE_NOT_READY | 0               | 9    | DEV_MCASP3_MCASP_ACLKR_PIN                                                          | CLK_STATE_READY     | 0               | 10    | DEV_MCASP3_MCASP_ACLKR_POUT                                                         | CLK_STATE_READY     | 0               | 11    | DEV_MCASP3_MCASP_ACLKX_PIN                                                          | CLK_STATE_READY     | 0               | 12    | DEV_MCASP3_MCASP_ACLKX_POUT                                                         | CLK_STATE_READY     | 0               | 13    | DEV_MCASP3_MCASP_AFSR_POUT                                                          | CLK_STATE_READY     | 0               | 14    | DEV_MCASP3_MCASP_AFSX_POUT                                                          | CLK_STATE_READY     | 0               | 15    | DEV_MCASP3_MCASP_AHCLKR_PIN                                                         | CLK_STATE_READY     | 0               | 16    | DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT                           | CLK_STATE_READY     | 0               | 17    | DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT                          | CLK_STATE_READY     | 24000000        | 18    | DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT                    | CLK_STATE_READY     | 0               | 19    | DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT                    | CLK_STATE_READY     | 0               | 24    | DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT                 | CLK_STATE_NOT_READY | 0               | 25    | DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1               | CLK_STATE_NOT_READY | 0               | 26    | DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2               | CLK_STATE_NOT_READY | 0               | 27    | DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3               | CLK_STATE_NOT_READY | 0               | 32    | DEV_MCASP3_MCASP_AHCLKR_POUT                                                        | CLK_STATE_READY     | 0               | 33    | DEV_MCASP3_MCASP_AHCLKX_PIN                                                         | CLK_STATE_READY     | 0               | 34    | DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT                           | CLK_STATE_READY     | 0               | 35    | DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT                          | CLK_STATE_READY     | 24000000        | 36    | DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT                    | CLK_STATE_READY     | 0               | 37    | DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT                    | CLK_STATE_READY     | 0               | 42    | DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT                 | CLK_STATE_NOT_READY | 0               | 43    | DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1               | CLK_STATE_NOT_READY | 0               | 44    | DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2               | CLK_STATE_NOT_READY | 0               | 45    | DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3               | CLK_STATE_NOT_READY | 0               | 50    | DEV_MCASP3_MCASP_AHCLKX_POUT                                                        | CLK_STATE_READY     | 0               | 51    | DEV_MCASP3_VBUSP_CLK                                                                | CLK_STATE_READY     | 250000000       | 0    | DEV_MCASP4_AUX_CLK                                                                  | CLK_STATE_READY     | 196608000       | 1    | DEV_MCASP4_AUX_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK                         | CLK_STATE_READY     | 196608000       | 2    | DEV_MCASP4_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK                         | CLK_STATE_READY     | 200000000       | 5    | DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT                          | CLK_STATE_NOT_READY | 0               | 6    | DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1                        | CLK_STATE_NOT_READY | 0               | 7    | DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2                        | CLK_STATE_NOT_READY | 0               | 8    | DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3                        | CLK_STATE_NOT_READY | 0               | 9    | DEV_MCASP4_MCASP_ACLKR_PIN                                                          | CLK_STATE_READY     | 0               | 10    | DEV_MCASP4_MCASP_ACLKR_POUT                                                         | CLK_STATE_READY     | 0               | 11    | DEV_MCASP4_MCASP_ACLKX_PIN                                                          | CLK_STATE_READY     | 0               | 12    | DEV_MCASP4_MCASP_ACLKX_POUT                                                         | CLK_STATE_READY     | 0               | 13    | DEV_MCASP4_MCASP_AFSR_POUT                                                          | CLK_STATE_READY     | 0               | 14    | DEV_MCASP4_MCASP_AFSX_POUT                                                          | CLK_STATE_READY     | 0               | 15    | DEV_MCASP4_MCASP_AHCLKR_PIN                                                         | CLK_STATE_READY     | 0               | 16    | DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT                           | CLK_STATE_READY     | 0               | 17    | DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT                          | CLK_STATE_READY     | 24000000        | 18    | DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT                    | CLK_STATE_READY     | 0               | 19    | DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT                    | CLK_STATE_READY     | 0               | 24    | DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT                 | CLK_STATE_NOT_READY | 0               | 25    | DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1               | CLK_STATE_NOT_READY | 0               | 26    | DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2               | CLK_STATE_NOT_READY | 0               | 27    | DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3               | CLK_STATE_NOT_READY | 0               | 32    | DEV_MCASP4_MCASP_AHCLKR_POUT                                                        | CLK_STATE_READY     | 0               | 33    | DEV_MCASP4_MCASP_AHCLKX_PIN                                                         | CLK_STATE_READY     | 0               | 34    | DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT                           | CLK_STATE_READY     | 0               | 35    | DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT                          | CLK_STATE_READY     | 24000000        | 36    | DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT                    | CLK_STATE_READY     | 0               | 37    | DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT                    | CLK_STATE_READY     | 0               | 42    | DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT                 | CLK_STATE_NOT_READY | 0               | 43    | DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1               | CLK_STATE_NOT_READY | 0               | 44    | DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2               | CLK_STATE_NOT_READY | 0               | 45    | DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3               | CLK_STATE_NOT_READY | 0               | 50    | DEV_MCASP4_MCASP_AHCLKX_POUT                                                        | CLK_STATE_READY     | 0               | 51    | DEV_MCASP4_VBUSP_CLK                                                                | CLK_STATE_READY     | 250000000       | 0    | DEV_MCSPI0_CLKSPIREF_CLK                                                            | CLK_STATE_READY     | 50000000        | 1    | DEV_MCSPI0_IO_CLKSPII_CLK                                                           | CLK_STATE_READY     | 0               | 2    | DEV_MCSPI0_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI0_CLK_OUT                               | CLK_STATE_READY     | 0               | 3    | DEV_MCSPI0_IO_CLKSPII_CLK_PARENT_SPI_MAIN_0_IO_CLKSPIO_CLK                          | CLK_STATE_NOT_READY | 0               | 4    | DEV_MCSPI0_IO_CLKSPIO_CLK                                                           | CLK_STATE_READY     | 0               | 5    | DEV_MCSPI0_VBUSP_CLK                                                                | CLK_STATE_READY     | 125000000       | 0    | DEV_MCSPI1_CLKSPIREF_CLK                                                            | CLK_STATE_READY     | 50000000        | 1    | DEV_MCSPI1_IO_CLKSPII_CLK                                                           | CLK_STATE_READY     | 0               | 2    | DEV_MCSPI1_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI1_CLK_OUT                               | CLK_STATE_READY     | 0               | 3    | DEV_MCSPI1_IO_CLKSPII_CLK_PARENT_SPI_MAIN_1_IO_CLKSPIO_CLK                          | CLK_STATE_NOT_READY | 0               | 4    | DEV_MCSPI1_IO_CLKSPIO_CLK                                                           | CLK_STATE_READY     | 0               | 5    | DEV_MCSPI1_VBUSP_CLK                                                                | CLK_STATE_READY     | 125000000       | 0    | DEV_MCSPI2_CLKSPIREF_CLK                                                            | CLK_STATE_READY     | 50000000        | 1    | DEV_MCSPI2_IO_CLKSPII_CLK                                                           | CLK_STATE_READY     | 0               | 2    | DEV_MCSPI2_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI2_CLK_OUT                               | CLK_STATE_READY     | 0               | 3    | DEV_MCSPI2_IO_CLKSPII_CLK_PARENT_SPI_MAIN_2_IO_CLKSPIO_CLK                          | CLK_STATE_NOT_READY | 0               | 4    | DEV_MCSPI2_IO_CLKSPIO_CLK                                                           | CLK_STATE_READY     | 0               | 5    | DEV_MCSPI2_VBUSP_CLK                                                                | CLK_STATE_READY     | 125000000       | 0    | DEV_MCSPI3_CLKSPIREF_CLK                                                            | CLK_STATE_READY     | 50000000        | 1    | DEV_MCSPI3_IO_CLKSPII_CLK                                                           | CLK_STATE_NOT_READY | 0               | 2    | DEV_MCSPI3_IO_CLKSPII_CLK_PARENT_SPI_MAIN_3_IO_CLKSPIO_CLK                          | CLK_STATE_NOT_READY | 0               | 3    | DEV_MCSPI3_IO_CLKSPII_CLK_PARENT_SPI3_CLK_LPBK_MUX_OUT0                             | CLK_STATE_READY     | 0               | 4    | DEV_MCSPI3_IO_CLKSPIO_CLK                                                           | CLK_STATE_READY     | 0               | 5    | DEV_MCSPI3_VBUSP_CLK                                                                | CLK_STATE_READY     | 125000000       | 0    | DEV_MCSPI4_CLKSPIREF_CLK                                                            | CLK_STATE_READY     | 50000000        | 1    | DEV_MCSPI4_IO_CLKSPII_CLK                                                           | CLK_STATE_READY     | 0               | 2    | DEV_MCSPI4_IO_CLKSPIO_CLK                                                           | CLK_STATE_READY     | 0               | 3    | DEV_MCSPI4_VBUSP_CLK                                                                | CLK_STATE_READY     | 125000000       | 0    | DEV_MCSPI5_CLKSPIREF_CLK                                                            | CLK_STATE_READY     | 50000000        | 1    | DEV_MCSPI5_IO_CLKSPII_CLK                                                           | CLK_STATE_READY     | 0               | 2    | DEV_MCSPI5_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI5_CLK_OUT                               | CLK_STATE_READY     | 0               | 3    | DEV_MCSPI5_IO_CLKSPII_CLK_PARENT_SPI_MAIN_5_IO_CLKSPIO_CLK                          | CLK_STATE_NOT_READY | 0               | 4    | DEV_MCSPI5_IO_CLKSPIO_CLK                                                           | CLK_STATE_READY     | 0               | 5    | DEV_MCSPI5_VBUSP_CLK                                                                | CLK_STATE_READY     | 125000000       | 0    | DEV_MCSPI6_CLKSPIREF_CLK                                                            | CLK_STATE_READY     | 50000000        | 1    | DEV_MCSPI6_IO_CLKSPII_CLK                                                           | CLK_STATE_READY     | 0               | 2    | DEV_MCSPI6_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI6_CLK_OUT                               | CLK_STATE_READY     | 0               | 3    | DEV_MCSPI6_IO_CLKSPII_CLK_PARENT_SPI_MAIN_6_IO_CLKSPIO_CLK                          | CLK_STATE_NOT_READY | 0               | 4    | DEV_MCSPI6_IO_CLKSPIO_CLK                                                           | CLK_STATE_READY     | 0               | 5    | DEV_MCSPI6_VBUSP_CLK                                                                | CLK_STATE_READY     | 125000000       | 0    | DEV_MCSPI7_CLKSPIREF_CLK                                                            | CLK_STATE_READY     | 50000000        | 1    | DEV_MCSPI7_IO_CLKSPII_CLK                                                           | CLK_STATE_READY     | 0               | 2    | DEV_MCSPI7_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI7_CLK_OUT                               | CLK_STATE_READY     | 0               | 3    | DEV_MCSPI7_IO_CLKSPII_CLK_PARENT_SPI_MAIN_7_IO_CLKSPIO_CLK                          | CLK_STATE_NOT_READY | 0               | 4    | DEV_MCSPI7_IO_CLKSPIO_CLK                                                           | CLK_STATE_READY     | 0               | 5    | DEV_MCSPI7_VBUSP_CLK                                                                | CLK_STATE_READY     | 125000000       | 0    | DEV_MCU_ADC12FC_16FFC0_ADC_CLK                                                      | CLK_STATE_READY     | 24000000        | 1    | DEV_MCU_ADC12FC_16FFC0_ADC_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                       | CLK_STATE_READY     | 24000000        | 2    | DEV_MCU_ADC12FC_16FFC0_ADC_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT1_CLK              | CLK_STATE_READY     | 60000000        | 3    | DEV_MCU_ADC12FC_16FFC0_ADC_CLK_PARENT_HSDIV1_16FFT_MCU_0_HSDIVOUT1_CLK              | CLK_STATE_READY     | 58823529        | 4    | DEV_MCU_ADC12FC_16FFC0_ADC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                   | CLK_STATE_READY     | 0               | 5    | DEV_MCU_ADC12FC_16FFC0_SYS_CLK                                                      | CLK_STATE_READY     | 500000000       | 6    | DEV_MCU_ADC12FC_16FFC0_VBUS_CLK                                                     | CLK_STATE_READY     | 333333333       | 0    | DEV_MCU_ADC12FC_16FFC1_ADC_CLK                                                      | CLK_STATE_READY     | 24000000        | 1    | DEV_MCU_ADC12FC_16FFC1_ADC_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                       | CLK_STATE_READY     | 24000000        | 2    | DEV_MCU_ADC12FC_16FFC1_ADC_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT1_CLK              | CLK_STATE_READY     | 60000000        | 3    | DEV_MCU_ADC12FC_16FFC1_ADC_CLK_PARENT_HSDIV1_16FFT_MCU_0_HSDIVOUT1_CLK              | CLK_STATE_READY     | 58823529        | 4    | DEV_MCU_ADC12FC_16FFC1_ADC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                   | CLK_STATE_READY     | 0               | 5    | DEV_MCU_ADC12FC_16FFC1_SYS_CLK                                                      | CLK_STATE_READY     | 500000000       | 6    | DEV_MCU_ADC12FC_16FFC1_VBUS_CLK                                                     | CLK_STATE_READY     | 333333333       | 0    | DEV_MCU_CPSW0_CPPI_CLK_CLK                                                          | CLK_STATE_READY     | 333333333       | 1    | DEV_MCU_CPSW0_CPTS_GENF0                                                            | CLK_STATE_READY     | 0               | 3    | DEV_MCU_CPSW0_CPTS_RFT_CLK                                                          | CLK_STATE_READY     | 500000000       | 4    | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK                 | CLK_STATE_READY     | 250000000       | 5    | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK               | CLK_STATE_READY     | 200000000       | 6    | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT                     | CLK_STATE_READY     | 0               | 7    | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT                         | CLK_STATE_READY     | 0               | 8    | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                       | CLK_STATE_READY     | 0               | 9    | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT                           | CLK_STATE_READY     | 0               | 10    | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN0_TXMCLK                | CLK_STATE_READY     | 0               | 11    | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN1_TXMCLK                | CLK_STATE_READY     | 0               | 12    | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN2_TXMCLK                | CLK_STATE_READY     | 0               | 13    | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN3_TXMCLK                | CLK_STATE_READY     | 0               | 14    | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN0_TXMCLK                | CLK_STATE_READY     | 0               | 15    | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN1_TXMCLK                | CLK_STATE_READY     | 0               | 16    | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP1_LN2_TXMCLK                | CLK_STATE_READY     | 0               | 17    | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP3_LN2_TXMCLK                | CLK_STATE_READY     | 0               | 18    | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK                  | CLK_STATE_READY     | 500000000       | 19    | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK2        | CLK_STATE_READY     | 500000000       | 20    | DEV_MCU_CPSW0_GMII1_MR_CLK                                                          | CLK_STATE_READY     | 25000000        | 21    | DEV_MCU_CPSW0_GMII1_MT_CLK                                                          | CLK_STATE_READY     | 25000000        | 22    | DEV_MCU_CPSW0_GMII_RFT_CLK                                                          | CLK_STATE_READY     | 125000000       | 23    | DEV_MCU_CPSW0_MDIO_MDCLK_O                                                          | CLK_STATE_READY     | 0               | 24    | DEV_MCU_CPSW0_RGMII1_RXC_I                                                          | CLK_STATE_READY     | 0               | 26    | DEV_MCU_CPSW0_RGMII1_TXC_O                                                          | CLK_STATE_READY     | 0               | 27    | DEV_MCU_CPSW0_RGMII_MHZ_250_CLK                                                     | CLK_STATE_READY     | 250000000       | 28    | DEV_MCU_CPSW0_RGMII_MHZ_50_CLK                                                      | CLK_STATE_READY     | 50000000        | 29    | DEV_MCU_CPSW0_RGMII_MHZ_5_CLK                                                       | CLK_STATE_READY     | 5000000         | 30    | DEV_MCU_CPSW0_RMII_MHZ_50_CLK                                                       | CLK_STATE_READY     | 0               | 0    | DEV_MCU_CPT2_AGGR0_VCLK_CLK                                                         | CLK_STATE_READY     | 333333333       | 0    | DEV_MCU_DCC0_DCC_CLKSRC0_CLK                                                        | CLK_STATE_READY     | 200000000       | 1    | DEV_MCU_DCC0_DCC_CLKSRC1_CLK                                                        | CLK_STATE_READY     | 60000000        | 2    | DEV_MCU_DCC0_DCC_CLKSRC2_CLK                                                        | CLK_STATE_READY     | 80000000        | 3    | DEV_MCU_DCC0_DCC_CLKSRC3_CLK                                                        | CLK_STATE_READY     | 96000000        | 4    | DEV_MCU_DCC0_DCC_CLKSRC4_CLK                                                        | CLK_STATE_READY     | 133333333       | 5    | DEV_MCU_DCC0_DCC_CLKSRC5_CLK                                                        | CLK_STATE_READY     | 32000           | 6    | DEV_MCU_DCC0_DCC_CLKSRC6_CLK                                                        | CLK_STATE_READY     | 32768           | 7    | DEV_MCU_DCC0_DCC_CLKSRC7_CLK                                                        | CLK_STATE_READY     | 0               | 8    | DEV_MCU_DCC0_DCC_INPUT00_CLK                                                        | CLK_STATE_READY     | 24000000        | 9    | DEV_MCU_DCC0_DCC_INPUT01_CLK                                                        | CLK_STATE_READY     | 32000           | 10    | DEV_MCU_DCC0_DCC_INPUT02_CLK                                                        | CLK_STATE_READY     | 12500000        | 11    | DEV_MCU_DCC0_DCC_INPUT10_CLK                                                        | CLK_STATE_READY     | 333333333       | 12    | DEV_MCU_DCC0_VBUS_CLK                                                               | CLK_STATE_READY     | 166666666       | 0    | DEV_MCU_DCC1_DCC_CLKSRC0_CLK                                                        | CLK_STATE_READY     | 250000000       | 1    | DEV_MCU_DCC1_DCC_CLKSRC1_CLK                                                        | CLK_STATE_READY     | 200000000       | 2    | DEV_MCU_DCC1_DCC_CLKSRC2_CLK                                                        | CLK_STATE_READY     | 80000000        | 3    | DEV_MCU_DCC1_DCC_CLKSRC3_CLK                                                        | CLK_STATE_READY     | 166666666       | 4    | DEV_MCU_DCC1_DCC_CLKSRC4_CLK                                                        | CLK_STATE_READY     | 250000000       | 5    | DEV_MCU_DCC1_DCC_CLKSRC5_CLK                                                        | CLK_STATE_READY     | 58823529        | 6    | DEV_MCU_DCC1_DCC_CLKSRC6_CLK                                                        | CLK_STATE_READY     | 0               | 7    | DEV_MCU_DCC1_DCC_CLKSRC7_CLK                                                        | CLK_STATE_READY     | 500000000       | 8    | DEV_MCU_DCC1_DCC_INPUT00_CLK                                                        | CLK_STATE_READY     | 24000000        | 9    | DEV_MCU_DCC1_DCC_INPUT01_CLK                                                        | CLK_STATE_READY     | 32768           | 10    | DEV_MCU_DCC1_DCC_INPUT02_CLK                                                        | CLK_STATE_READY     | 12500000        | 11    | DEV_MCU_DCC1_DCC_INPUT10_CLK                                                        | CLK_STATE_READY     | 250000000       | 12    | DEV_MCU_DCC1_VBUS_CLK                                                               | CLK_STATE_READY     | 166666666       | 0    | DEV_MCU_DCC2_DCC_CLKSRC0_CLK                                                        | CLK_STATE_READY     | 0               | 1    | DEV_MCU_DCC2_DCC_CLKSRC1_CLK                                                        | CLK_STATE_READY     | 0               | 2    | DEV_MCU_DCC2_DCC_CLKSRC2_CLK                                                        | CLK_STATE_READY     | 0               | 3    | DEV_MCU_DCC2_DCC_CLKSRC3_CLK                                                        | CLK_STATE_READY     | 192000000       | 4    | DEV_MCU_DCC2_DCC_CLKSRC4_CLK                                                        | CLK_STATE_READY     | 0               | 6    | DEV_MCU_DCC2_DCC_CLKSRC6_CLK                                                        | CLK_STATE_READY     | 12500000        | 7    | DEV_MCU_DCC2_DCC_CLKSRC7_CLK                                                        | CLK_STATE_READY     | 24000000        | 8    | DEV_MCU_DCC2_DCC_INPUT00_CLK                                                        | CLK_STATE_READY     | 24000000        | 9    | DEV_MCU_DCC2_DCC_INPUT01_CLK                                                        | CLK_STATE_READY     | 0               | 10    | DEV_MCU_DCC2_DCC_INPUT02_CLK                                                        | CLK_STATE_READY     | 12500000        | 11    | DEV_MCU_DCC2_DCC_INPUT10_CLK                                                        | CLK_STATE_READY     | 333333333       | 12    | DEV_MCU_DCC2_VBUS_CLK                                                               | CLK_STATE_READY     | 166666666       | 0    | DEV_MCU_ESM0_CLK                                                                    | CLK_STATE_READY     | 166666666       | 0    | DEV_MCU_FSS0_FSAS_0_GCLK                                                            | CLK_STATE_READY     | 1000000000      | 0    | DEV_MCU_FSS0_HYPERBUS1P0_0_CBA_CLK                                                  | CLK_STATE_READY     | 1000000000      | 2    | DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX1_CLK                                            | CLK_STATE_READY     | 83333333        | 4    | DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX1_INV_CLK                                        | CLK_STATE_READY     | 83333333        | 6    | DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX2_CLK                                            | CLK_STATE_READY     | 166666666       | 8    | DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX2_INV_CLK                                        | CLK_STATE_READY     | 166666666       | 10    | DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_OUT_CLK_N                                            | CLK_STATE_READY     | 0               | 11    | DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_OUT_CLK_P                                            | CLK_STATE_READY     | 0               | 0    | DEV_MCU_FSS0_OSPI_0_OSPI_DQS_CLK                                                    | CLK_STATE_READY     | 0               | 1    | DEV_MCU_FSS0_OSPI_0_OSPI_HCLK_CLK                                                   | CLK_STATE_READY     | 1000000000      | 2    | DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK                                                   | CLK_STATE_READY     | 0               | 3    | DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_BOARD_0_MCU_OSPI0_DQS_OUT                  | CLK_STATE_READY     | 0               | 4    | DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_FSS_MCU_0_OSPI_0_OSPI_OCLK_CLK             | CLK_STATE_NOT_READY | 0               | 5    | DEV_MCU_FSS0_OSPI_0_OSPI_OCLK_CLK                                                   | CLK_STATE_READY     | 0               | 6    | DEV_MCU_FSS0_OSPI_0_OSPI_PCLK_CLK                                                   | CLK_STATE_READY     | 1000000000      | 7    | DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK                                                   | CLK_STATE_READY     | 166666666       | 8    | DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT4_CLK           | CLK_STATE_READY     | 133333333       | 9    | DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT4_CLK           | CLK_STATE_READY     | 166666666       | 0    | DEV_MCU_FSS0_OSPI_1_OSPI_DQS_CLK                                                    | CLK_STATE_READY     | 0               | 1    | DEV_MCU_FSS0_OSPI_1_OSPI_HCLK_CLK                                                   | CLK_STATE_READY     | 1000000000      | 2    | DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK                                                   | CLK_STATE_READY     | 0               | 3    | DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK_PARENT_BOARD_0_MCU_OSPI1_DQS_OUT                  | CLK_STATE_READY     | 0               | 4    | DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK_PARENT_FSS_MCU_0_OSPI_1_OSPI_OCLK_CLK             | CLK_STATE_READY     | 0               | 5    | DEV_MCU_FSS0_OSPI_1_OSPI_OCLK_CLK                                                   | CLK_STATE_READY     | 0               | 6    | DEV_MCU_FSS0_OSPI_1_OSPI_PCLK_CLK                                                   | CLK_STATE_READY     | 1000000000      | 7    | DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK                                                   | CLK_STATE_READY     | 133333333       | 8    | DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT4_CLK           | CLK_STATE_READY     | 133333333       | 9    | DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT4_CLK           | CLK_STATE_READY     | 166666666       | 0    | DEV_MCU_I2C0_CLK                                                                    | CLK_STATE_READY     | 166666666       | 1    | DEV_MCU_I2C0_PISCL                                                                  | CLK_STATE_READY     | 0               | 2    | DEV_MCU_I2C0_PISYS_CLK                                                              | CLK_STATE_READY     | 96000000        | 3    | DEV_MCU_I2C0_PORSCL                                                                 | CLK_STATE_READY     | 0               | 0    | DEV_MCU_I2C1_CLK                                                                    | CLK_STATE_READY     | 166666666       | 1    | DEV_MCU_I2C1_PISCL                                                                  | CLK_STATE_READY     | 0               | 2    | DEV_MCU_I2C1_PISYS_CLK                                                              | CLK_STATE_READY     | 96000000        | 3    | DEV_MCU_I2C1_PORSCL                                                                 | CLK_STATE_READY     | 0               | 0    | DEV_MCU_I3C0_I3C_PCLK_CLK                                                           | CLK_STATE_READY     | 166666666       | 1    | DEV_MCU_I3C0_I3C_SCL_DI                                                             | CLK_STATE_READY     | 0               | 2    | DEV_MCU_I3C0_I3C_SCL_DO                                                             | CLK_STATE_READY     | 0               | 3    | DEV_MCU_I3C0_I3C_SCLK_CLK                                                           | CLK_STATE_READY     | 166666666       | 4    | DEV_MCU_I3C0_I3C_SDA_DI                                                             | CLK_STATE_READY     | 0               | 0    | DEV_MCU_I3C1_I3C_PCLK_CLK                                                           | CLK_STATE_READY     | 166666666       | 3    | DEV_MCU_I3C1_I3C_SCLK_CLK                                                           | CLK_STATE_READY     | 166666666       | 0    | DEV_MCU_MCAN0_MCANSS_CAN_RXD                                                        | CLK_STATE_READY     | 0               | 1    | DEV_MCU_MCAN0_MCANSS_CCLK_CLK                                                       | CLK_STATE_READY     | 80000000        | 2    | DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT3_CLK               | CLK_STATE_READY     | 80000000        | 3    | DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                    | CLK_STATE_READY     | 0               | 4    | DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT2_CLK               | CLK_STATE_READY     | 80000000        | 5    | DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                        | CLK_STATE_READY     | 24000000        | 6    | DEV_MCU_MCAN0_MCANSS_HCLK_CLK                                                       | CLK_STATE_READY     | 166666666       | 0    | DEV_MCU_MCAN1_MCANSS_CAN_RXD                                                        | CLK_STATE_READY     | 0               | 1    | DEV_MCU_MCAN1_MCANSS_CCLK_CLK                                                       | CLK_STATE_READY     | 80000000        | 2    | DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT3_CLK               | CLK_STATE_READY     | 80000000        | 3    | DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                    | CLK_STATE_READY     | 0               | 4    | DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT2_CLK               | CLK_STATE_READY     | 80000000        | 5    | DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                        | CLK_STATE_READY     | 24000000        | 6    | DEV_MCU_MCAN1_MCANSS_HCLK_CLK                                                       | CLK_STATE_READY     | 166666666       | 0    | DEV_MCU_MCSPI0_CLKSPIREF_CLK                                                        | CLK_STATE_READY     | 50000000        | 1    | DEV_MCU_MCSPI0_IO_CLKSPII_CLK                                                       | CLK_STATE_READY     | 0               | 2    | DEV_MCU_MCSPI0_IO_CLKSPII_CLK_PARENT_BOARD_0_MCU_SPI0_CLK_OUT                       | CLK_STATE_READY     | 0               | 3    | DEV_MCU_MCSPI0_IO_CLKSPII_CLK_PARENT_SPI_MCU_0_IO_CLKSPIO_CLK                       | CLK_STATE_READY     | 0               | 4    | DEV_MCU_MCSPI0_IO_CLKSPIO_CLK                                                       | CLK_STATE_READY     | 0               | 5    | DEV_MCU_MCSPI0_VBUSP_CLK                                                            | CLK_STATE_READY     | 166666666       | 0    | DEV_MCU_MCSPI1_CLKSPIREF_CLK                                                        | CLK_STATE_READY     | 50000000        | 1    | DEV_MCU_MCSPI1_IO_CLKSPII_CLK                                                       | CLK_STATE_NOT_READY | 0               | 2    | DEV_MCU_MCSPI1_IO_CLKSPII_CLK_PARENT_SPI_MAIN_3_IO_CLKSPIO_CLK                      | CLK_STATE_NOT_READY | 0               | 3    | DEV_MCU_MCSPI1_IO_CLKSPII_CLK_PARENT_MCU_SPI1_CLK_LPBK_MUX_OUT0                     | CLK_STATE_READY     | 0               | 4    | DEV_MCU_MCSPI1_IO_CLKSPIO_CLK                                                       | CLK_STATE_READY     | 0               | 5    | DEV_MCU_MCSPI1_VBUSP_CLK                                                            | CLK_STATE_READY     | 166666666       | 0    | DEV_MCU_MCSPI2_CLKSPIREF_CLK                                                        | CLK_STATE_READY     | 50000000        | 1    | DEV_MCU_MCSPI2_IO_CLKSPII_CLK                                                       | CLK_STATE_READY     | 0               | 2    | DEV_MCU_MCSPI2_IO_CLKSPIO_CLK                                                       | CLK_STATE_READY     | 0               | 3    | DEV_MCU_MCSPI2_VBUSP_CLK                                                            | CLK_STATE_READY     | 166666666       | 0    | DEV_MCU_NAVSS0_INTR_ROUTER_0_INTR_CLK                                               | CLK_STATE_READY     | 1000000000      | 0    | DEV_MCU_NAVSS0_MCRC_0_CLK                                                           | CLK_STATE_READY     | 1000000000      | 0    | DEV_MCU_NAVSS0_MODSS_VD2CLK                                                         | CLK_STATE_READY     | 1000000000      | 0    | DEV_MCU_NAVSS0_PROXY0_CLK_CLK                                                       | CLK_STATE_READY     | 1000000000      | 0    | DEV_MCU_NAVSS0_RINGACC0_SYS_CLK                                                     | CLK_STATE_READY     | 1000000000      | 0    | DEV_MCU_NAVSS0_UDMAP_0_SYS_CLK                                                      | CLK_STATE_READY     | 1000000000      | 0    | DEV_MCU_NAVSS0_UDMASS_VD2CLK                                                        | CLK_STATE_READY     | 1000000000      | 0    | DEV_MCU_NAVSS0_UDMASS_INTA_0_SYS_CLK                                                | CLK_STATE_READY     | 1000000000      | 0    | DEV_MCU_PBIST0_CLK1_CLK                                                             | CLK_STATE_READY     | 500000000       | 1    | DEV_MCU_PBIST0_CLK2_CLK                                                             | CLK_STATE_READY     | 333333333       | 2    | DEV_MCU_PBIST0_CLK3_CLK                                                             | CLK_STATE_READY     | 166666666       | 3    | DEV_MCU_PBIST0_CLK4_CLK                                                             | CLK_STATE_READY     | 83333333        | 4    | DEV_MCU_PBIST0_CLK5_CLK                                                             | CLK_STATE_READY     | 83333333        | 5    | DEV_MCU_PBIST0_CLK6_CLK                                                             | CLK_STATE_READY     | 83333333        | 6    | DEV_MCU_PBIST0_CLK7_CLK                                                             | CLK_STATE_READY     | 83333333        | 7    | DEV_MCU_PBIST0_CLK8_CLK                                                             | CLK_STATE_READY     | 83333333        | 0    | DEV_MCU_PBIST1_CLK1_CLK                                                             | CLK_STATE_READY     | 500000000       | 1    | DEV_MCU_PBIST1_CLK2_CLK                                                             | CLK_STATE_READY     | 400000000       | 2    | DEV_MCU_PBIST1_CLK3_CLK                                                             | CLK_STATE_READY     | 333333333       | 3    | DEV_MCU_PBIST1_CLK4_CLK                                                             | CLK_STATE_READY     | 83333333        | 4    | DEV_MCU_PBIST1_CLK5_CLK                                                             | CLK_STATE_READY     | 166666666       | 5    | DEV_MCU_PBIST1_CLK6_CLK                                                             | CLK_STATE_READY     | 83333333        | 6    | DEV_MCU_PBIST1_CLK7_CLK                                                             | CLK_STATE_READY     | 83333333        | 7    | DEV_MCU_PBIST1_CLK8_CLK                                                             | CLK_STATE_READY     | 83333333        | 7    | DEV_MCU_PBIST2_CLK8_CLK                                                             | CLK_STATE_READY     | 83333333        | 0    | DEV_MCU_R5FSS0_CORE0_CPU_CLK                                                        | CLK_STATE_READY     | 1000000000      | 1    | DEV_MCU_R5FSS0_CORE0_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK       | CLK_STATE_READY     | 1000000000      | 2    | DEV_MCU_R5FSS0_CORE0_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK3      | CLK_STATE_READY     | 333333333       | 3    | DEV_MCU_R5FSS0_CORE0_INTERFACE_CLK                                                  | CLK_STATE_READY     | 1000000000      | 4    | DEV_MCU_R5FSS0_CORE0_INTERFACE_PHASE                                                | CLK_STATE_READY     | 333333333       | 0    | DEV_MCU_R5FSS0_CORE1_CPU_CLK                                                        | CLK_STATE_READY     | 1000000000      | 1    | DEV_MCU_R5FSS0_CORE1_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK       | CLK_STATE_READY     | 1000000000      | 2    | DEV_MCU_R5FSS0_CORE1_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK3      | CLK_STATE_READY     | 333333333       | 3    | DEV_MCU_R5FSS0_CORE1_INTERFACE_CLK                                                  | CLK_STATE_READY     | 1000000000      | 4    | DEV_MCU_R5FSS0_CORE1_INTERFACE_PHASE                                                | CLK_STATE_READY     | 333333333       | 0    | DEV_MCU_RTI0_RTI_CLK                                                                | CLK_STATE_READY     | 24000000        | 1    | DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                                 | CLK_STATE_READY     | 24000000        | 2    | DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                                 | CLK_STATE_READY     | 32768           | 3    | DEV_MCU_RTI0_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK            | CLK_STATE_READY     | 12500000        | 4    | DEV_MCU_RTI0_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK              | CLK_STATE_READY     | 32000           | 9    | DEV_MCU_RTI0_VBUSP_CLK                                                              | CLK_STATE_READY     | 166666666       | 0    | DEV_MCU_RTI1_RTI_CLK                                                                | CLK_STATE_READY     | 24000000        | 1    | DEV_MCU_RTI1_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                                 | CLK_STATE_READY     | 24000000        | 2    | DEV_MCU_RTI1_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                                 | CLK_STATE_READY     | 32768           | 3    | DEV_MCU_RTI1_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK            | CLK_STATE_READY     | 12500000        | 4    | DEV_MCU_RTI1_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK              | CLK_STATE_READY     | 32000           | 9    | DEV_MCU_RTI1_VBUSP_CLK                                                              | CLK_STATE_READY     | 166666666       | 0    | DEV_MCU_TIMER0_TIMER_HCLK_CLK                                                       | CLK_STATE_READY     | 166666666       | 1    | DEV_MCU_TIMER0_TIMER_PWM                                                            | CLK_STATE_READY     | 0               | 2    | DEV_MCU_TIMER0_TIMER_TCLK_CLK                                                       | CLK_STATE_READY     | 62500000        | 3    | DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                        | CLK_STATE_READY     | 24000000        | 4    | DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16    | CLK_STATE_READY     | 62500000        | 5    | DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK   | CLK_STATE_READY     | 12500000        | 6    | DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK               | CLK_STATE_READY     | 200000000       | 7    | DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                    | CLK_STATE_READY     | 0               | 8    | DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                        | CLK_STATE_READY     | 32768           | 9    | DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0                    | CLK_STATE_READY     | 0               | 10    | DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK     | CLK_STATE_READY     | 32000           | 0    | DEV_MCU_TIMER1_TIMER_HCLK_CLK                                                       | CLK_STATE_READY     | 166666666       | 2    | DEV_MCU_TIMER1_TIMER_TCLK_CLK                                                       | CLK_STATE_READY     | 24000000        | 3    | DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT1                          | CLK_STATE_READY     | 24000000        | 4    | DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_0_TIMER_PWM                 | CLK_STATE_READY     | 0               | 0    | DEV_MCU_TIMER2_TIMER_HCLK_CLK                                                       | CLK_STATE_READY     | 166666666       | 1    | DEV_MCU_TIMER2_TIMER_PWM                                                            | CLK_STATE_READY     | 0               | 2    | DEV_MCU_TIMER2_TIMER_TCLK_CLK                                                       | CLK_STATE_READY     | 24000000        | 3    | DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                        | CLK_STATE_READY     | 24000000        | 4    | DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16    | CLK_STATE_READY     | 62500000        | 5    | DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK   | CLK_STATE_READY     | 12500000        | 6    | DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK               | CLK_STATE_READY     | 200000000       | 7    | DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                    | CLK_STATE_READY     | 0               | 8    | DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                        | CLK_STATE_READY     | 32768           | 9    | DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0                    | CLK_STATE_READY     | 0               | 10    | DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK     | CLK_STATE_READY     | 32000           | 0    | DEV_MCU_TIMER3_TIMER_HCLK_CLK                                                       | CLK_STATE_READY     | 166666666       | 2    | DEV_MCU_TIMER3_TIMER_TCLK_CLK                                                       | CLK_STATE_READY     | 24000000        | 3    | DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT3                          | CLK_STATE_READY     | 24000000        | 4    | DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_2_TIMER_PWM                 | CLK_STATE_READY     | 0               | 0    | DEV_MCU_TIMER4_TIMER_HCLK_CLK                                                       | CLK_STATE_READY     | 166666666       | 1    | DEV_MCU_TIMER4_TIMER_PWM                                                            | CLK_STATE_READY     | 0               | 2    | DEV_MCU_TIMER4_TIMER_TCLK_CLK                                                       | CLK_STATE_READY     | 24000000        | 3    | DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                        | CLK_STATE_READY     | 24000000        | 4    | DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16    | CLK_STATE_READY     | 62500000        | 5    | DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK   | CLK_STATE_READY     | 12500000        | 6    | DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK               | CLK_STATE_READY     | 200000000       | 7    | DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                    | CLK_STATE_READY     | 0               | 8    | DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                        | CLK_STATE_READY     | 32768           | 9    | DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0                    | CLK_STATE_READY     | 0               | 10    | DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK     | CLK_STATE_READY     | 32000           | 0    | DEV_MCU_TIMER5_TIMER_HCLK_CLK                                                       | CLK_STATE_READY     | 166666666       | 2    | DEV_MCU_TIMER5_TIMER_TCLK_CLK                                                       | CLK_STATE_READY     | 24000000        | 3    | DEV_MCU_TIMER5_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT5                          | CLK_STATE_READY     | 24000000        | 4    | DEV_MCU_TIMER5_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_4_TIMER_PWM                 | CLK_STATE_READY     | 0               | 0    | DEV_MCU_TIMER6_TIMER_HCLK_CLK                                                       | CLK_STATE_READY     | 166666666       | 1    | DEV_MCU_TIMER6_TIMER_PWM                                                            | CLK_STATE_READY     | 0               | 2    | DEV_MCU_TIMER6_TIMER_TCLK_CLK                                                       | CLK_STATE_READY     | 24000000        | 3    | DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                        | CLK_STATE_READY     | 24000000        | 4    | DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16    | CLK_STATE_READY     | 62500000        | 5    | DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK   | CLK_STATE_READY     | 12500000        | 6    | DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK               | CLK_STATE_READY     | 200000000       | 7    | DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                    | CLK_STATE_READY     | 0               | 8    | DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                        | CLK_STATE_READY     | 32768           | 9    | DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0                    | CLK_STATE_READY     | 0               | 10    | DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK     | CLK_STATE_READY     | 32000           | 0    | DEV_MCU_TIMER7_TIMER_HCLK_CLK                                                       | CLK_STATE_READY     | 166666666       | 2    | DEV_MCU_TIMER7_TIMER_TCLK_CLK                                                       | CLK_STATE_READY     | 24000000        | 3    | DEV_MCU_TIMER7_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT7                          | CLK_STATE_READY     | 24000000        | 4    | DEV_MCU_TIMER7_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_6_TIMER_PWM                 | CLK_STATE_READY     | 0               | 0    | DEV_MCU_TIMER8_TIMER_HCLK_CLK                                                       | CLK_STATE_READY     | 166666666       | 1    | DEV_MCU_TIMER8_TIMER_PWM                                                            | CLK_STATE_READY     | 0               | 2    | DEV_MCU_TIMER8_TIMER_TCLK_CLK                                                       | CLK_STATE_READY     | 24000000        | 3    | DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                        | CLK_STATE_READY     | 24000000        | 4    | DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16    | CLK_STATE_READY     | 62500000        | 5    | DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK   | CLK_STATE_READY     | 12500000        | 6    | DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK               | CLK_STATE_READY     | 200000000       | 7    | DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                    | CLK_STATE_READY     | 0               | 8    | DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                        | CLK_STATE_READY     | 32768           | 9    | DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0                    | CLK_STATE_READY     | 0               | 10    | DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK     | CLK_STATE_READY     | 32000           | 0    | DEV_MCU_TIMER9_TIMER_HCLK_CLK                                                       | CLK_STATE_READY     | 166666666       | 2    | DEV_MCU_TIMER9_TIMER_TCLK_CLK                                                       | CLK_STATE_READY     | 62500000        | 3    | DEV_MCU_TIMER9_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT9                          | CLK_STATE_READY     | 62500000        | 4    | DEV_MCU_TIMER9_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_8_TIMER_PWM                 | CLK_STATE_READY     | 0               | 0    | DEV_MCU_UART0_FCLK_CLK                                                              | CLK_STATE_READY     | 96000000        | 1    | DEV_MCU_UART0_FCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT3_CLK                      | CLK_STATE_READY     | 96000000        | 2    | DEV_MCU_UART0_FCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_1_HSDIVOUT5_CLK                   | CLK_STATE_READY     | 192000000       | 5    | DEV_MCU_UART0_VBUSP_CLK                                                             | CLK_STATE_READY     | 166666666       | 1    | DEV_MMCSD0_EMMCSS_VBUS_CLK                                                          | CLK_STATE_READY     | 250000000       | 2    | DEV_MMCSD0_EMMCSS_XIN_CLK                                                           | CLK_STATE_READY     | 200000000       | 3    | DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK                  | CLK_STATE_READY     | 200000000       | 4    | DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT2_CLK                  | CLK_STATE_READY     | 192000000       | 5    | DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK                  | CLK_STATE_READY     | 200000000       | 6    | DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT2_CLK                  | CLK_STATE_READY     | 192307692       | 0    | DEV_MMCSD1_EMMCSDSS_IO_CLK_I                                                        | CLK_STATE_READY     | 0               | 1    | DEV_MMCSD1_EMMCSDSS_IO_CLK_O                                                        | CLK_STATE_READY     | 0               | 3    | DEV_MMCSD1_EMMCSDSS_VBUS_CLK                                                        | CLK_STATE_READY     | 250000000       | 4    | DEV_MMCSD1_EMMCSDSS_XIN_CLK                                                         | CLK_STATE_READY     | 200000000       | 5    | DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK                | CLK_STATE_READY     | 200000000       | 6    | DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT2_CLK                | CLK_STATE_READY     | 192000000       | 7    | DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK                | CLK_STATE_READY     | 200000000       | 8    | DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT2_CLK                | CLK_STATE_READY     | 192307692       | 0    | DEV_NAVSS0_CPTS0_GENF2                                                              | CLK_STATE_READY     | 0               | 1    | DEV_NAVSS0_CPTS0_GENF3                                                              | CLK_STATE_READY     | 0               | 0    | DEV_NAVSS0_BCDMA_0_CLK                                                              | CLK_STATE_READY     | 500000000       | 0    | DEV_NAVSS0_CPTS_0_RCLK                                                              | CLK_STATE_READY     | 250000000       | 1    | DEV_NAVSS0_CPTS_0_RCLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK                     | CLK_STATE_READY     | 250000000       | 2    | DEV_NAVSS0_CPTS_0_RCLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK                   | CLK_STATE_READY     | 200000000       | 3    | DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT                         | CLK_STATE_READY     | 0               | 4    | DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT                             | CLK_STATE_READY     | 0               | 5    | DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                           | CLK_STATE_READY     | 0               | 6    | DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_EXT_REFCLK1_OUT                               | CLK_STATE_READY     | 0               | 7    | DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN0_TXMCLK                    | CLK_STATE_READY     | 0               | 8    | DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN1_TXMCLK                    | CLK_STATE_READY     | 0               | 9    | DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN2_TXMCLK                    | CLK_STATE_READY     | 0               | 10    | DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN3_TXMCLK                    | CLK_STATE_READY     | 0               | 11    | DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN0_TXMCLK                    | CLK_STATE_READY     | 0               | 12    | DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN1_TXMCLK                    | CLK_STATE_READY     | 0               | 13    | DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP1_LN2_TXMCLK                    | CLK_STATE_READY     | 0               | 14    | DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP3_LN2_TXMCLK                    | CLK_STATE_READY     | 0               | 15    | DEV_NAVSS0_CPTS_0_RCLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK                      | CLK_STATE_READY     | 500000000       | 16    | DEV_NAVSS0_CPTS_0_RCLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK             | CLK_STATE_READY     | 500000000       | 17    | DEV_NAVSS0_CPTS_0_TS_GENF0                                                          | CLK_STATE_READY     | 0               | 18    | DEV_NAVSS0_CPTS_0_TS_GENF1                                                          | CLK_STATE_READY     | 0               | 21    | DEV_NAVSS0_CPTS_0_VBUSP_GCLK                                                        | CLK_STATE_READY     | 500000000       | 0    | DEV_NAVSS0_INTR_0_INTR_CLK                                                          | CLK_STATE_READY     | 500000000       | 0    | DEV_NAVSS0_MAILBOX1_0_VCLK_CLK                                                      | CLK_STATE_READY     | 500000000       | 0    | DEV_NAVSS0_MAILBOX1_1_VCLK_CLK                                                      | CLK_STATE_READY     | 500000000       | 0    | DEV_NAVSS0_MAILBOX1_10_VCLK_CLK                                                     | CLK_STATE_READY     | 500000000       | 0    | DEV_NAVSS0_MAILBOX1_11_VCLK_CLK                                                     | CLK_STATE_READY     | 500000000       | 0    | DEV_NAVSS0_MAILBOX1_2_VCLK_CLK                                                      | CLK_STATE_READY     | 500000000       | 0    | DEV_NAVSS0_MAILBOX1_3_VCLK_CLK                                                      | CLK_STATE_READY     | 500000000       | 0    | DEV_NAVSS0_MAILBOX1_4_VCLK_CLK                                                      | CLK_STATE_READY     | 500000000       | 0    | DEV_NAVSS0_MAILBOX1_5_VCLK_CLK                                                      | CLK_STATE_READY     | 500000000       | 0    | DEV_NAVSS0_MAILBOX1_6_VCLK_CLK                                                      | CLK_STATE_READY     | 500000000       | 0    | DEV_NAVSS0_MAILBOX1_7_VCLK_CLK                                                      | CLK_STATE_READY     | 500000000       | 0    | DEV_NAVSS0_MAILBOX1_8_VCLK_CLK                                                      | CLK_STATE_READY     | 500000000       | 0    | DEV_NAVSS0_MAILBOX1_9_VCLK_CLK                                                      | CLK_STATE_READY     | 500000000       | 0    | DEV_NAVSS0_MAILBOX_0_VCLK_CLK                                                       | CLK_STATE_READY     | 500000000       | 0    | DEV_NAVSS0_MAILBOX_1_VCLK_CLK                                                       | CLK_STATE_READY     | 500000000       | 0    | DEV_NAVSS0_MAILBOX_10_VCLK_CLK                                                      | CLK_STATE_READY     | 500000000       | 0    | DEV_NAVSS0_MAILBOX_11_VCLK_CLK                                                      | CLK_STATE_READY     | 500000000       | 0    | DEV_NAVSS0_MAILBOX_2_VCLK_CLK                                                       | CLK_STATE_READY     | 500000000       | 0    | DEV_NAVSS0_MAILBOX_3_VCLK_CLK                                                       | CLK_STATE_READY     | 500000000       | 0    | DEV_NAVSS0_MAILBOX_4_VCLK_CLK                                                       | CLK_STATE_READY     | 500000000       | 0    | DEV_NAVSS0_MAILBOX_5_VCLK_CLK                                                       | CLK_STATE_READY     | 500000000       | 0    | DEV_NAVSS0_MAILBOX_6_VCLK_CLK                                                       | CLK_STATE_READY     | 500000000       | 0    | DEV_NAVSS0_MAILBOX_7_VCLK_CLK                                                       | CLK_STATE_READY     | 500000000       | 0    | DEV_NAVSS0_MAILBOX_8_VCLK_CLK                                                       | CLK_STATE_READY     | 500000000       | 0    | DEV_NAVSS0_MAILBOX_9_VCLK_CLK                                                       | CLK_STATE_READY     | 500000000       | 0    | DEV_NAVSS0_MCRC_0_CLK                                                               | CLK_STATE_READY     | 500000000       | 0    | DEV_NAVSS0_MODSS_VD2CLK                                                             | CLK_STATE_READY     | 500000000       | 0    | DEV_NAVSS0_MODSS_INTA_0_SYS_CLK                                                     | CLK_STATE_READY     | 500000000       | 0    | DEV_NAVSS0_MODSS_INTA_1_SYS_CLK                                                     | CLK_STATE_READY     | 500000000       | 0    | DEV_NAVSS0_PROXY_0_CLK_CLK                                                          | CLK_STATE_READY     | 500000000       | 0    | DEV_NAVSS0_PVU_0_CLK_CLK                                                            | CLK_STATE_READY     | 500000000       | 0    | DEV_NAVSS0_PVU_1_CLK_CLK                                                            | CLK_STATE_READY     | 500000000       | 0    | DEV_NAVSS0_RINGACC_0_SYS_CLK                                                        | CLK_STATE_READY     | 500000000       | 0    | DEV_NAVSS0_SPINLOCK_0_CLK                                                           | CLK_STATE_READY     | 500000000       | 0    | DEV_NAVSS0_TIMERMGR_0_EON_TICK_EVT                                                  | CLK_STATE_READY     | 0               | 1    | DEV_NAVSS0_TIMERMGR_0_VCLK_CLK                                                      | CLK_STATE_READY     | 500000000       | 0    | DEV_NAVSS0_TIMERMGR_1_EON_TICK_EVT                                                  | CLK_STATE_READY     | 0               | 1    | DEV_NAVSS0_TIMERMGR_1_VCLK_CLK                                                      | CLK_STATE_READY     | 500000000       | 0    | DEV_NAVSS0_UDMAP_0_SYS_CLK                                                          | CLK_STATE_READY     | 500000000       | 0    | DEV_NAVSS0_UDMASS_VD2CLK                                                            | CLK_STATE_READY     | 500000000       | 0    | DEV_NAVSS0_UDMASS_INTA_0_SYS_CLK                                                    | CLK_STATE_READY     | 500000000       | 0    | DEV_NAVSS0_VIRTSS_VD2CLK                                                            | CLK_STATE_READY     | 500000000       | 7    | DEV_PBIST0_CLK8_CLK                                                                 | CLK_STATE_READY     | 125000000       | 7    | DEV_PBIST1_CLK8_CLK                                                                 | CLK_STATE_READY     | 125000000       | 7    | DEV_PBIST10_CLK8_CLK                                                                | CLK_STATE_READY     | 125000000       | 6    | DEV_PBIST11_CLK7_CLK                                                                | CLK_STATE_READY     | 125000000       | 7    | DEV_PBIST14_CLK8_CLK                                                                | CLK_STATE_READY     | 125000000       | 7    | DEV_PBIST2_CLK8_CLK                                                                 | CLK_STATE_READY     | 125000000       | 7    | DEV_PBIST3_CLK8_CLK                                                                 | CLK_STATE_READY     | 125000000       | 7    | DEV_PBIST4_CLK8_CLK                                                                 | CLK_STATE_READY     | 125000000       | 7    | DEV_PBIST5_CLK8_CLK                                                                 | CLK_STATE_READY     | 125000000       | 0    | DEV_PCIE0_PCIE_CBA_CLK                                                              | CLK_STATE_READY     | 250000000       | 2    | DEV_PCIE0_PCIE_CPTS_RCLK_CLK                                                        | CLK_STATE_READY     | 250000000       | 3    | DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK               | CLK_STATE_READY     | 250000000       | 4    | DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK             | CLK_STATE_READY     | 200000000       | 5    | DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT                   | CLK_STATE_READY     | 0               | 6    | DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT                       | CLK_STATE_READY     | 0               | 7    | DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                     | CLK_STATE_READY     | 0               | 8    | DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT                         | CLK_STATE_READY     | 0               | 9    | DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN0_TXMCLK              | CLK_STATE_READY     | 0               | 10    | DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN1_TXMCLK              | CLK_STATE_READY     | 0               | 11    | DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN2_TXMCLK              | CLK_STATE_READY     | 0               | 12    | DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN3_TXMCLK              | CLK_STATE_READY     | 0               | 13    | DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN0_TXMCLK              | CLK_STATE_READY     | 0               | 14    | DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN1_TXMCLK              | CLK_STATE_READY     | 0               | 15    | DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP1_LN2_TXMCLK              | CLK_STATE_READY     | 0               | 16    | DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP3_LN2_TXMCLK              | CLK_STATE_READY     | 0               | 17    | DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK                | CLK_STATE_READY     | 500000000       | 18    | DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK       | CLK_STATE_READY     | 500000000       | 19    | DEV_PCIE0_PCIE_LANE0_REFCLK                                                         | CLK_STATE_READY     | 0               | 20    | DEV_PCIE0_PCIE_LANE0_RXCLK                                                          | CLK_STATE_READY     | 0               | 21    | DEV_PCIE0_PCIE_LANE0_RXFCLK                                                         | CLK_STATE_READY     | 0               | 22    | DEV_PCIE0_PCIE_LANE0_TXCLK                                                          | CLK_STATE_READY     | 0               | 23    | DEV_PCIE0_PCIE_LANE0_TXFCLK                                                         | CLK_STATE_READY     | 0               | 24    | DEV_PCIE0_PCIE_LANE0_TXMCLK                                                         | CLK_STATE_READY     | 0               | 25    | DEV_PCIE0_PCIE_LANE1_REFCLK                                                         | CLK_STATE_READY     | 0               | 26    | DEV_PCIE0_PCIE_LANE1_RXCLK                                                          | CLK_STATE_READY     | 0               | 27    | DEV_PCIE0_PCIE_LANE1_RXFCLK                                                         | CLK_STATE_READY     | 0               | 28    | DEV_PCIE0_PCIE_LANE1_TXCLK                                                          | CLK_STATE_READY     | 0               | 29    | DEV_PCIE0_PCIE_LANE1_TXFCLK                                                         | CLK_STATE_READY     | 0               | 30    | DEV_PCIE0_PCIE_LANE1_TXMCLK                                                         | CLK_STATE_READY     | 0               | 31    | DEV_PCIE0_PCIE_LANE2_REFCLK                                                         | CLK_STATE_READY     | 0               | 32    | DEV_PCIE0_PCIE_LANE2_RXCLK                                                          | CLK_STATE_READY     | 0               | 33    | DEV_PCIE0_PCIE_LANE2_RXFCLK                                                         | CLK_STATE_READY     | 0               | 34    | DEV_PCIE0_PCIE_LANE2_TXCLK                                                          | CLK_STATE_READY     | 0               | 35    | DEV_PCIE0_PCIE_LANE2_TXFCLK                                                         | CLK_STATE_READY     | 0               | 36    | DEV_PCIE0_PCIE_LANE2_TXMCLK                                                         | CLK_STATE_READY     | 0               | 37    | DEV_PCIE0_PCIE_LANE3_REFCLK                                                         | CLK_STATE_READY     | 0               | 38    | DEV_PCIE0_PCIE_LANE3_RXCLK                                                          | CLK_STATE_READY     | 0               | 39    | DEV_PCIE0_PCIE_LANE3_RXFCLK                                                         | CLK_STATE_READY     | 0               | 40    | DEV_PCIE0_PCIE_LANE3_TXCLK                                                          | CLK_STATE_READY     | 0               | 41    | DEV_PCIE0_PCIE_LANE3_TXFCLK                                                         | CLK_STATE_READY     | 0               | 42    | DEV_PCIE0_PCIE_LANE3_TXMCLK                                                         | CLK_STATE_READY     | 0               | 43    | DEV_PCIE0_PCIE_PM_CLK                                                               | CLK_STATE_READY     | 12500000        | 0    | DEV_PCIE1_PCIE_CBA_CLK                                                              | CLK_STATE_READY     | 250000000       | 2    | DEV_PCIE1_PCIE_CPTS_RCLK_CLK                                                        | CLK_STATE_READY     | 250000000       | 3    | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK               | CLK_STATE_READY     | 250000000       | 4    | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK             | CLK_STATE_READY     | 200000000       | 5    | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT                   | CLK_STATE_READY     | 0               | 6    | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT                       | CLK_STATE_READY     | 0               | 7    | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                     | CLK_STATE_READY     | 0               | 8    | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT                         | CLK_STATE_READY     | 0               | 9    | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN0_TXMCLK              | CLK_STATE_READY     | 0               | 10    | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN1_TXMCLK              | CLK_STATE_READY     | 0               | 11    | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN2_TXMCLK              | CLK_STATE_READY     | 0               | 12    | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN3_TXMCLK              | CLK_STATE_READY     | 0               | 13    | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN0_TXMCLK              | CLK_STATE_READY     | 0               | 14    | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN1_TXMCLK              | CLK_STATE_READY     | 0               | 15    | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP1_LN2_TXMCLK              | CLK_STATE_READY     | 0               | 16    | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP3_LN2_TXMCLK              | CLK_STATE_READY     | 0               | 17    | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK                | CLK_STATE_READY     | 500000000       | 18    | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK       | CLK_STATE_READY     | 500000000       | 19    | DEV_PCIE1_PCIE_LANE0_REFCLK                                                         | CLK_STATE_READY     | 0               | 20    | DEV_PCIE1_PCIE_LANE0_RXCLK                                                          | CLK_STATE_READY     | 0               | 21    | DEV_PCIE1_PCIE_LANE0_RXFCLK                                                         | CLK_STATE_READY     | 0               | 22    | DEV_PCIE1_PCIE_LANE0_TXCLK                                                          | CLK_STATE_READY     | 0               | 23    | DEV_PCIE1_PCIE_LANE0_TXFCLK                                                         | CLK_STATE_READY     | 0               | 24    | DEV_PCIE1_PCIE_LANE0_TXMCLK                                                         | CLK_STATE_READY     | 0               | 25    | DEV_PCIE1_PCIE_LANE1_REFCLK                                                         | CLK_STATE_READY     | 0               | 26    | DEV_PCIE1_PCIE_LANE1_RXCLK                                                          | CLK_STATE_READY     | 0               | 27    | DEV_PCIE1_PCIE_LANE1_RXFCLK                                                         | CLK_STATE_READY     | 0               | 28    | DEV_PCIE1_PCIE_LANE1_TXCLK                                                          | CLK_STATE_READY     | 0               | 29    | DEV_PCIE1_PCIE_LANE1_TXFCLK                                                         | CLK_STATE_READY     | 0               | 30    | DEV_PCIE1_PCIE_LANE1_TXMCLK                                                         | CLK_STATE_READY     | 0               | 31    | DEV_PCIE1_PCIE_LANE2_REFCLK                                                         | CLK_STATE_READY     | 0               | 32    | DEV_PCIE1_PCIE_LANE2_RXCLK                                                          | CLK_STATE_READY     | 0               | 33    | DEV_PCIE1_PCIE_LANE2_RXFCLK                                                         | CLK_STATE_READY     | 0               | 34    | DEV_PCIE1_PCIE_LANE2_TXCLK                                                          | CLK_STATE_READY     | 0               | 35    | DEV_PCIE1_PCIE_LANE2_TXFCLK                                                         | CLK_STATE_READY     | 0               | 36    | DEV_PCIE1_PCIE_LANE2_TXMCLK                                                         | CLK_STATE_READY     | 0               | 37    | DEV_PCIE1_PCIE_LANE3_REFCLK                                                         | CLK_STATE_READY     | 0               | 38    | DEV_PCIE1_PCIE_LANE3_RXCLK                                                          | CLK_STATE_READY     | 0               | 39    | DEV_PCIE1_PCIE_LANE3_RXFCLK                                                         | CLK_STATE_READY     | 0               | 40    | DEV_PCIE1_PCIE_LANE3_TXCLK                                                          | CLK_STATE_READY     | 0               | 41    | DEV_PCIE1_PCIE_LANE3_TXFCLK                                                         | CLK_STATE_READY     | 0               | 42    | DEV_PCIE1_PCIE_LANE3_TXMCLK                                                         | CLK_STATE_READY     | 0               | 43    | DEV_PCIE1_PCIE_PM_CLK                                                               | CLK_STATE_READY     | 12500000        | 0    | DEV_PCIE2_PCIE_CBA_CLK                                                              | CLK_STATE_READY     | 250000000       | 2    | DEV_PCIE2_PCIE_CPTS_RCLK_CLK                                                        | CLK_STATE_READY     | 250000000       | 3    | DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK               | CLK_STATE_READY     | 250000000       | 4    | DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK             | CLK_STATE_READY     | 200000000       | 5    | DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT                   | CLK_STATE_READY     | 0               | 6    | DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT                       | CLK_STATE_READY     | 0               | 7    | DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                     | CLK_STATE_READY     | 0               | 8    | DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT                         | CLK_STATE_READY     | 0               | 9    | DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN0_TXMCLK              | CLK_STATE_READY     | 0               | 10    | DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN1_TXMCLK              | CLK_STATE_READY     | 0               | 11    | DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN2_TXMCLK              | CLK_STATE_READY     | 0               | 12    | DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN3_TXMCLK              | CLK_STATE_READY     | 0               | 13    | DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN0_TXMCLK              | CLK_STATE_READY     | 0               | 14    | DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN1_TXMCLK              | CLK_STATE_READY     | 0               | 15    | DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP1_LN2_TXMCLK              | CLK_STATE_READY     | 0               | 16    | DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP3_LN2_TXMCLK              | CLK_STATE_READY     | 0               | 17    | DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK                | CLK_STATE_READY     | 500000000       | 18    | DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK       | CLK_STATE_READY     | 500000000       | 19    | DEV_PCIE2_PCIE_LANE0_REFCLK                                                         | CLK_STATE_READY     | 0               | 20    | DEV_PCIE2_PCIE_LANE0_RXCLK                                                          | CLK_STATE_READY     | 0               | 21    | DEV_PCIE2_PCIE_LANE0_RXFCLK                                                         | CLK_STATE_READY     | 0               | 22    | DEV_PCIE2_PCIE_LANE0_TXCLK                                                          | CLK_STATE_READY     | 0               | 23    | DEV_PCIE2_PCIE_LANE0_TXFCLK                                                         | CLK_STATE_READY     | 0               | 24    | DEV_PCIE2_PCIE_LANE0_TXMCLK                                                         | CLK_STATE_READY     | 0               | 25    | DEV_PCIE2_PCIE_LANE1_REFCLK                                                         | CLK_STATE_READY     | 0               | 26    | DEV_PCIE2_PCIE_LANE1_RXCLK                                                          | CLK_STATE_READY     | 0               | 27    | DEV_PCIE2_PCIE_LANE1_RXFCLK                                                         | CLK_STATE_READY     | 0               | 28    | DEV_PCIE2_PCIE_LANE1_TXCLK                                                          | CLK_STATE_READY     | 0               | 29    | DEV_PCIE2_PCIE_LANE1_TXFCLK                                                         | CLK_STATE_READY     | 0               | 30    | DEV_PCIE2_PCIE_LANE1_TXMCLK                                                         | CLK_STATE_READY     | 0               | 43    | DEV_PCIE2_PCIE_PM_CLK                                                               | CLK_STATE_READY     | 12500000        | 0    | DEV_PCIE3_PCIE_CBA_CLK                                                              | CLK_STATE_READY     | 250000000       | 2    | DEV_PCIE3_PCIE_CPTS_RCLK_CLK                                                        | CLK_STATE_READY     | 250000000       | 3    | DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK               | CLK_STATE_READY     | 250000000       | 4    | DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK             | CLK_STATE_READY     | 200000000       | 5    | DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT                   | CLK_STATE_READY     | 0               | 6    | DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT                       | CLK_STATE_READY     | 0               | 7    | DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                     | CLK_STATE_READY     | 0               | 8    | DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT                         | CLK_STATE_READY     | 0               | 9    | DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN0_TXMCLK              | CLK_STATE_READY     | 0               | 10    | DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN1_TXMCLK              | CLK_STATE_READY     | 0               | 11    | DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN2_TXMCLK              | CLK_STATE_READY     | 0               | 12    | DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN3_TXMCLK              | CLK_STATE_READY     | 0               | 13    | DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN0_TXMCLK              | CLK_STATE_READY     | 0               | 14    | DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN1_TXMCLK              | CLK_STATE_READY     | 0               | 15    | DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP1_LN2_TXMCLK              | CLK_STATE_READY     | 0               | 16    | DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP3_LN2_TXMCLK              | CLK_STATE_READY     | 0               | 17    | DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK                | CLK_STATE_READY     | 500000000       | 18    | DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK       | CLK_STATE_READY     | 500000000       | 19    | DEV_PCIE3_PCIE_LANE0_REFCLK                                                         | CLK_STATE_READY     | 0               | 20    | DEV_PCIE3_PCIE_LANE0_RXCLK                                                          | CLK_STATE_READY     | 0               | 21    | DEV_PCIE3_PCIE_LANE0_RXFCLK                                                         | CLK_STATE_READY     | 0               | 22    | DEV_PCIE3_PCIE_LANE0_TXCLK                                                          | CLK_STATE_READY     | 0               | 23    | DEV_PCIE3_PCIE_LANE0_TXFCLK                                                         | CLK_STATE_READY     | 0               | 24    | DEV_PCIE3_PCIE_LANE0_TXMCLK                                                         | CLK_STATE_READY     | 0               | 25    | DEV_PCIE3_PCIE_LANE1_REFCLK                                                         | CLK_STATE_READY     | 0               | 26    | DEV_PCIE3_PCIE_LANE1_RXCLK                                                          | CLK_STATE_READY     | 0               | 27    | DEV_PCIE3_PCIE_LANE1_RXFCLK                                                         | CLK_STATE_READY     | 0               | 28    | DEV_PCIE3_PCIE_LANE1_TXCLK                                                          | CLK_STATE_READY     | 0               | 29    | DEV_PCIE3_PCIE_LANE1_TXFCLK                                                         | CLK_STATE_READY     | 0               | 30    | DEV_PCIE3_PCIE_LANE1_TXMCLK                                                         | CLK_STATE_READY     | 0               | 43    | DEV_PCIE3_PCIE_PM_CLK                                                               | CLK_STATE_READY     | 12500000        | 0    | DEV_PSC0_CLK                                                                        | CLK_STATE_READY     | 125000000       | 1    | DEV_PSC0_SLOW_CLK                                                                   | CLK_STATE_READY     | 20833333        | 0    | DEV_R5FSS0_CORE0_CPU_CLK                                                            | CLK_STATE_READY     | 1000000000      | 1    | DEV_R5FSS0_CORE0_INTERFACE_CLK                                                      | CLK_STATE_READY     | 1000000000      | 0    | DEV_R5FSS0_CORE1_CPU_CLK                                                            | CLK_STATE_READY     | 1000000000      | 1    | DEV_R5FSS0_CORE1_INTERFACE_CLK                                                      | CLK_STATE_READY     | 1000000000      | 0    | DEV_R5FSS1_CORE0_CPU_CLK                                                            | CLK_STATE_READY     | 1000000000      | 1    | DEV_R5FSS1_CORE0_INTERFACE_CLK                                                      | CLK_STATE_READY     | 1000000000      | 0    | DEV_R5FSS1_CORE1_CPU_CLK                                                            | CLK_STATE_READY     | 1000000000      | 1    | DEV_R5FSS1_CORE1_INTERFACE_CLK                                                      | CLK_STATE_READY     | 1000000000      | 0    | DEV_R5FSS2_CORE0_CPU_CLK                                                            | CLK_STATE_READY     | 1000000000      | 1    | DEV_R5FSS2_CORE0_INTERFACE_CLK                                                      | CLK_STATE_READY     | 1000000000      | 0    | DEV_R5FSS2_CORE1_CPU_CLK                                                            | CLK_STATE_READY     | 1000000000      | 1    | DEV_R5FSS2_CORE1_INTERFACE_CLK                                                      | CLK_STATE_READY     | 1000000000      | 0    | DEV_RTI0_RTI_CLK                                                                    | CLK_STATE_READY     | 32000           | 1    | DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                                     | CLK_STATE_READY     | 24000000        | 2    | DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                                     | CLK_STATE_READY     | 32768           | 3    | DEV_RTI0_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK                | CLK_STATE_READY     | 12500000        | 4    | DEV_RTI0_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK                  | CLK_STATE_READY     | 32000           | 5    | DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                                      | CLK_STATE_READY     | 0               | 6    | DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0                                 | CLK_STATE_READY     | 0               | 7    | DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1                                 | CLK_STATE_READY     | 0               | 8    | DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2                                 | CLK_STATE_READY     | 0               | 9    | DEV_RTI0_VBUSP_CLK                                                                  | CLK_STATE_READY     | 125000000       | 0    | DEV_RTI1_RTI_CLK                                                                    | CLK_STATE_READY     | 32000           | 1    | DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                                     | CLK_STATE_READY     | 24000000        | 2    | DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                                     | CLK_STATE_READY     | 32768           | 3    | DEV_RTI1_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK                | CLK_STATE_READY     | 12500000        | 4    | DEV_RTI1_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK                  | CLK_STATE_READY     | 32000           | 5    | DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                                      | CLK_STATE_READY     | 0               | 6    | DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0                                 | CLK_STATE_READY     | 0               | 7    | DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1                                 | CLK_STATE_READY     | 0               | 8    | DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2                                 | CLK_STATE_READY     | 0               | 9    | DEV_RTI1_VBUSP_CLK                                                                  | CLK_STATE_READY     | 125000000       | 0    | DEV_RTI15_RTI_CLK                                                                   | CLK_STATE_READY     | 24000000        | 1    | DEV_RTI15_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                                    | CLK_STATE_READY     | 24000000        | 2    | DEV_RTI15_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                                    | CLK_STATE_READY     | 32768           | 3    | DEV_RTI15_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK               | CLK_STATE_READY     | 12500000        | 4    | DEV_RTI15_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK                 | CLK_STATE_READY     | 32000           | 5    | DEV_RTI15_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                                     | CLK_STATE_READY     | 0               | 6    | DEV_RTI15_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0                                | CLK_STATE_READY     | 0               | 7    | DEV_RTI15_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1                                | CLK_STATE_READY     | 0               | 8    | DEV_RTI15_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2                                | CLK_STATE_READY     | 0               | 9    | DEV_RTI15_VBUSP_CLK                                                                 | CLK_STATE_READY     | 125000000       | 0    | DEV_RTI16_RTI_CLK                                                                   | CLK_STATE_READY     | 24000000        | 1    | DEV_RTI16_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                                    | CLK_STATE_READY     | 24000000        | 2    | DEV_RTI16_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                                    | CLK_STATE_READY     | 32768           | 3    | DEV_RTI16_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK               | CLK_STATE_READY     | 12500000        | 4    | DEV_RTI16_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK                 | CLK_STATE_READY     | 32000           | 5    | DEV_RTI16_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                                     | CLK_STATE_READY     | 0               | 6    | DEV_RTI16_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0                                | CLK_STATE_READY     | 0               | 7    | DEV_RTI16_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1                                | CLK_STATE_READY     | 0               | 8    | DEV_RTI16_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2                                | CLK_STATE_READY     | 0               | 9    | DEV_RTI16_VBUSP_CLK                                                                 | CLK_STATE_READY     | 125000000       | 0    | DEV_RTI17_RTI_CLK                                                                   | CLK_STATE_READY     | 24000000        | 1    | DEV_RTI17_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                                    | CLK_STATE_READY     | 24000000        | 2    | DEV_RTI17_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                                    | CLK_STATE_READY     | 32768           | 3    | DEV_RTI17_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK               | CLK_STATE_READY     | 12500000        | 4    | DEV_RTI17_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK                 | CLK_STATE_READY     | 32000           | 5    | DEV_RTI17_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                                     | CLK_STATE_READY     | 0               | 6    | DEV_RTI17_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0                                | CLK_STATE_READY     | 0               | 7    | DEV_RTI17_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1                                | CLK_STATE_READY     | 0               | 8    | DEV_RTI17_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2                                | CLK_STATE_READY     | 0               | 9    | DEV_RTI17_VBUSP_CLK                                                                 | CLK_STATE_READY     | 125000000       | 0    | DEV_RTI18_RTI_CLK                                                                   | CLK_STATE_READY     | 24000000        | 1    | DEV_RTI18_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                                    | CLK_STATE_READY     | 24000000        | 2    | DEV_RTI18_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                                    | CLK_STATE_READY     | 32768           | 3    | DEV_RTI18_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK               | CLK_STATE_READY     | 12500000        | 4    | DEV_RTI18_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK                 | CLK_STATE_READY     | 32000           | 5    | DEV_RTI18_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                                     | CLK_STATE_READY     | 0               | 6    | DEV_RTI18_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0                                | CLK_STATE_READY     | 0               | 7    | DEV_RTI18_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1                                | CLK_STATE_READY     | 0               | 8    | DEV_RTI18_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2                                | CLK_STATE_READY     | 0               | 9    | DEV_RTI18_VBUSP_CLK                                                                 | CLK_STATE_READY     | 125000000       | 0    | DEV_RTI19_RTI_CLK                                                                   | CLK_STATE_READY     | 24000000        | 1    | DEV_RTI19_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                                    | CLK_STATE_READY     | 24000000        | 2    | DEV_RTI19_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                                    | CLK_STATE_READY     | 32768           | 3    | DEV_RTI19_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK               | CLK_STATE_READY     | 12500000        | 4    | DEV_RTI19_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK                 | CLK_STATE_READY     | 32000           | 5    | DEV_RTI19_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                                     | CLK_STATE_READY     | 0               | 6    | DEV_RTI19_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0                                | CLK_STATE_READY     | 0               | 7    | DEV_RTI19_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1                                | CLK_STATE_READY     | 0               | 8    | DEV_RTI19_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2                                | CLK_STATE_READY     | 0               | 9    | DEV_RTI19_VBUSP_CLK                                                                 | CLK_STATE_READY     | 125000000       | 0    | DEV_RTI2_RTI_CLK                                                                    | CLK_STATE_READY     | 32000           | 1    | DEV_RTI2_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                                     | CLK_STATE_READY     | 24000000        | 2    | DEV_RTI2_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                                     | CLK_STATE_READY     | 32768           | 3    | DEV_RTI2_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK                | CLK_STATE_READY     | 12500000        | 4    | DEV_RTI2_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK                  | CLK_STATE_READY     | 32000           | 5    | DEV_RTI2_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                                      | CLK_STATE_READY     | 0               | 6    | DEV_RTI2_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0                                 | CLK_STATE_READY     | 0               | 7    | DEV_RTI2_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1                                 | CLK_STATE_READY     | 0               | 8    | DEV_RTI2_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2                                 | CLK_STATE_READY     | 0               | 9    | DEV_RTI2_VBUSP_CLK                                                                  | CLK_STATE_READY     | 125000000       | 0    | DEV_RTI28_RTI_CLK                                                                   | CLK_STATE_READY     | 24000000        | 1    | DEV_RTI28_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                                    | CLK_STATE_READY     | 24000000        | 2    | DEV_RTI28_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                                    | CLK_STATE_READY     | 32768           | 3    | DEV_RTI28_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK               | CLK_STATE_READY     | 12500000        | 4    | DEV_RTI28_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK                 | CLK_STATE_READY     | 32000           | 5    | DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                                     | CLK_STATE_READY     | 0               | 6    | DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0                                | CLK_STATE_READY     | 0               | 7    | DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1                                | CLK_STATE_READY     | 0               | 8    | DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2                                | CLK_STATE_READY     | 0               | 9    | DEV_RTI28_VBUSP_CLK                                                                 | CLK_STATE_READY     | 125000000       | 0    | DEV_RTI29_RTI_CLK                                                                   | CLK_STATE_READY     | 24000000        | 1    | DEV_RTI29_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                                    | CLK_STATE_READY     | 24000000        | 2    | DEV_RTI29_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                                    | CLK_STATE_READY     | 32768           | 3    | DEV_RTI29_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK               | CLK_STATE_READY     | 12500000        | 4    | DEV_RTI29_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK                 | CLK_STATE_READY     | 32000           | 5    | DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                                     | CLK_STATE_READY     | 0               | 6    | DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0                                | CLK_STATE_READY     | 0               | 7    | DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1                                | CLK_STATE_READY     | 0               | 8    | DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2                                | CLK_STATE_READY     | 0               | 9    | DEV_RTI29_VBUSP_CLK                                                                 | CLK_STATE_READY     | 125000000       | 0    | DEV_RTI3_RTI_CLK                                                                    | CLK_STATE_READY     | 32000           | 1    | DEV_RTI3_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                                     | CLK_STATE_READY     | 24000000        | 2    | DEV_RTI3_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                                     | CLK_STATE_READY     | 32768           | 3    | DEV_RTI3_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK                | CLK_STATE_READY     | 12500000        | 4    | DEV_RTI3_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK                  | CLK_STATE_READY     | 32000           | 5    | DEV_RTI3_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                                      | CLK_STATE_READY     | 0               | 6    | DEV_RTI3_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0                                 | CLK_STATE_READY     | 0               | 7    | DEV_RTI3_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1                                 | CLK_STATE_READY     | 0               | 8    | DEV_RTI3_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2                                 | CLK_STATE_READY     | 0               | 9    | DEV_RTI3_VBUSP_CLK                                                                  | CLK_STATE_READY     | 125000000       | 0    | DEV_RTI30_RTI_CLK                                                                   | CLK_STATE_READY     | 24000000        | 1    | DEV_RTI30_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                                    | CLK_STATE_READY     | 24000000        | 2    | DEV_RTI30_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                                    | CLK_STATE_READY     | 32768           | 3    | DEV_RTI30_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK               | CLK_STATE_READY     | 12500000        | 4    | DEV_RTI30_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK                 | CLK_STATE_READY     | 32000           | 5    | DEV_RTI30_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                                     | CLK_STATE_READY     | 0               | 6    | DEV_RTI30_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0                                | CLK_STATE_READY     | 0               | 7    | DEV_RTI30_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1                                | CLK_STATE_READY     | 0               | 8    | DEV_RTI30_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2                                | CLK_STATE_READY     | 0               | 9    | DEV_RTI30_VBUSP_CLK                                                                 | CLK_STATE_READY     | 125000000       | 0    | DEV_RTI31_RTI_CLK                                                                   | CLK_STATE_READY     | 24000000        | 1    | DEV_RTI31_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                                    | CLK_STATE_READY     | 24000000        | 2    | DEV_RTI31_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                                    | CLK_STATE_READY     | 32768           | 3    | DEV_RTI31_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK               | CLK_STATE_READY     | 12500000        | 4    | DEV_RTI31_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK                 | CLK_STATE_READY     | 32000           | 5    | DEV_RTI31_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                                     | CLK_STATE_READY     | 0               | 6    | DEV_RTI31_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0                                | CLK_STATE_READY     | 0               | 7    | DEV_RTI31_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1                                | CLK_STATE_READY     | 0               | 8    | DEV_RTI31_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2                                | CLK_STATE_READY     | 0               | 9    | DEV_RTI31_VBUSP_CLK                                                                 | CLK_STATE_READY     | 125000000       | 0    | DEV_RTI32_RTI_CLK                                                                   | CLK_STATE_READY     | 24000000        | 1    | DEV_RTI32_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                                    | CLK_STATE_READY     | 24000000        | 2    | DEV_RTI32_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                                    | CLK_STATE_READY     | 32768           | 3    | DEV_RTI32_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK               | CLK_STATE_READY     | 12500000        | 4    | DEV_RTI32_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK                 | CLK_STATE_READY     | 32000           | 5    | DEV_RTI32_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                                     | CLK_STATE_READY     | 0               | 6    | DEV_RTI32_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0                                | CLK_STATE_READY     | 0               | 7    | DEV_RTI32_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1                                | CLK_STATE_READY     | 0               | 8    | DEV_RTI32_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2                                | CLK_STATE_READY     | 0               | 9    | DEV_RTI32_VBUSP_CLK                                                                 | CLK_STATE_READY     | 125000000       | 0    | DEV_RTI33_RTI_CLK                                                                   | CLK_STATE_READY     | 24000000        | 1    | DEV_RTI33_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                                    | CLK_STATE_READY     | 24000000        | 2    | DEV_RTI33_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                                    | CLK_STATE_READY     | 32768           | 3    | DEV_RTI33_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK               | CLK_STATE_READY     | 12500000        | 4    | DEV_RTI33_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK                 | CLK_STATE_READY     | 32000           | 5    | DEV_RTI33_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                                     | CLK_STATE_READY     | 0               | 6    | DEV_RTI33_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0                                | CLK_STATE_READY     | 0               | 7    | DEV_RTI33_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1                                | CLK_STATE_READY     | 0               | 8    | DEV_RTI33_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2                                | CLK_STATE_READY     | 0               | 9    | DEV_RTI33_VBUSP_CLK                                                                 | CLK_STATE_READY     | 125000000       | 0    | DEV_RTI4_RTI_CLK                                                                    | CLK_STATE_READY     | 32000           | 1    | DEV_RTI4_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                                     | CLK_STATE_READY     | 24000000        | 2    | DEV_RTI4_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                                     | CLK_STATE_READY     | 32768           | 3    | DEV_RTI4_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK                | CLK_STATE_READY     | 12500000        | 4    | DEV_RTI4_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK                  | CLK_STATE_READY     | 32000           | 5    | DEV_RTI4_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                                      | CLK_STATE_READY     | 0               | 6    | DEV_RTI4_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0                                 | CLK_STATE_READY     | 0               | 7    | DEV_RTI4_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1                                 | CLK_STATE_READY     | 0               | 8    | DEV_RTI4_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2                                 | CLK_STATE_READY     | 0               | 9    | DEV_RTI4_VBUSP_CLK                                                                  | CLK_STATE_READY     | 125000000       | 0    | DEV_RTI5_RTI_CLK                                                                    | CLK_STATE_READY     | 32000           | 1    | DEV_RTI5_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                                     | CLK_STATE_READY     | 24000000        | 2    | DEV_RTI5_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                                     | CLK_STATE_READY     | 32768           | 3    | DEV_RTI5_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK                | CLK_STATE_READY     | 12500000        | 4    | DEV_RTI5_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK                  | CLK_STATE_READY     | 32000           | 5    | DEV_RTI5_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                                      | CLK_STATE_READY     | 0               | 6    | DEV_RTI5_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0                                 | CLK_STATE_READY     | 0               | 7    | DEV_RTI5_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1                                 | CLK_STATE_READY     | 0               | 8    | DEV_RTI5_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2                                 | CLK_STATE_READY     | 0               | 9    | DEV_RTI5_VBUSP_CLK                                                                  | CLK_STATE_READY     | 125000000       | 0    | DEV_RTI6_RTI_CLK                                                                    | CLK_STATE_READY     | 32000           | 1    | DEV_RTI6_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                                     | CLK_STATE_READY     | 24000000        | 2    | DEV_RTI6_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                                     | CLK_STATE_READY     | 32768           | 3    | DEV_RTI6_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK                | CLK_STATE_READY     | 12500000        | 4    | DEV_RTI6_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK                  | CLK_STATE_READY     | 32000           | 5    | DEV_RTI6_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                                      | CLK_STATE_READY     | 0               | 6    | DEV_RTI6_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0                                 | CLK_STATE_READY     | 0               | 7    | DEV_RTI6_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1                                 | CLK_STATE_READY     | 0               | 8    | DEV_RTI6_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2                                 | CLK_STATE_READY     | 0               | 9    | DEV_RTI6_VBUSP_CLK                                                                  | CLK_STATE_READY     | 125000000       | 0    | DEV_RTI7_RTI_CLK                                                                    | CLK_STATE_READY     | 32000           | 1    | DEV_RTI7_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                                     | CLK_STATE_READY     | 24000000        | 2    | DEV_RTI7_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                                     | CLK_STATE_READY     | 32768           | 3    | DEV_RTI7_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK                | CLK_STATE_READY     | 12500000        | 4    | DEV_RTI7_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK                  | CLK_STATE_READY     | 32000           | 5    | DEV_RTI7_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                                      | CLK_STATE_READY     | 0               | 6    | DEV_RTI7_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0                                 | CLK_STATE_READY     | 0               | 7    | DEV_RTI7_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1                                 | CLK_STATE_READY     | 0               | 8    | DEV_RTI7_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2                                 | CLK_STATE_READY     | 0               | 9    | DEV_RTI7_VBUSP_CLK                                                                  | CLK_STATE_READY     | 125000000       | 0    | DEV_SA2_CPSW_PSILSS0_MAIN_2_CLK                                                     | CLK_STATE_READY     | 250000000       | 1    | DEV_SA2_CPSW_PSILSS0_MAIN_CLK                                                       | CLK_STATE_READY     | 500000000       | 0    | DEV_SA2_UL0_PKA_IN_CLK                                                              | CLK_STATE_READY     | 400000000       | 1    | DEV_SA2_UL0_X1_CLK                                                                  | CLK_STATE_READY     | 125000000       | 2    | DEV_SA2_UL0_X2_CLK                                                                  | CLK_STATE_READY     | 250000000       | 2    | DEV_SERDES_10G0_CLK                                                                 | CLK_STATE_READY     | 125000000       | 3    | DEV_SERDES_10G0_CMN_REFCLK_M                                                        | CLK_STATE_READY     | 0               | 3    | DEV_SERDES_10G0_CMN_REFCLK_M                                                        | CLK_STATE_READY     | 0               | 4    | DEV_SERDES_10G0_CMN_REFCLK_P                                                        | CLK_STATE_READY     | 0               | 4    | DEV_SERDES_10G0_CMN_REFCLK_P                                                        | CLK_STATE_READY     | 0               | 5    | DEV_SERDES_10G0_CORE_REF1_CLK                                                       | CLK_STATE_READY     | 156250000       | 6    | DEV_SERDES_10G0_CORE_REF_CLK                                                        | CLK_STATE_READY     | 100000000       | 7    | DEV_SERDES_10G0_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                         | CLK_STATE_READY     | 24000000        | 8    | DEV_SERDES_10G0_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                          | CLK_STATE_READY     | 0               | 9    | DEV_SERDES_10G0_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK               | CLK_STATE_READY     | 156250000       | 10    | DEV_SERDES_10G0_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK               | CLK_STATE_READY     | 100000000       | 15    | DEV_SERDES_10G0_IP1_LN0_TXCLK                                                       | CLK_STATE_READY     | 0               | 21    | DEV_SERDES_10G0_IP1_LN1_TXCLK                                                       | CLK_STATE_READY     | 0               | 24    | DEV_SERDES_10G0_IP1_LN2_REFCLK                                                      | CLK_STATE_READY     | 0               | 25    | DEV_SERDES_10G0_IP1_LN2_RXCLK                                                       | CLK_STATE_READY     | 0               | 26    | DEV_SERDES_10G0_IP1_LN2_RXFCLK                                                      | CLK_STATE_READY     | 0               | 27    | DEV_SERDES_10G0_IP1_LN2_TXCLK                                                       | CLK_STATE_READY     | 0               | 28    | DEV_SERDES_10G0_IP1_LN2_TXFCLK                                                      | CLK_STATE_READY     | 0               | 29    | DEV_SERDES_10G0_IP1_LN2_TXMCLK                                                      | CLK_STATE_READY     | 0               | 30    | DEV_SERDES_10G0_IP1_LN3_REFCLK                                                      | CLK_STATE_READY     | 0               | 31    | DEV_SERDES_10G0_IP1_LN3_RXCLK                                                       | CLK_STATE_READY     | 0               | 32    | DEV_SERDES_10G0_IP1_LN3_RXFCLK                                                      | CLK_STATE_READY     | 0               | 33    | DEV_SERDES_10G0_IP1_LN3_TXCLK                                                       | CLK_STATE_READY     | 0               | 34    | DEV_SERDES_10G0_IP1_LN3_TXFCLK                                                      | CLK_STATE_READY     | 0               | 35    | DEV_SERDES_10G0_IP1_LN3_TXMCLK                                                      | CLK_STATE_READY     | 0               | 36    | DEV_SERDES_10G0_IP2_LN0_REFCLK                                                      | CLK_STATE_READY     | 0               | 37    | DEV_SERDES_10G0_IP2_LN0_RXCLK                                                       | CLK_STATE_READY     | 0               | 38    | DEV_SERDES_10G0_IP2_LN0_RXFCLK                                                      | CLK_STATE_READY     | 0               | 39    | DEV_SERDES_10G0_IP2_LN0_TXCLK                                                       | CLK_STATE_READY     | 0               | 40    | DEV_SERDES_10G0_IP2_LN0_TXFCLK                                                      | CLK_STATE_READY     | 0               | 41    | DEV_SERDES_10G0_IP2_LN0_TXMCLK                                                      | CLK_STATE_READY     | 0               | 42    | DEV_SERDES_10G0_IP2_LN1_REFCLK                                                      | CLK_STATE_READY     | 0               | 43    | DEV_SERDES_10G0_IP2_LN1_RXCLK                                                       | CLK_STATE_READY     | 0               | 44    | DEV_SERDES_10G0_IP2_LN1_RXFCLK                                                      | CLK_STATE_READY     | 0               | 45    | DEV_SERDES_10G0_IP2_LN1_TXCLK                                                       | CLK_STATE_READY     | 0               | 46    | DEV_SERDES_10G0_IP2_LN1_TXFCLK                                                      | CLK_STATE_READY     | 0               | 47    | DEV_SERDES_10G0_IP2_LN1_TXMCLK                                                      | CLK_STATE_READY     | 0               | 48    | DEV_SERDES_10G0_IP2_LN2_REFCLK                                                      | CLK_STATE_READY     | 0               | 49    | DEV_SERDES_10G0_IP2_LN2_RXCLK                                                       | CLK_STATE_READY     | 0               | 50    | DEV_SERDES_10G0_IP2_LN2_RXFCLK                                                      | CLK_STATE_READY     | 0               | 51    | DEV_SERDES_10G0_IP2_LN2_TXCLK                                                       | CLK_STATE_READY     | 0               | 52    | DEV_SERDES_10G0_IP2_LN2_TXFCLK                                                      | CLK_STATE_READY     | 0               | 53    | DEV_SERDES_10G0_IP2_LN2_TXMCLK                                                      | CLK_STATE_READY     | 0               | 54    | DEV_SERDES_10G0_IP2_LN3_REFCLK                                                      | CLK_STATE_READY     | 0               | 55    | DEV_SERDES_10G0_IP2_LN3_RXCLK                                                       | CLK_STATE_READY     | 0               | 56    | DEV_SERDES_10G0_IP2_LN3_RXFCLK                                                      | CLK_STATE_READY     | 0               | 57    | DEV_SERDES_10G0_IP2_LN3_TXCLK                                                       | CLK_STATE_READY     | 0               | 58    | DEV_SERDES_10G0_IP2_LN3_TXFCLK                                                      | CLK_STATE_READY     | 0               | 59    | DEV_SERDES_10G0_IP2_LN3_TXMCLK                                                      | CLK_STATE_READY     | 0               | 78    | DEV_SERDES_10G0_IP3_LN3_REFCLK                                                      | CLK_STATE_READY     | 0               | 79    | DEV_SERDES_10G0_IP3_LN3_RXCLK                                                       | CLK_STATE_READY     | 0               | 80    | DEV_SERDES_10G0_IP3_LN3_RXFCLK                                                      | CLK_STATE_READY     | 0               | 81    | DEV_SERDES_10G0_IP3_LN3_TXCLK                                                       | CLK_STATE_READY     | 0               | 82    | DEV_SERDES_10G0_IP3_LN3_TXFCLK                                                      | CLK_STATE_READY     | 0               | 83    | DEV_SERDES_10G0_IP3_LN3_TXMCLK                                                      | CLK_STATE_READY     | 0               | 84    | DEV_SERDES_10G0_IP4_LN0_REFCLK                                                      | CLK_STATE_READY     | 0               | 85    | DEV_SERDES_10G0_IP4_LN0_RXCLK                                                       | CLK_STATE_READY     | 0               | 86    | DEV_SERDES_10G0_IP4_LN0_RXFCLK                                                      | CLK_STATE_READY     | 0               | 87    | DEV_SERDES_10G0_IP4_LN0_TXCLK                                                       | CLK_STATE_READY     | 0               | 88    | DEV_SERDES_10G0_IP4_LN0_TXFCLK                                                      | CLK_STATE_READY     | 0               | 89    | DEV_SERDES_10G0_IP4_LN0_TXMCLK                                                      | CLK_STATE_READY     | 0               | 90    | DEV_SERDES_10G0_IP4_LN1_REFCLK                                                      | CLK_STATE_READY     | 0               | 91    | DEV_SERDES_10G0_IP4_LN1_RXCLK                                                       | CLK_STATE_READY     | 0               | 92    | DEV_SERDES_10G0_IP4_LN1_RXFCLK                                                      | CLK_STATE_READY     | 0               | 93    | DEV_SERDES_10G0_IP4_LN1_TXCLK                                                       | CLK_STATE_READY     | 0               | 94    | DEV_SERDES_10G0_IP4_LN1_TXFCLK                                                      | CLK_STATE_READY     | 0               | 95    | DEV_SERDES_10G0_IP4_LN1_TXMCLK                                                      | CLK_STATE_READY     | 0               | 96    | DEV_SERDES_10G0_IP4_LN2_REFCLK                                                      | CLK_STATE_READY     | 0               | 97    | DEV_SERDES_10G0_IP4_LN2_RXCLK                                                       | CLK_STATE_READY     | 0               | 98    | DEV_SERDES_10G0_IP4_LN2_RXFCLK                                                      | CLK_STATE_READY     | 0               | 99    | DEV_SERDES_10G0_IP4_LN2_TXCLK                                                       | CLK_STATE_READY     | 0               | | DEV_SERDES_10G0_IP4_LN2_TXFCLK                                                      | CLK_STATE_READY     | 0               | | DEV_SERDES_10G0_IP4_LN2_TXMCLK                                                      | CLK_STATE_READY     | 0               | | DEV_SERDES_10G0_IP4_LN3_REFCLK                                                      | CLK_STATE_READY     | 0               | | DEV_SERDES_10G0_IP4_LN3_RXCLK                                                       | CLK_STATE_READY     | 0               | | DEV_SERDES_10G0_IP4_LN3_RXFCLK                                                      | CLK_STATE_READY     | 0               | | DEV_SERDES_10G0_IP4_LN3_TXCLK                                                       | CLK_STATE_READY     | 0               | | DEV_SERDES_10G0_IP4_LN3_TXFCLK                                                      | CLK_STATE_READY     | 0               | | DEV_SERDES_10G0_IP4_LN3_TXMCLK                                                      | CLK_STATE_READY     | 0               | | DEV_SERDES_10G0_REF_DER_OUT_CLK                                                     | CLK_STATE_READY     | 0               | | DEV_SERDES_10G0_REF_OUT_CLK                                                         | CLK_STATE_READY     | 0               | | DEV_SERDES_10G0_TAP_TCK                                                             | CLK_STATE_READY     | 0               | 2    | DEV_SERDES_10G1_CLK                                                                 | CLK_STATE_READY     | 125000000       | 3    | DEV_SERDES_10G1_CMN_REFCLK_M                                                        | CLK_STATE_READY     | 0               | 3    | DEV_SERDES_10G1_CMN_REFCLK_M                                                        | CLK_STATE_READY     | 0               | 4    | DEV_SERDES_10G1_CMN_REFCLK_P                                                        | CLK_STATE_READY     | 0               | 4    | DEV_SERDES_10G1_CMN_REFCLK_P                                                        | CLK_STATE_READY     | 0               | 5    | DEV_SERDES_10G1_CORE_REF1_CLK                                                       | CLK_STATE_READY     | 156250000       | 6    | DEV_SERDES_10G1_CORE_REF_CLK                                                        | CLK_STATE_READY     | 100000000       | 7    | DEV_SERDES_10G1_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                         | CLK_STATE_READY     | 24000000        | 8    | DEV_SERDES_10G1_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                          | CLK_STATE_READY     | 0               | 9    | DEV_SERDES_10G1_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK               | CLK_STATE_READY     | 156250000       | 10    | DEV_SERDES_10G1_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK               | CLK_STATE_READY     | 100000000       | 12    | DEV_SERDES_10G1_IP1_LN0_REFCLK                                                      | CLK_STATE_READY     | 0               | 13    | DEV_SERDES_10G1_IP1_LN0_RXCLK                                                       | CLK_STATE_READY     | 0               | 14    | DEV_SERDES_10G1_IP1_LN0_RXFCLK                                                      | CLK_STATE_READY     | 0               | 15    | DEV_SERDES_10G1_IP1_LN0_TXCLK                                                       | CLK_STATE_READY     | 0               | 16    | DEV_SERDES_10G1_IP1_LN0_TXFCLK                                                      | CLK_STATE_READY     | 0               | 17    | DEV_SERDES_10G1_IP1_LN0_TXMCLK                                                      | CLK_STATE_READY     | 0               | 18    | DEV_SERDES_10G1_IP1_LN1_REFCLK                                                      | CLK_STATE_READY     | 0               | 19    | DEV_SERDES_10G1_IP1_LN1_RXCLK                                                       | CLK_STATE_READY     | 0               | 20    | DEV_SERDES_10G1_IP1_LN1_RXFCLK                                                      | CLK_STATE_READY     | 0               | 21    | DEV_SERDES_10G1_IP1_LN1_TXCLK                                                       | CLK_STATE_READY     | 0               | 22    | DEV_SERDES_10G1_IP1_LN1_TXFCLK                                                      | CLK_STATE_READY     | 0               | 23    | DEV_SERDES_10G1_IP1_LN1_TXMCLK                                                      | CLK_STATE_READY     | 0               | 24    | DEV_SERDES_10G1_IP1_LN2_REFCLK                                                      | CLK_STATE_READY     | 0               | 25    | DEV_SERDES_10G1_IP1_LN2_RXCLK                                                       | CLK_STATE_READY     | 0               | 26    | DEV_SERDES_10G1_IP1_LN2_RXFCLK                                                      | CLK_STATE_READY     | 0               | 27    | DEV_SERDES_10G1_IP1_LN2_TXCLK                                                       | CLK_STATE_READY     | 0               | 28    | DEV_SERDES_10G1_IP1_LN2_TXFCLK                                                      | CLK_STATE_READY     | 0               | 29    | DEV_SERDES_10G1_IP1_LN2_TXMCLK                                                      | CLK_STATE_READY     | 0               | 30    | DEV_SERDES_10G1_IP1_LN3_REFCLK                                                      | CLK_STATE_READY     | 0               | 31    | DEV_SERDES_10G1_IP1_LN3_RXCLK                                                       | CLK_STATE_READY     | 0               | 32    | DEV_SERDES_10G1_IP1_LN3_RXFCLK                                                      | CLK_STATE_READY     | 0               | 33    | DEV_SERDES_10G1_IP1_LN3_TXCLK                                                       | CLK_STATE_READY     | 0               | 34    | DEV_SERDES_10G1_IP1_LN3_TXFCLK                                                      | CLK_STATE_READY     | 0               | 35    | DEV_SERDES_10G1_IP1_LN3_TXMCLK                                                      | CLK_STATE_READY     | 0               | 36    | DEV_SERDES_10G1_IP2_LN0_REFCLK                                                      | CLK_STATE_READY     | 0               | 37    | DEV_SERDES_10G1_IP2_LN0_RXCLK                                                       | CLK_STATE_READY     | 0               | 38    | DEV_SERDES_10G1_IP2_LN0_RXFCLK                                                      | CLK_STATE_READY     | 0               | 39    | DEV_SERDES_10G1_IP2_LN0_TXCLK                                                       | CLK_STATE_READY     | 0               | 40    | DEV_SERDES_10G1_IP2_LN0_TXFCLK                                                      | CLK_STATE_READY     | 0               | 41    | DEV_SERDES_10G1_IP2_LN0_TXMCLK                                                      | CLK_STATE_READY     | 0               | 42    | DEV_SERDES_10G1_IP2_LN1_REFCLK                                                      | CLK_STATE_READY     | 0               | 43    | DEV_SERDES_10G1_IP2_LN1_RXCLK                                                       | CLK_STATE_READY     | 0               | 44    | DEV_SERDES_10G1_IP2_LN1_RXFCLK                                                      | CLK_STATE_READY     | 0               | 45    | DEV_SERDES_10G1_IP2_LN1_TXCLK                                                       | CLK_STATE_READY     | 0               | 46    | DEV_SERDES_10G1_IP2_LN1_TXFCLK                                                      | CLK_STATE_READY     | 0               | 47    | DEV_SERDES_10G1_IP2_LN1_TXMCLK                                                      | CLK_STATE_READY     | 0               | 48    | DEV_SERDES_10G1_IP2_LN2_REFCLK                                                      | CLK_STATE_READY     | 0               | 49    | DEV_SERDES_10G1_IP2_LN2_RXCLK                                                       | CLK_STATE_READY     | 0               | 50    | DEV_SERDES_10G1_IP2_LN2_RXFCLK                                                      | CLK_STATE_READY     | 0               | 51    | DEV_SERDES_10G1_IP2_LN2_TXCLK                                                       | CLK_STATE_READY     | 0               | 52    | DEV_SERDES_10G1_IP2_LN2_TXFCLK                                                      | CLK_STATE_READY     | 0               | 53    | DEV_SERDES_10G1_IP2_LN2_TXMCLK                                                      | CLK_STATE_READY     | 0               | 54    | DEV_SERDES_10G1_IP2_LN3_REFCLK                                                      | CLK_STATE_READY     | 0               | 55    | DEV_SERDES_10G1_IP2_LN3_RXCLK                                                       | CLK_STATE_READY     | 0               | 56    | DEV_SERDES_10G1_IP2_LN3_RXFCLK                                                      | CLK_STATE_READY     | 0               | 57    | DEV_SERDES_10G1_IP2_LN3_TXCLK                                                       | CLK_STATE_READY     | 0               | 58    | DEV_SERDES_10G1_IP2_LN3_TXFCLK                                                      | CLK_STATE_READY     | 0               | 59    | DEV_SERDES_10G1_IP2_LN3_TXMCLK                                                      | CLK_STATE_READY     | 0               | 72    | DEV_SERDES_10G1_IP3_LN2_REFCLK                                                      | CLK_STATE_READY     | 0               | 73    | DEV_SERDES_10G1_IP3_LN2_RXCLK                                                       | CLK_STATE_READY     | 0               | 74    | DEV_SERDES_10G1_IP3_LN2_RXFCLK                                                      | CLK_STATE_READY     | 0               | 75    | DEV_SERDES_10G1_IP3_LN2_TXCLK                                                       | CLK_STATE_READY     | 0               | 76    | DEV_SERDES_10G1_IP3_LN2_TXFCLK                                                      | CLK_STATE_READY     | 0               | 77    | DEV_SERDES_10G1_IP3_LN2_TXMCLK                                                      | CLK_STATE_READY     | 0               | 78    | DEV_SERDES_10G1_IP3_LN3_REFCLK                                                      | CLK_STATE_READY     | 0               | 79    | DEV_SERDES_10G1_IP3_LN3_RXCLK                                                       | CLK_STATE_READY     | 0               | 80    | DEV_SERDES_10G1_IP3_LN3_RXFCLK                                                      | CLK_STATE_READY     | 0               | 81    | DEV_SERDES_10G1_IP3_LN3_TXCLK                                                       | CLK_STATE_READY     | 0               | 82    | DEV_SERDES_10G1_IP3_LN3_TXFCLK                                                      | CLK_STATE_READY     | 0               | 83    | DEV_SERDES_10G1_IP3_LN3_TXMCLK                                                      | CLK_STATE_READY     | 0               | | DEV_SERDES_10G1_REF_DER_OUT_CLK                                                     | CLK_STATE_READY     | 0               | | DEV_SERDES_10G1_REF_OUT_CLK                                                         | CLK_STATE_READY     | 0               | | DEV_SERDES_10G1_TAP_TCK                                                             | CLK_STATE_READY     | 0               | 2    | DEV_SERDES_10G2_CLK                                                                 | CLK_STATE_READY     | 125000000       | 3    | DEV_SERDES_10G2_CMN_REFCLK_M                                                        | CLK_STATE_READY     | 0               | 3    | DEV_SERDES_10G2_CMN_REFCLK_M                                                        | CLK_STATE_READY     | 0               | 4    | DEV_SERDES_10G2_CMN_REFCLK_P                                                        | CLK_STATE_READY     | 0               | 5    | DEV_SERDES_10G2_CORE_REF1_CLK                                                       | CLK_STATE_READY     | 156250000       | 6    | DEV_SERDES_10G2_CORE_REF_CLK                                                        | CLK_STATE_READY     | 24000000        | 7    | DEV_SERDES_10G2_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                         | CLK_STATE_READY     | 24000000        | 8    | DEV_SERDES_10G2_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                          | CLK_STATE_READY     | 0               | 9    | DEV_SERDES_10G2_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK               | CLK_STATE_READY     | 156250000       | 10    | DEV_SERDES_10G2_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK               | CLK_STATE_READY     | 100000000       | 12    | DEV_SERDES_10G2_IP1_LN0_REFCLK                                                      | CLK_STATE_READY     | 0               | 13    | DEV_SERDES_10G2_IP1_LN0_RXCLK                                                       | CLK_STATE_READY     | 0               | 14    | DEV_SERDES_10G2_IP1_LN0_RXFCLK                                                      | CLK_STATE_READY     | 0               | 15    | DEV_SERDES_10G2_IP1_LN0_TXCLK                                                       | CLK_STATE_READY     | 0               | 16    | DEV_SERDES_10G2_IP1_LN0_TXFCLK                                                      | CLK_STATE_READY     | 0               | 17    | DEV_SERDES_10G2_IP1_LN0_TXMCLK                                                      | CLK_STATE_READY     | 0               | 18    | DEV_SERDES_10G2_IP1_LN1_REFCLK                                                      | CLK_STATE_READY     | 0               | 19    | DEV_SERDES_10G2_IP1_LN1_RXCLK                                                       | CLK_STATE_READY     | 0               | 20    | DEV_SERDES_10G2_IP1_LN1_RXFCLK                                                      | CLK_STATE_READY     | 0               | 21    | DEV_SERDES_10G2_IP1_LN1_TXCLK                                                       | CLK_STATE_READY     | 0               | 22    | DEV_SERDES_10G2_IP1_LN1_TXFCLK                                                      | CLK_STATE_READY     | 0               | 23    | DEV_SERDES_10G2_IP1_LN1_TXMCLK                                                      | CLK_STATE_READY     | 0               | 24    | DEV_SERDES_10G2_IP1_LN2_REFCLK                                                      | CLK_STATE_READY     | 0               | 25    | DEV_SERDES_10G2_IP1_LN2_RXCLK                                                       | CLK_STATE_READY     | 0               | 26    | DEV_SERDES_10G2_IP1_LN2_RXFCLK                                                      | CLK_STATE_READY     | 0               | 27    | DEV_SERDES_10G2_IP1_LN2_TXCLK                                                       | CLK_STATE_READY     | 0               | 28    | DEV_SERDES_10G2_IP1_LN2_TXFCLK                                                      | CLK_STATE_READY     | 0               | 29    | DEV_SERDES_10G2_IP1_LN2_TXMCLK                                                      | CLK_STATE_READY     | 0               | 30    | DEV_SERDES_10G2_IP1_LN3_REFCLK                                                      | CLK_STATE_READY     | 0               | 31    | DEV_SERDES_10G2_IP1_LN3_RXCLK                                                       | CLK_STATE_READY     | 0               | 32    | DEV_SERDES_10G2_IP1_LN3_RXFCLK                                                      | CLK_STATE_READY     | 0               | 33    | DEV_SERDES_10G2_IP1_LN3_TXCLK                                                       | CLK_STATE_READY     | 0               | 34    | DEV_SERDES_10G2_IP1_LN3_TXFCLK                                                      | CLK_STATE_READY     | 0               | 35    | DEV_SERDES_10G2_IP1_LN3_TXMCLK                                                      | CLK_STATE_READY     | 0               | 48    | DEV_SERDES_10G2_IP2_LN2_REFCLK                                                      | CLK_STATE_READY     | 0               | 49    | DEV_SERDES_10G2_IP2_LN2_RXCLK                                                       | CLK_STATE_READY     | 0               | 50    | DEV_SERDES_10G2_IP2_LN2_RXFCLK                                                      | CLK_STATE_READY     | 0               | 51    | DEV_SERDES_10G2_IP2_LN2_TXCLK                                                       | CLK_STATE_READY     | 0               | 52    | DEV_SERDES_10G2_IP2_LN2_TXFCLK                                                      | CLK_STATE_READY     | 0               | 53    | DEV_SERDES_10G2_IP2_LN2_TXMCLK                                                      | CLK_STATE_READY     | 0               | 54    | DEV_SERDES_10G2_IP2_LN3_REFCLK                                                      | CLK_STATE_READY     | 0               | 55    | DEV_SERDES_10G2_IP2_LN3_RXCLK                                                       | CLK_STATE_READY     | 0               | 56    | DEV_SERDES_10G2_IP2_LN3_RXFCLK                                                      | CLK_STATE_READY     | 0               | 57    | DEV_SERDES_10G2_IP2_LN3_TXCLK                                                       | CLK_STATE_READY     | 0               | 58    | DEV_SERDES_10G2_IP2_LN3_TXFCLK                                                      | CLK_STATE_READY     | 0               | 59    | DEV_SERDES_10G2_IP2_LN3_TXMCLK                                                      | CLK_STATE_READY     | 0               | | DEV_SERDES_10G2_TAP_TCK                                                             | CLK_STATE_READY     | 0               | 2    | DEV_SERDES_10G4_CLK                                                                 | CLK_STATE_READY     | 125000000       | 3    | DEV_SERDES_10G4_CMN_REFCLK_M                                                        | CLK_STATE_READY     | 0               | 3    | DEV_SERDES_10G4_CMN_REFCLK_M                                                        | CLK_STATE_READY     | 0               | 4    | DEV_SERDES_10G4_CMN_REFCLK_P                                                        | CLK_STATE_READY     | 0               | 4    | DEV_SERDES_10G4_CMN_REFCLK_P                                                        | CLK_STATE_READY     | 0               | 5    | DEV_SERDES_10G4_CORE_REF1_CLK                                                       | CLK_STATE_READY     | 156250000       | 6    | DEV_SERDES_10G4_CORE_REF_CLK                                                        | CLK_STATE_READY     | 100000000       | 7    | DEV_SERDES_10G4_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                         | CLK_STATE_READY     | 24000000        | 8    | DEV_SERDES_10G4_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                          | CLK_STATE_READY     | 0               | 9    | DEV_SERDES_10G4_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK               | CLK_STATE_READY     | 156250000       | 10    | DEV_SERDES_10G4_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK               | CLK_STATE_READY     | 100000000       | 12    | DEV_SERDES_10G4_IP1_LN0_REFCLK                                                      | CLK_STATE_READY     | 0               | 13    | DEV_SERDES_10G4_IP1_LN0_RXCLK                                                       | CLK_STATE_READY     | 0               | 14    | DEV_SERDES_10G4_IP1_LN0_RXFCLK                                                      | CLK_STATE_READY     | 0               | 15    | DEV_SERDES_10G4_IP1_LN0_TXCLK                                                       | CLK_STATE_READY     | 0               | 16    | DEV_SERDES_10G4_IP1_LN0_TXFCLK                                                      | CLK_STATE_READY     | 0               | 17    | DEV_SERDES_10G4_IP1_LN0_TXMCLK                                                      | CLK_STATE_READY     | 0               | 18    | DEV_SERDES_10G4_IP1_LN1_REFCLK                                                      | CLK_STATE_READY     | 0               | 19    | DEV_SERDES_10G4_IP1_LN1_RXCLK                                                       | CLK_STATE_READY     | 0               | 20    | DEV_SERDES_10G4_IP1_LN1_RXFCLK                                                      | CLK_STATE_READY     | 0               | 21    | DEV_SERDES_10G4_IP1_LN1_TXCLK                                                       | CLK_STATE_READY     | 0               | 22    | DEV_SERDES_10G4_IP1_LN1_TXFCLK                                                      | CLK_STATE_READY     | 0               | 23    | DEV_SERDES_10G4_IP1_LN1_TXMCLK                                                      | CLK_STATE_READY     | 0               | 24    | DEV_SERDES_10G4_IP1_LN2_REFCLK                                                      | CLK_STATE_READY     | 0               | 25    | DEV_SERDES_10G4_IP1_LN2_RXCLK                                                       | CLK_STATE_READY     | 0               | 26    | DEV_SERDES_10G4_IP1_LN2_RXFCLK                                                      | CLK_STATE_READY     | 0               | 27    | DEV_SERDES_10G4_IP1_LN2_TXCLK                                                       | CLK_STATE_READY     | 0               | 28    | DEV_SERDES_10G4_IP1_LN2_TXFCLK                                                      | CLK_STATE_READY     | 0               | 29    | DEV_SERDES_10G4_IP1_LN2_TXMCLK                                                      | CLK_STATE_READY     | 0               | 30    | DEV_SERDES_10G4_IP1_LN3_REFCLK                                                      | CLK_STATE_READY     | 0               | 31    | DEV_SERDES_10G4_IP1_LN3_RXCLK                                                       | CLK_STATE_READY     | 0               | 32    | DEV_SERDES_10G4_IP1_LN3_RXFCLK                                                      | CLK_STATE_READY     | 0               | 33    | DEV_SERDES_10G4_IP1_LN3_TXCLK                                                       | CLK_STATE_READY     | 0               | 34    | DEV_SERDES_10G4_IP1_LN3_TXFCLK                                                      | CLK_STATE_READY     | 0               | 35    | DEV_SERDES_10G4_IP1_LN3_TXMCLK                                                      | CLK_STATE_READY     | 0               | 36    | DEV_SERDES_10G4_IP2_LN0_REFCLK                                                      | CLK_STATE_READY     | 0               | 37    | DEV_SERDES_10G4_IP2_LN0_RXCLK                                                       | CLK_STATE_READY     | 0               | 38    | DEV_SERDES_10G4_IP2_LN0_RXFCLK                                                      | CLK_STATE_READY     | 0               | 39    | DEV_SERDES_10G4_IP2_LN0_TXCLK                                                       | CLK_STATE_READY     | 0               | 40    | DEV_SERDES_10G4_IP2_LN0_TXFCLK                                                      | CLK_STATE_READY     | 0               | 41    | DEV_SERDES_10G4_IP2_LN0_TXMCLK                                                      | CLK_STATE_READY     | 0               | 42    | DEV_SERDES_10G4_IP2_LN1_REFCLK                                                      | CLK_STATE_READY     | 0               | 43    | DEV_SERDES_10G4_IP2_LN1_RXCLK                                                       | CLK_STATE_READY     | 0               | 44    | DEV_SERDES_10G4_IP2_LN1_RXFCLK                                                      | CLK_STATE_READY     | 0               | 45    | DEV_SERDES_10G4_IP2_LN1_TXCLK                                                       | CLK_STATE_READY     | 0               | 46    | DEV_SERDES_10G4_IP2_LN1_TXFCLK                                                      | CLK_STATE_READY     | 0               | 47    | DEV_SERDES_10G4_IP2_LN1_TXMCLK                                                      | CLK_STATE_READY     | 0               | 48    | DEV_SERDES_10G4_IP2_LN2_REFCLK                                                      | CLK_STATE_READY     | 0               | 49    | DEV_SERDES_10G4_IP2_LN2_RXCLK                                                       | CLK_STATE_READY     | 0               | 50    | DEV_SERDES_10G4_IP2_LN2_RXFCLK                                                      | CLK_STATE_READY     | 0               | 51    | DEV_SERDES_10G4_IP2_LN2_TXCLK                                                       | CLK_STATE_READY     | 0               | 52    | DEV_SERDES_10G4_IP2_LN2_TXFCLK                                                      | CLK_STATE_READY     | 0               | 53    | DEV_SERDES_10G4_IP2_LN2_TXMCLK                                                      | CLK_STATE_READY     | 0               | 54    | DEV_SERDES_10G4_IP2_LN3_REFCLK                                                      | CLK_STATE_READY     | 0               | 55    | DEV_SERDES_10G4_IP2_LN3_RXCLK                                                       | CLK_STATE_READY     | 0               | 56    | DEV_SERDES_10G4_IP2_LN3_RXFCLK                                                      | CLK_STATE_READY     | 0               | 57    | DEV_SERDES_10G4_IP2_LN3_TXCLK                                                       | CLK_STATE_READY     | 0               | 58    | DEV_SERDES_10G4_IP2_LN3_TXFCLK                                                      | CLK_STATE_READY     | 0               | 59    | DEV_SERDES_10G4_IP2_LN3_TXMCLK                                                      | CLK_STATE_READY     | 0               | 78    | DEV_SERDES_10G4_IP3_LN3_REFCLK                                                      | CLK_STATE_READY     | 0               | 79    | DEV_SERDES_10G4_IP3_LN3_RXCLK                                                       | CLK_STATE_READY     | 0               | 80    | DEV_SERDES_10G4_IP3_LN3_RXFCLK                                                      | CLK_STATE_READY     | 0               | 81    | DEV_SERDES_10G4_IP3_LN3_TXCLK                                                       | CLK_STATE_READY     | 0               | 82    | DEV_SERDES_10G4_IP3_LN3_TXFCLK                                                      | CLK_STATE_READY     | 0               | 83    | DEV_SERDES_10G4_IP3_LN3_TXMCLK                                                      | CLK_STATE_READY     | 0               | 84    | DEV_SERDES_10G4_IP4_LN0_REFCLK                                                      | CLK_STATE_READY     | 0               | 85    | DEV_SERDES_10G4_IP4_LN0_RXCLK                                                       | CLK_STATE_READY     | 0               | 86    | DEV_SERDES_10G4_IP4_LN0_RXFCLK                                                      | CLK_STATE_READY     | 0               | 87    | DEV_SERDES_10G4_IP4_LN0_TXCLK                                                       | CLK_STATE_READY     | 0               | 88    | DEV_SERDES_10G4_IP4_LN0_TXFCLK                                                      | CLK_STATE_READY     | 0               | 89    | DEV_SERDES_10G4_IP4_LN0_TXMCLK                                                      | CLK_STATE_READY     | 0               | 90    | DEV_SERDES_10G4_IP4_LN1_REFCLK                                                      | CLK_STATE_READY     | 0               | 91    | DEV_SERDES_10G4_IP4_LN1_RXCLK                                                       | CLK_STATE_READY     | 0               | 92    | DEV_SERDES_10G4_IP4_LN1_RXFCLK                                                      | CLK_STATE_READY     | 0               | 93    | DEV_SERDES_10G4_IP4_LN1_TXCLK                                                       | CLK_STATE_READY     | 0               | 94    | DEV_SERDES_10G4_IP4_LN1_TXFCLK                                                      | CLK_STATE_READY     | 0               | 95    | DEV_SERDES_10G4_IP4_LN1_TXMCLK                                                      | CLK_STATE_READY     | 0               | 96    | DEV_SERDES_10G4_IP4_LN2_REFCLK                                                      | CLK_STATE_READY     | 0               | 97    | DEV_SERDES_10G4_IP4_LN2_RXCLK                                                       | CLK_STATE_READY     | 0               | 98    | DEV_SERDES_10G4_IP4_LN2_RXFCLK                                                      | CLK_STATE_READY     | 0               | 99    | DEV_SERDES_10G4_IP4_LN2_TXCLK                                                       | CLK_STATE_READY     | 0               | | DEV_SERDES_10G4_IP4_LN2_TXFCLK                                                      | CLK_STATE_READY     | 0               | | DEV_SERDES_10G4_IP4_LN2_TXMCLK                                                      | CLK_STATE_READY     | 0               | | DEV_SERDES_10G4_IP4_LN3_REFCLK                                                      | CLK_STATE_READY     | 0               | | DEV_SERDES_10G4_IP4_LN3_RXCLK                                                       | CLK_STATE_READY     | 0               | | DEV_SERDES_10G4_IP4_LN3_RXFCLK                                                      | CLK_STATE_READY     | 0               | | DEV_SERDES_10G4_IP4_LN3_TXCLK                                                       | CLK_STATE_READY     | 0               | | DEV_SERDES_10G4_IP4_LN3_TXFCLK                                                      | CLK_STATE_READY     | 0               | | DEV_SERDES_10G4_IP4_LN3_TXMCLK                                                      | CLK_STATE_READY     | 0               | 0    | DEV_STM0_ATB_CLK                                                                    | CLK_STATE_READY     | 250000000       | 1    | DEV_STM0_CORE_CLK                                                                   | CLK_STATE_READY     | 250000000       | 2    | DEV_STM0_VBUSP_CLK                                                                  | CLK_STATE_READY     | 125000000       | 0    | DEV_TIMER0_TIMER_HCLK_CLK                                                           | CLK_STATE_READY     | 125000000       | 1    | DEV_TIMER0_TIMER_PWM                                                                | CLK_STATE_READY     | 0               | 2    | DEV_TIMER0_TIMER_TCLK_CLK                                                           | CLK_STATE_READY     | 24000000        | 3    | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                            | CLK_STATE_READY     | 24000000        | 4    | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                             | CLK_STATE_READY     | 0               | 5    | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK                | CLK_STATE_READY     | 250000000       | 6    | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK       | CLK_STATE_READY     | 12500000        | 7    | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK                  | CLK_STATE_READY     | 250000000       | 8    | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                        | CLK_STATE_READY     | 0               | 9    | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT                            | CLK_STATE_READY     | 0               | 10    | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                            | CLK_STATE_READY     | 32768           | 11    | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT                          | CLK_STATE_READY     | 0               | 12    | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK                  | CLK_STATE_READY     | 192000000       | 13    | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK                | CLK_STATE_READY     | 225000000       | 14    | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK                  | CLK_STATE_READY     | 196608000       | 15    | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2                    | CLK_STATE_READY     | 0               | 16    | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3                    | CLK_STATE_READY     | 0               | 17    | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0                       | CLK_STATE_READY     | 0               | 18    | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_J7AM_MAIN_0_CPTS_GENF0                  | CLK_STATE_READY     | 0               | 0    | DEV_TIMER1_TIMER_HCLK_CLK                                                           | CLK_STATE_READY     | 125000000       | 2    | DEV_TIMER1_TIMER_TCLK_CLK                                                           | CLK_STATE_READY     | 24000000        | 3    | DEV_TIMER1_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT1                             | CLK_STATE_READY     | 24000000        | 4    | DEV_TIMER1_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_0_TIMER_PWM                    | CLK_STATE_READY     | 0               | 0    | DEV_TIMER10_TIMER_HCLK_CLK                                                          | CLK_STATE_READY     | 125000000       | 1    | DEV_TIMER10_TIMER_PWM                                                               | CLK_STATE_READY     | 0               | 2    | DEV_TIMER10_TIMER_TCLK_CLK                                                          | CLK_STATE_READY     | 24000000        | 3    | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                           | CLK_STATE_READY     | 24000000        | 4    | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                            | CLK_STATE_READY     | 0               | 5    | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK               | CLK_STATE_READY     | 250000000       | 6    | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK      | CLK_STATE_READY     | 12500000        | 7    | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK                 | CLK_STATE_READY     | 250000000       | 8    | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                       | CLK_STATE_READY     | 0               | 9    | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT                           | CLK_STATE_READY     | 0               | 10    | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                           | CLK_STATE_READY     | 32768           | 11    | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT                         | CLK_STATE_READY     | 0               | 12    | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK                 | CLK_STATE_READY     | 192000000       | 13    | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK               | CLK_STATE_READY     | 225000000       | 14    | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK                 | CLK_STATE_READY     | 196608000       | 15    | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2                   | CLK_STATE_READY     | 0               | 16    | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3                   | CLK_STATE_READY     | 0               | 17    | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0                      | CLK_STATE_READY     | 0               | 18    | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_J7AM_MAIN_0_CPTS_GENF0                 | CLK_STATE_READY     | 0               | 0    | DEV_TIMER11_TIMER_HCLK_CLK                                                          | CLK_STATE_READY     | 125000000       | 2    | DEV_TIMER11_TIMER_TCLK_CLK                                                          | CLK_STATE_READY     | 24000000        | 3    | DEV_TIMER11_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT11                           | CLK_STATE_READY     | 24000000        | 4    | DEV_TIMER11_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_10_TIMER_PWM                  | CLK_STATE_NOT_READY | 0               | 0    | DEV_TIMER12_TIMER_HCLK_CLK                                                          | CLK_STATE_READY     | 125000000       | 1    | DEV_TIMER12_TIMER_PWM                                                               | CLK_STATE_READY     | 0               | 2    | DEV_TIMER12_TIMER_TCLK_CLK                                                          | CLK_STATE_READY     | 24000000        | 3    | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                           | CLK_STATE_READY     | 24000000        | 4    | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                            | CLK_STATE_READY     | 0               | 5    | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK               | CLK_STATE_READY     | 250000000       | 6    | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK      | CLK_STATE_READY     | 12500000        | 7    | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK                 | CLK_STATE_READY     | 250000000       | 8    | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                       | CLK_STATE_READY     | 0               | 9    | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT                           | CLK_STATE_READY     | 0               | 10    | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                           | CLK_STATE_READY     | 32768           | 11    | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT                         | CLK_STATE_READY     | 0               | 12    | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK                 | CLK_STATE_READY     | 192000000       | 13    | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK               | CLK_STATE_READY     | 225000000       | 14    | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK                 | CLK_STATE_READY     | 196608000       | 15    | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2                   | CLK_STATE_READY     | 0               | 16    | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3                   | CLK_STATE_READY     | 0               | 17    | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0                      | CLK_STATE_READY     | 0               | 18    | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_J7AM_MAIN_0_CPTS_GENF0                 | CLK_STATE_READY     | 0               | 0    | DEV_TIMER13_TIMER_HCLK_CLK                                                          | CLK_STATE_READY     | 125000000       | 2    | DEV_TIMER13_TIMER_TCLK_CLK                                                          | CLK_STATE_READY     | 24000000        | 3    | DEV_TIMER13_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT13                           | CLK_STATE_READY     | 24000000        | 4    | DEV_TIMER13_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_12_TIMER_PWM                  | CLK_STATE_NOT_READY | 0               | 0    | DEV_TIMER14_TIMER_HCLK_CLK                                                          | CLK_STATE_READY     | 125000000       | 1    | DEV_TIMER14_TIMER_PWM                                                               | CLK_STATE_READY     | 0               | 2    | DEV_TIMER14_TIMER_TCLK_CLK                                                          | CLK_STATE_READY     | 24000000        | 3    | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                           | CLK_STATE_READY     | 24000000        | 4    | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                            | CLK_STATE_READY     | 0               | 5    | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK               | CLK_STATE_READY     | 250000000       | 6    | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK      | CLK_STATE_READY     | 12500000        | 7    | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK                 | CLK_STATE_READY     | 250000000       | 8    | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                       | CLK_STATE_READY     | 0               | 9    | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT                           | CLK_STATE_READY     | 0               | 10    | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                           | CLK_STATE_READY     | 32768           | 11    | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT                         | CLK_STATE_READY     | 0               | 12    | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK                 | CLK_STATE_READY     | 192000000       | 13    | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK               | CLK_STATE_READY     | 225000000       | 14    | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK                 | CLK_STATE_READY     | 196608000       | 15    | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2                   | CLK_STATE_READY     | 0               | 16    | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3                   | CLK_STATE_READY     | 0               | 17    | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0                      | CLK_STATE_READY     | 0               | 18    | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_J7AM_MAIN_0_CPTS_GENF0                 | CLK_STATE_READY     | 0               | 0    | DEV_TIMER15_TIMER_HCLK_CLK                                                          | CLK_STATE_READY     | 125000000       | 2    | DEV_TIMER15_TIMER_TCLK_CLK                                                          | CLK_STATE_READY     | 24000000        | 3    | DEV_TIMER15_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT15                           | CLK_STATE_READY     | 24000000        | 4    | DEV_TIMER15_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_14_TIMER_PWM                  | CLK_STATE_NOT_READY | 0               | 0    | DEV_TIMER16_TIMER_HCLK_CLK                                                          | CLK_STATE_READY     | 125000000       | 1    | DEV_TIMER16_TIMER_PWM                                                               | CLK_STATE_READY     | 0               | 2    | DEV_TIMER16_TIMER_TCLK_CLK                                                          | CLK_STATE_READY     | 24000000        | 3    | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT16                           | CLK_STATE_READY     | 24000000        | 4    | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_MAIN_TIMER16_AFS_SEL_OUT0                         | CLK_STATE_READY     | 0               | 0    | DEV_TIMER17_TIMER_HCLK_CLK                                                          | CLK_STATE_READY     | 125000000       | 2    | DEV_TIMER17_TIMER_TCLK_CLK                                                          | CLK_STATE_READY     | 24000000        | 3    | DEV_TIMER17_TIMER_TCLK_CLK_PARENT_MAIN_TIMER17_AFS_EN_OUT0                          | CLK_STATE_READY     | 24000000        | 4    | DEV_TIMER17_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_16_TIMER_PWM                  | CLK_STATE_NOT_READY | 0               | 0    | DEV_TIMER18_TIMER_HCLK_CLK                                                          | CLK_STATE_READY     | 125000000       | 1    | DEV_TIMER18_TIMER_PWM                                                               | CLK_STATE_READY     | 0               | 2    | DEV_TIMER18_TIMER_TCLK_CLK                                                          | CLK_STATE_READY     | 24000000        | 3    | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT18                           | CLK_STATE_READY     | 24000000        | 4    | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_MAIN_TIMER18_AFS_SEL_OUT0                         | CLK_STATE_READY     | 0               | 0    | DEV_TIMER19_TIMER_HCLK_CLK                                                          | CLK_STATE_READY     | 125000000       | 2    | DEV_TIMER19_TIMER_TCLK_CLK                                                          | CLK_STATE_READY     | 24000000        | 3    | DEV_TIMER19_TIMER_TCLK_CLK_PARENT_MAIN_TIMER19_AFS_EN_OUT0                          | CLK_STATE_READY     | 24000000        | 4    | DEV_TIMER19_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_18_TIMER_PWM                  | CLK_STATE_NOT_READY | 0               | 0    | DEV_TIMER2_TIMER_HCLK_CLK                                                           | CLK_STATE_READY     | 125000000       | 1    | DEV_TIMER2_TIMER_PWM                                                                | CLK_STATE_READY     | 0               | 2    | DEV_TIMER2_TIMER_TCLK_CLK                                                           | CLK_STATE_READY     | 24000000        | 3    | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                            | CLK_STATE_READY     | 24000000        | 4    | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                             | CLK_STATE_READY     | 0               | 5    | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK                | CLK_STATE_READY     | 250000000       | 6    | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK       | CLK_STATE_READY     | 12500000        | 7    | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK                  | CLK_STATE_READY     | 250000000       | 8    | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                        | CLK_STATE_READY     | 0               | 9    | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT                            | CLK_STATE_READY     | 0               | 10    | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                            | CLK_STATE_READY     | 32768           | 11    | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT                          | CLK_STATE_READY     | 0               | 12    | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK                  | CLK_STATE_READY     | 192000000       | 13    | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK                | CLK_STATE_READY     | 225000000       | 14    | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK                  | CLK_STATE_READY     | 196608000       | 15    | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2                    | CLK_STATE_READY     | 0               | 16    | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3                    | CLK_STATE_READY     | 0               | 17    | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0                       | CLK_STATE_READY     | 0               | 18    | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_J7AM_MAIN_0_CPTS_GENF0                  | CLK_STATE_READY     | 0               | 0    | DEV_TIMER3_TIMER_HCLK_CLK                                                           | CLK_STATE_READY     | 125000000       | 2    | DEV_TIMER3_TIMER_TCLK_CLK                                                           | CLK_STATE_READY     | 24000000        | 3    | DEV_TIMER3_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT3                             | CLK_STATE_READY     | 24000000        | 4    | DEV_TIMER3_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_2_TIMER_PWM                    | CLK_STATE_READY     | 0               | 0    | DEV_TIMER4_TIMER_HCLK_CLK                                                           | CLK_STATE_READY     | 125000000       | 1    | DEV_TIMER4_TIMER_PWM                                                                | CLK_STATE_READY     | 0               | 2    | DEV_TIMER4_TIMER_TCLK_CLK                                                           | CLK_STATE_READY     | 24000000        | 3    | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                            | CLK_STATE_READY     | 24000000        | 4    | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                             | CLK_STATE_READY     | 0               | 5    | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK                | CLK_STATE_READY     | 250000000       | 6    | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK       | CLK_STATE_READY     | 12500000        | 7    | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK                  | CLK_STATE_READY     | 250000000       | 8    | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                        | CLK_STATE_READY     | 0               | 9    | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT                            | CLK_STATE_READY     | 0               | 10    | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                            | CLK_STATE_READY     | 32768           | 11    | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT                          | CLK_STATE_READY     | 0               | 12    | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK                  | CLK_STATE_READY     | 192000000       | 13    | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK                | CLK_STATE_READY     | 225000000       | 14    | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK                  | CLK_STATE_READY     | 196608000       | 15    | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2                    | CLK_STATE_READY     | 0               | 16    | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3                    | CLK_STATE_READY     | 0               | 17    | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0                       | CLK_STATE_READY     | 0               | 18    | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_J7AM_MAIN_0_CPTS_GENF0                  | CLK_STATE_READY     | 0               | 0    | DEV_TIMER5_TIMER_HCLK_CLK                                                           | CLK_STATE_READY     | 125000000       | 2    | DEV_TIMER5_TIMER_TCLK_CLK                                                           | CLK_STATE_READY     | 24000000        | 3    | DEV_TIMER5_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT5                             | CLK_STATE_READY     | 24000000        | 4    | DEV_TIMER5_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_4_TIMER_PWM                    | CLK_STATE_READY     | 0               | 0    | DEV_TIMER6_TIMER_HCLK_CLK                                                           | CLK_STATE_READY     | 125000000       | 1    | DEV_TIMER6_TIMER_PWM                                                                | CLK_STATE_READY     | 0               | 2    | DEV_TIMER6_TIMER_TCLK_CLK                                                           | CLK_STATE_READY     | 24000000        | 3    | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                            | CLK_STATE_READY     | 24000000        | 4    | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                             | CLK_STATE_READY     | 0               | 5    | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK                | CLK_STATE_READY     | 250000000       | 6    | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK       | CLK_STATE_READY     | 12500000        | 7    | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK                  | CLK_STATE_READY     | 250000000       | 8    | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                        | CLK_STATE_READY     | 0               | 9    | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT                            | CLK_STATE_READY     | 0               | 10    | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                            | CLK_STATE_READY     | 32768           | 11    | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT                          | CLK_STATE_READY     | 0               | 12    | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK                  | CLK_STATE_READY     | 192000000       | 13    | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK                | CLK_STATE_READY     | 225000000       | 14    | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK                  | CLK_STATE_READY     | 196608000       | 15    | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2                    | CLK_STATE_READY     | 0               | 16    | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3                    | CLK_STATE_READY     | 0               | 17    | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0                       | CLK_STATE_READY     | 0               | 18    | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_J7AM_MAIN_0_CPTS_GENF0                  | CLK_STATE_READY     | 0               | 0    | DEV_TIMER7_TIMER_HCLK_CLK                                                           | CLK_STATE_READY     | 125000000       | 2    | DEV_TIMER7_TIMER_TCLK_CLK                                                           | CLK_STATE_READY     | 24000000        | 3    | DEV_TIMER7_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT7                             | CLK_STATE_READY     | 24000000        | 4    | DEV_TIMER7_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_6_TIMER_PWM                    | CLK_STATE_READY     | 0               | 0    | DEV_TIMER8_TIMER_HCLK_CLK                                                           | CLK_STATE_READY     | 125000000       | 1    | DEV_TIMER8_TIMER_PWM                                                                | CLK_STATE_READY     | 0               | 2    | DEV_TIMER8_TIMER_TCLK_CLK                                                           | CLK_STATE_READY     | 24000000        | 3    | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                            | CLK_STATE_READY     | 24000000        | 4    | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                             | CLK_STATE_READY     | 0               | 5    | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK                | CLK_STATE_READY     | 250000000       | 6    | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK       | CLK_STATE_READY     | 12500000        | 7    | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK                  | CLK_STATE_READY     | 250000000       | 8    | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                        | CLK_STATE_READY     | 0               | 9    | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT                            | CLK_STATE_READY     | 0               | 10    | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                            | CLK_STATE_READY     | 32768           | 11    | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT                          | CLK_STATE_READY     | 0               | 12    | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK                  | CLK_STATE_READY     | 192000000       | 13    | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK                | CLK_STATE_READY     | 225000000       | 14    | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK                  | CLK_STATE_READY     | 196608000       | 15    | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2                    | CLK_STATE_READY     | 0               | 16    | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3                    | CLK_STATE_READY     | 0               | 17    | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0                       | CLK_STATE_READY     | 0               | 18    | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_J7AM_MAIN_0_CPTS_GENF0                  | CLK_STATE_READY     | 0               | 0    | DEV_TIMER9_TIMER_HCLK_CLK                                                           | CLK_STATE_READY     | 125000000       | 2    | DEV_TIMER9_TIMER_TCLK_CLK                                                           | CLK_STATE_READY     | 24000000        | 3    | DEV_TIMER9_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT9                             | CLK_STATE_READY     | 24000000        | 4    | DEV_TIMER9_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_8_TIMER_PWM                    | CLK_STATE_NOT_READY | 0               | 0    | DEV_TIMESYNC_INTRTR0_INTR_CLK                                                       | CLK_STATE_READY     | 125000000       | 0    | DEV_UART0_FCLK_CLK                                                                  | CLK_STATE_READY     | 48000000        | 3    | DEV_UART0_VBUSP_CLK                                                                 | CLK_STATE_READY     | 125000000       | 0    | DEV_UART1_FCLK_CLK                                                                  | CLK_STATE_READY     | 48000000        | 3    | DEV_UART1_VBUSP_CLK                                                                 | CLK_STATE_READY     | 125000000       | 0    | DEV_UART2_FCLK_CLK                                                                  | CLK_STATE_READY     | 48000000        | 3    | DEV_UART2_VBUSP_CLK                                                                 | CLK_STATE_READY     | 125000000       | 0    | DEV_UART3_FCLK_CLK                                                                  | CLK_STATE_READY     | 48000000        | 3    | DEV_UART3_VBUSP_CLK                                                                 | CLK_STATE_READY     | 125000000       | 0    | DEV_UART4_FCLK_CLK                                                                  | CLK_STATE_READY     | 48000000        | 3    | DEV_UART4_VBUSP_CLK                                                                 | CLK_STATE_READY     | 125000000       | 0    | DEV_UART5_FCLK_CLK                                                                  | CLK_STATE_READY     | 48000000        | 3    | DEV_UART5_VBUSP_CLK                                                                 | CLK_STATE_READY     | 125000000       | 0    | DEV_UART6_FCLK_CLK                                                                  | CLK_STATE_READY     | 48000000        | 3    | DEV_UART6_VBUSP_CLK                                                                 | CLK_STATE_READY     | 125000000       | 0    | DEV_UART7_FCLK_CLK                                                                  | CLK_STATE_READY     | 48000000        | 3    | DEV_UART7_VBUSP_CLK                                                                 | CLK_STATE_READY     | 125000000       | 0    | DEV_UART8_FCLK_CLK                                                                  | CLK_STATE_READY     | 48000000        | 3    | DEV_UART8_VBUSP_CLK                                                                 | CLK_STATE_READY     | 125000000       | 0    | DEV_UART9_FCLK_CLK                                                                  | CLK_STATE_READY     | 48000000        | 3    | DEV_UART9_VBUSP_CLK                                                                 | CLK_STATE_READY     | 125000000       | 1    | DEV_UFS0_UFSHCI_HCLK_CLK                                                            | CLK_STATE_READY     | 250000000       | 3    | DEV_UFS0_UFSHCI_MCLK_CLK                                                            | CLK_STATE_READY     | 24000000        | 4    | DEV_UFS0_UFSHCI_MCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                             | CLK_STATE_READY     | 24000000        | 5    | DEV_UFS0_UFSHCI_MCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                              | CLK_STATE_READY     | 0               | 6    | DEV_UFS0_UFSHCI_MCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_1_HSDIVOUT6_CLK                 | CLK_STATE_READY     | 19200000        | 7    | DEV_UFS0_UFSHCI_MCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT                             | CLK_STATE_READY     | 0               | 8    | DEV_UFS0_UFSHCI_MPHY_REFCLK                                                         | CLK_STATE_READY     | 0               | 23    | DEV_UFS0_UFSHCI_MPHY_TX_REF_SYMBOLCLK                                               | CLK_STATE_READY     | 0               | 24    | DEV_UFS0_UFSHCI_MPHY_M31_VCO_19P2M_CLK                                              | CLK_STATE_READY     | 0               | 25    | DEV_UFS0_UFSHCI_MPHY_M31_VCO_26M_CLK                                                | CLK_STATE_READY     | 0               | 0    | DEV_USB0_ACLK_CLK                                                                   | CLK_STATE_READY     | 500000000       | 1    | DEV_USB0_BUF_CLK                                                                    | CLK_STATE_READY     | 250000000       | 2    | DEV_USB0_CLK_LPM_CLK                                                                | CLK_STATE_READY     | 24000000        | 3    | DEV_USB0_PCLK_CLK                                                                   | CLK_STATE_READY     | 125000000       | 4    | DEV_USB0_PIPE_REFCLK                                                                | CLK_STATE_READY     | 0               | 5    | DEV_USB0_PIPE_REFCLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP3_LN3_REFCLK                      | CLK_STATE_READY     | 0               | 6    | DEV_USB0_PIPE_REFCLK_PARENT_WIZ16B8M4CT3_MAIN_4_IP3_LN3_REFCLK                      | CLK_STATE_READY     | 0               | 7    | DEV_USB0_PIPE_RXCLK                                                                 | CLK_STATE_READY     | 0               | 8    | DEV_USB0_PIPE_RXCLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP3_LN3_RXCLK                        | CLK_STATE_READY     | 0               | 9    | DEV_USB0_PIPE_RXCLK_PARENT_WIZ16B8M4CT3_MAIN_4_IP3_LN3_RXCLK                        | CLK_STATE_READY     | 0               | 10    | DEV_USB0_PIPE_RXFCLK                                                                | CLK_STATE_READY     | 0               | 11    | DEV_USB0_PIPE_RXFCLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP3_LN3_RXFCLK                      | CLK_STATE_READY     | 0               | 12    | DEV_USB0_PIPE_RXFCLK_PARENT_WIZ16B8M4CT3_MAIN_4_IP3_LN3_RXFCLK                      | CLK_STATE_READY     | 0               | 13    | DEV_USB0_PIPE_TXCLK                                                                 | CLK_STATE_READY     | 0               | 14    | DEV_USB0_PIPE_TXFCLK                                                                | CLK_STATE_READY     | 0               | 15    | DEV_USB0_PIPE_TXFCLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP3_LN3_TXFCLK                      | CLK_STATE_READY     | 0               | 16    | DEV_USB0_PIPE_TXFCLK_PARENT_WIZ16B8M4CT3_MAIN_4_IP3_LN3_TXFCLK                      | CLK_STATE_READY     | 0               | 17    | DEV_USB0_PIPE_TXMCLK                                                                | CLK_STATE_READY     | 0               | 18    | DEV_USB0_PIPE_TXMCLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP3_LN3_TXMCLK                      | CLK_STATE_READY     | 0               | 19    | DEV_USB0_PIPE_TXMCLK_PARENT_WIZ16B8M4CT3_MAIN_4_IP3_LN3_TXMCLK                      | CLK_STATE_READY     | 0               | 20    | DEV_USB0_USB2_APB_PCLK_CLK                                                          | CLK_STATE_READY     | 125000000       | 21    | DEV_USB0_USB2_REFCLOCK_CLK                                                          | CLK_STATE_READY     | 24000000        | 22    | DEV_USB0_USB2_REFCLOCK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                           | CLK_STATE_READY     | 24000000        | 23    | DEV_USB0_USB2_REFCLOCK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                            | CLK_STATE_READY     | 0               | 28    | DEV_USB0_USB2_TAP_TCK                                                               | CLK_STATE_READY     | 0               | 0    | DEV_VPAC0_LDC0_CLK_CLK                                                              | CLK_STATE_READY     | 720000000       | 1    | DEV_VPAC0_MAIN_CLK                                                                  | CLK_STATE_READY     | 720000000       | 2    | DEV_VPAC0_MAIN_CLK_PARENT_HSDIV1_16FFT_MAIN_25_HSDIVOUT1_CLK                        | CLK_STATE_READY     | 720000000       | 3    | DEV_VPAC0_MAIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK                         | CLK_STATE_READY     | 600000000       | 4    | DEV_VPAC0_MSC_CLK                                                                   | CLK_STATE_READY     | 720000000       | 5    | DEV_VPAC0_NF_CLK_CLK                                                                | CLK_STATE_READY     | 720000000       | 6    | DEV_VPAC0_PSIL_LEAF_CLK                                                             | CLK_STATE_READY     | 500000000       | 7    | DEV_VPAC0_VISS0_CLK_CLK                                                             | CLK_STATE_READY     | 720000000       | 0    | DEV_VPAC1_LDC0_CLK_CLK                                                              | CLK_STATE_READY     | 720000000       | 1    | DEV_VPAC1_MAIN_CLK                                                                  | CLK_STATE_READY     | 720000000       | 2    | DEV_VPAC1_MAIN_CLK_PARENT_HSDIV1_16FFT_MAIN_25_HSDIVOUT1_CLK                        | CLK_STATE_READY     | 720000000       | 3    | DEV_VPAC1_MAIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK                         | CLK_STATE_READY     | 600000000       | 4    | DEV_VPAC1_MSC_CLK                                                                   | CLK_STATE_READY     | 720000000       | 5    | DEV_VPAC1_NF_CLK_CLK                                                                | CLK_STATE_READY     | 720000000       | 6    | DEV_VPAC1_PSIL_LEAF_CLK                                                             | CLK_STATE_READY     | 500000000       | 7    | DEV_VPAC1_VISS0_CLK_CLK                                                             | CLK_STATE_READY     | 720000000       | 0    | DEV_VUSR_DUAL0_V0_CLK                                                               | CLK_STATE_READY     | 500000000       | 1    | DEV_VUSR_DUAL0_V0_RXFL_CLK                                                          | CLK_STATE_READY     | 0               | 2    | DEV_VUSR_DUAL0_V0_RXPM_CLK                                                          | CLK_STATE_READY     | 0               | 3    | DEV_VUSR_DUAL0_V0_TXFL_CLK                                                          | CLK_STATE_READY     | 0               | 4    | DEV_VUSR_DUAL0_V0_TXPM_CLK                                                          | CLK_STATE_READY     | 0               | 5    | DEV_VUSR_DUAL0_V1_CLK                                                               | CLK_STATE_READY     | 500000000       | 6    | DEV_VUSR_DUAL0_V1_RXFL_CLK                                                          | CLK_STATE_READY     | 0               | 7    | DEV_VUSR_DUAL0_V1_RXPM_CLK                                                          | CLK_STATE_READY     | 0               | 8    | DEV_VUSR_DUAL0_V1_TXFL_CLK                                                          | CLK_STATE_READY     | 0               | 9    | DEV_VUSR_DUAL0_V1_TXPM_CLK                                                          | CLK_STATE_READY     | 0               | 10    | DEV_VUSR_DUAL0_VUSRX_LN0_REFCLK                                                     | CLK_STATE_READY     | 0               | 11    | DEV_VUSR_DUAL0_VUSRX_LN0_RXCLK                                                      | CLK_STATE_READY     | 0               | 12    | DEV_VUSR_DUAL0_VUSRX_LN0_RXFCLK                                                     | CLK_STATE_READY     | 0               | 13    | DEV_VUSR_DUAL0_VUSRX_LN0_TXCLK                                                      | CLK_STATE_READY     | 0               | 14    | DEV_VUSR_DUAL0_VUSRX_LN0_TXFCLK                                                     | CLK_STATE_READY     | 0               | 15    | DEV_VUSR_DUAL0_VUSRX_LN0_TXMCLK                                                     | CLK_STATE_READY     | 0               | 16    | DEV_VUSR_DUAL0_VUSRX_LN1_REFCLK                                                     | CLK_STATE_READY     | 0               | 17    | DEV_VUSR_DUAL0_VUSRX_LN1_RXCLK                                                      | CLK_STATE_READY     | 0               | 18    | DEV_VUSR_DUAL0_VUSRX_LN1_RXFCLK                                                     | CLK_STATE_READY     | 0               | 19    | DEV_VUSR_DUAL0_VUSRX_LN1_TXCLK                                                      | CLK_STATE_READY     | 0               | 20    | DEV_VUSR_DUAL0_VUSRX_LN1_TXFCLK                                                     | CLK_STATE_READY     | 0               | 21    | DEV_VUSR_DUAL0_VUSRX_LN1_TXMCLK                                                     | CLK_STATE_READY     | 0               | 22    | DEV_VUSR_DUAL0_VUSRX_LN2_REFCLK                                                     | CLK_STATE_READY     | 0               | 23    | DEV_VUSR_DUAL0_VUSRX_LN2_RXCLK                                                      | CLK_STATE_READY     | 0               | 24    | DEV_VUSR_DUAL0_VUSRX_LN2_RXFCLK                                                     | CLK_STATE_READY     | 0               | 25    | DEV_VUSR_DUAL0_VUSRX_LN2_TXCLK                                                      | CLK_STATE_READY     | 0               | 26    | DEV_VUSR_DUAL0_VUSRX_LN2_TXFCLK                                                     | CLK_STATE_READY     | 0               | 27    | DEV_VUSR_DUAL0_VUSRX_LN2_TXMCLK                                                     | CLK_STATE_READY     | 0               | 28    | DEV_VUSR_DUAL0_VUSRX_LN3_REFCLK                                                     | CLK_STATE_READY     | 0               | 29    | DEV_VUSR_DUAL0_VUSRX_LN3_RXCLK                                                      | CLK_STATE_READY     | 0               | 30    | DEV_VUSR_DUAL0_VUSRX_LN3_RXFCLK                                                     | CLK_STATE_READY     | 0               | 31    | DEV_VUSR_DUAL0_VUSRX_LN3_TXCLK                                                      | CLK_STATE_READY     | 0               | 32    | DEV_VUSR_DUAL0_VUSRX_LN3_TXFCLK                                                     | CLK_STATE_READY     | 0               | 33    | DEV_VUSR_DUAL0_VUSRX_LN3_TXMCLK                                                     | CLK_STATE_READY     | 0               | 0    | DEV_WKUP_DDPA0_DDPA_CLK                                                             | CLK_STATE_READY     | 166666666       | 0    | DEV_WKUP_ESM0_CLK                                                                   | CLK_STATE_READY     | 166666666       | 0    | DEV_WKUP_GPIO0_MMR_CLK                                                              | CLK_STATE_READY     | 27777777        | 0    | DEV_WKUP_GPIO1_MMR_CLK                                                              | CLK_STATE_READY     | 27777777        | 0    | DEV_WKUP_GPIOMUX_INTRTR0_INTR_CLK                                                   | CLK_STATE_READY     | 166666666       | 0    | DEV_WKUP_HSM0_DAP_CLK                                                               | CLK_STATE_READY     | 1000000000      | 0    | DEV_WKUP_I2C0_CLK                                                                   | CLK_STATE_READY     | 166666666       | 1    | DEV_WKUP_I2C0_PISCL                                                                 | CLK_STATE_READY     | 0               | 2    | DEV_WKUP_I2C0_PISYS_CLK                                                             | CLK_STATE_READY     | 96000000        | 3    | DEV_WKUP_I2C0_PISYS_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT3_CLK                     | CLK_STATE_READY     | 96000000        | 4    | DEV_WKUP_I2C0_PISYS_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                              | CLK_STATE_READY     | 24000000        | 5    | DEV_WKUP_I2C0_PORSCL                                                                | CLK_STATE_READY     | 0               | 0    | DEV_WKUP_J7AM_WAKEUP_16FF0_PLL_CTRL_WKUP_CLK24_CLK                                  | CLK_STATE_READY     | 1000000000      | 1    | DEV_WKUP_J7AM_WAKEUP_16FF0_WKUP_RCOSC_12P5M_CLK                                     | CLK_STATE_READY     | 12500000        | 2    | DEV_WKUP_J7AM_WAKEUP_16FF0_WKUP_RCOSC_32K_CLK                                       | CLK_STATE_READY     | 32000           | 0    | DEV_WKUP_PORZ_SYNC0_CLK_12M_RC_CLK                                                  | CLK_STATE_READY     | 12500000        | 0    | DEV_WKUP_PSC0_CLK                                                                   | CLK_STATE_READY     | 166666666       | 1    | DEV_WKUP_PSC0_SLOW_CLK                                                              | CLK_STATE_READY     | 41666666        | 0    | DEV_WKUP_UART0_FCLK_CLK                                                             | CLK_STATE_READY     | 96000000        | 1    | DEV_WKUP_UART0_FCLK_CLK_PARENT_WKUP_USART_CLKSEL_OUT0                               | CLK_STATE_READY     | 96000000        | 2    | DEV_WKUP_UART0_FCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                              | CLK_STATE_READY     | 24000000        | 7    | DEV_WKUP_UART0_VBUSP_CLK                                                            | CLK_STATE_READY     | 166666666       | 0    | DEV_WKUP_VTM0_FIX_REF2_CLK                                                          | CLK_STATE_READY     | 12500000        | 1    | DEV_WKUP_VTM0_FIX_REF_CLK                                                           | CLK_STATE_READY     | 24000000        | 2    | DEV_WKUP_VTM0_VBUSP_CLK                                                             | CLK_STATE_READY     | 166666666       | ----------------------------------------------------------------------------------------------------------------------------------|

Kind regards,
Emanuele

1 month ago

0 Tanmay Patil 1 month ago

TI__Mastermind 27040 points

Hi Emanuele,

You won't see the external clock on k3conf dump as it is explicitly for internal clocks.

Are you getting any error from serdes or wiz module in linux boot log?

Regards,
Tanmay

0 Emanuele Ghidoli 1 month ago in reply to Tanmay Patil

Prodigy 245 points

Hi Tanmay,
I do not get errors about wiz/serdes module but nothing seems to change.

Currently, I am not able to communicate over SGMII (see https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1385154/am69-sgmii-not-working-with-dp83867is). I'm not sure if I have to use the external clock or the internal one is also good.

See this schematic for details: https://share.toradex.com/cte0k5i1caquyzq

Thank you and kind regards,
Emanuele

+1 Tanmay Patil 1 month ago in reply to Emanuele Ghidoli

TI__Mastermind 27040 points

Hi Emanuele,

Emanuele Ghidoli said:
I'm not sure if I have to use the external clock or the internal one is also good.

I suggest using internal clock first. Preferably, the default SDK clock configuration if that's possible. After that is working, you can switch over to external clocks.

Also, this issue could have the same solution as the ticket here : https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1385154/am69-sgmii-not-working-with-dp83867is

The schematic is not very helpful to me as I can't see where SERDES_1_REFCLK are sourced from. But it looks good.

Regards,
Tanmay

0 Emanuele Ghidoli 1 month ago in reply to Tanmay Patil

Prodigy 245 points

Hi Tanmay,
thank you.

I have the possibility to enable the external clock at runtime to verify if it is really used and I confirm that it is working.

Kind regards,
Emanuele

Processors

Processors forum

AM69: SERDES external reference clock selection not working