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Original question:

TDA4VM: Using TDA4's CPSW9G, connecting to phy chip, link fails.

TDA4VM: TDA4VM: Using TDA4's CPSW9G, connecting to phy chip, link up successfully but we can't ping other devices

Bruce Lee
Prodigy 26 points
Part Number: TDA4VM

Tool/software:

Hi TI,

Please help me check whether my configuration is correct.

Using TDA4's CPSW9G, connecting to phy chip, link up successfully but we can't ping other devices

SDK-10.00

serdes0-lane1: rtl9010(sgmii2)   

configure

1.uboot:

2.linux dts  k3-j721e-common-proc-board.dts

&serdes_ln_ctrl {
idle-states = <J721E_SERDES0_LANE0_QSGMII_LANE1>, <J721E_SERDES0_LANE1_QSGMII_LANE2>,
<J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>,
<J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>,
<J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>,
<J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>,
<J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>;
};

&serdes_wiz0 {
status = "okay";
};

&serdes0 {
status = "okay";
assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>, <&serdes0 CDNS_SIERRA_PLL_CMNLC1>;
assigned-clock-parents = <&wiz0_pll1_refclk>, <&wiz0_pll1_refclk>;
#address-cells = <1>;
#size-cells = <0>;

serdes0_sgmii_link: phy@0 {
reg = <0>;
cdns,num-lanes = <2>;
#phy-cells = <0>;
cdns,phy-type = <PHY_TYPE_SGMII>;
resets = <&serdes_wiz0 1>,<&serdes_wiz0 2>;
};
};

&cpsw0 {
status = "okay";
};

&cpsw0_port2 {
status = "okay";
phy-handle = <&cpsw9g_phy1>;
phy-mode = "sgmii";
mac-address = [00 00 00 00 00 00];
phys = <&cpsw0_phy_gmii_sel 2>,<&serdes0_sgmii_link>;
phy-names = "portmode", "serdes-phy";
};

&cpsw9g_mdio {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mdio0_pins_default>;
reset-post-delay-us = <120000>;
#address-cells = <1>;
#size-cells = <0>;

cpsw9g_phy1: ethernet-phy@1 {
reg = <1>;
compatible = "ethernet-phy-id001c.cb30","ethernet-phy-ieee802.3-c22";
fixed-link {
speed = <1000>;
full-duplex;
};
};
};

3.remove j7-main-r5f0_0-fw

4. ethtool eth0

5.boot log

0878.bootlog.txt
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[ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x411fd080]
[ 0.000000] Linux version 6.6.32-ti-gdb8871293143-dirty (bingo@ubuntu) (aarch64-oe-linux-gcc (GCC) 13.3.0, GNU ld (GNU Binutils) 2.42.0.20240620) #29 SMP PREEMPT Thu Nov 14 14:39:50 CST 2024
[ 0.000000] KASLR disabled due to lack of seed
[ 0.000000] Machine model: Texas Instruments J721e EVM
[ 0.000000] earlycon: ns16550a0 at MMIO32 0x0000000002800000 (options '')
[ 0.000000] printk: bootconsole [ns16550a0] enabled
[ 0.000000] efi: UEFI not found.
[ 0.000000] Reserved memory: created CMA memory pool at 0x00000008e0000000, size 512 MiB
[ 0.000000] OF: reserved mem: initialized node linux,cma, compatible id shared-dma-pool
[ 0.000000] OF: reserved mem: 0x00000008e0000000..0x00000008ffffffff (524288 KiB) map reusable linux,cma
[ 0.000000] OF: reserved mem: 0x000000009e800000..0x000000009fffffff (24576 KiB) nomap non-reusable optee@9e800000
[ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a0000000, size 1 MiB
[ 0.000000] OF: reserved mem: initialized node vision-apps-r5f-dma-memory@a0000000, compatible id shared-dma-pool
[ 0.000000] OF: reserved mem: 0x00000000a0000000..0x00000000a00fffff (1024 KiB) nomap non-reusable vision-apps-r5f-dma-memory@a0000000
[ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a0100000, size 15 MiB
[ 0.000000] OF: reserved mem: initialized node vision-apps-r5f-memory@a0100000, compatible id shared-dma-pool
[ 0.000000] OF: reserved mem: 0x00000000a0100000..0x00000000a0ffffff (15360 KiB) nomap non-reusable vision-apps-r5f-memory@a0100000
[ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a1000000, size 1 MiB
[ 0.000000] OF: reserved mem: initialized node vision-apps-r5f-dma-memory@a1000000, compatible id shared-dma-pool
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

  • 0
    TI__Guru 52410 points

    Hi,

    1) Please change the "phy-names" in CPSW ports as below.

    - phy-names = "portmode", "serdes-phy";
    + phy-names = "portmode", "serdes";

    2) Also, no need to add below serdes clock assignment under Serdes node.
    assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>, <&serdes0 CDNS_SIERRA_PLL_CMNLC1>;
    assigned-clock-parents = <&wiz0_pll1_refclk>, <&wiz0_pll1_refclk>;

    Can you please check with above suggested changes.

    Best Regards,
    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    Prodigy 26 points

    Hi ,

    After modification as you suggested, eth0 is gone.

  • 0 in reply to Bruce Lee
    TI__Guru 52410 points

    Hi,

    Can you please share the A72 log?

    Best Regards,
    Sudheer

  • 0 in reply to Bruce Lee
    TI__Guru 52410 points

    Hi,

    I could see SerDes driver failure form the A72 log, causing cpsw driver probe fail.

    Can you please share the log of below command after booting Linux.

    # k3conf dump clock 292

    Best Regards,
    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    Prodigy 26 points

    Hi,

    The result of executing this command is shown below.

  • 0 in reply to Bruce Lee
    TI__Guru 52410 points

    Hi,

    Can you please check with below clock configuration in Serdes node and check once.

    assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>, <&serdes0 CDNS_SIERRA_PLL_CMNLC1>;
    assigned-clock-parents = <&wiz0_pll1_refclk>, <&wiz0_pll1_refclk>;


    Also, share the log of below command after booting Linux.

    # k3conf dump clock 292

    Best Regards,
    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    Prodigy 26 points

    Hi,

    0640.log2.txt
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    [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x411fd080]
    [ 0.000000] Linux version 6.6.32-ti-gdb8871293143-dirty (bingo@ubuntu) (aarch64-oe-linux-gcc (GCC) 13.3.0, GNU ld (GNU Binutils) 2.42.0.20240620) #33 SMP PREEMPT Fri Nov 15 10:35:44 CST 2024
    [ 0.000000] KASLR disabled due to lack of seed
    [ 0.000000] Machine model: Texas Instruments J721e EVM
    [ 0.000000] earlycon: ns16550a0 at MMIO32 0x0000000002800000 (options '')
    [ 0.000000] printk: bootconsole [ns16550a0] enabled
    [ 0.000000] efi: UEFI not found.
    [ 0.000000] Reserved memory: created CMA memory pool at 0x00000008e0000000, size 512 MiB
    [ 0.000000] OF: reserved mem: initialized node linux,cma, compatible id shared-dma-pool
    [ 0.000000] OF: reserved mem: 0x00000008e0000000..0x00000008ffffffff (524288 KiB) map reusable linux,cma
    [ 0.000000] OF: reserved mem: 0x000000009e800000..0x000000009fffffff (24576 KiB) nomap non-reusable optee@9e800000
    [ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a0000000, size 1 MiB
    [ 0.000000] OF: reserved mem: initialized node vision-apps-r5f-dma-memory@a0000000, compatible id shared-dma-pool
    [ 0.000000] OF: reserved mem: 0x00000000a0000000..0x00000000a00fffff (1024 KiB) nomap non-reusable vision-apps-r5f-dma-memory@a0000000
    [ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a0100000, size 15 MiB
    [ 0.000000] OF: reserved mem: initialized node vision-apps-r5f-memory@a0100000, compatible id shared-dma-pool
    [ 0.000000] OF: reserved mem: 0x00000000a0100000..0x00000000a0ffffff (15360 KiB) nomap non-reusable vision-apps-r5f-memory@a0100000
    [ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a1000000, size 1 MiB
    [ 0.000000] OF: reserved mem: initialized node vision-apps-r5f-dma-memory@a1000000, compatible id shared-dma-pool
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

  • 0 in reply to Bruce Lee
    TI__Guru 52410 points

    Hi,

    Can you dump below register details, and share with us.

    # devmem2 0x0500e000
    # devmem2 0x05000404
    # devmem2 0x05000408
    # devmem2 0x0500040C
    # devmem2 0x05000480
    # devmem2 0x05000484
    # devmem2 0x05000488
    # devmem2 0x0500048C

    Best Regards,
    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    Prodigy 26 points

    Hi，

    Reading these registers results in the following.

    root@j721e-evm:~# devmem2 0x0500e000
    /dev/mem opened.
    Memory mapped at address 0xffffb3221000.
    Read at address 0x0500E000 (0xffffb3221000): 0x00003010
    root@j721e-evm:~# devmem2 0x05000404
    /dev/mem opened.
    Memory mapped at address 0xffffa8489000.
    Read at address 0x05000404 (0xffffa8489404): 0x00000000
    root@j721e-evm:~# devmem2 0x05000408
    /dev/mem opened.
    Memory mapped at address 0xffffb863d000.
    Read at address 0x05000408 (0xffffb863d408): 0x9A000000
    root@j721e-evm:~# devmem2 0x0500040C
    /dev/mem opened.
    Memory mapped at address 0xffff9afd3000.
    Read at address 0x0500040C (0xffff9afd340c): 0x92000000
    root@j721e-evm:~# devmem2 0x05000480
    /dev/mem opened.
    Memory mapped at address 0xffffb7a17000.
    Read at address 0x05000480 (0xffffb7a17480): 0x70800000
    root@j721e-evm:~# devmem2 0x05000484
    /dev/mem opened.
    Memory mapped at address 0xffffb9447000.
    Read at address 0x05000484 (0xffffb9447484): 0x00010002
    root@j721e-evm:~# devmem2 0x05000488
    /dev/mem opened.
    Memory mapped at address 0xffffa32aa000.
    Read at address 0x05000488 (0xffffa32aa488): 0x00000000
    root@j721e-evm:~# devmem2 0x0500048c
    /dev/mem opened.
    Memory mapped at address 0xffffbe74f000.
    Read at address 0x0500048C (0xffffbe74f48c): 0x00000002
    root@j721e-evm:~#
    root@j721e-evm:~#

  • 0 in reply to Bruce Lee
    TI__Guru 52410 points

    Hi,

    Bruce Lee said:
    root@j721e-evm:~# devmem2 0x0500e000
    /dev/mem opened.
    Memory mapped at address 0xffffb3221000.
    Read at address 0x0500E000 (0xffffb3221000): 0x00003010

    It seems like PLL is not locked.
    But, clock information of SerDes is same in TI EVM.

    Can you check whether "CONFIG_PHY_J721E_WIZ" enabled in your case.

    Best Regards,
    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    Prodigy 26 points

    Hi,

    I have checked the configuration file and CONFIG_PHY_J721E_WIZ has been enabled.

    board-support/ti-linux-kernel-6.6.32+git-ti/.config:

     

    Are there any other configurations to check? Please help to analyze it again,thank you.

  • 0 in reply to Bruce Lee
    TI__Guru 52410 points

    Hi,

    Bruce Lee said:
    Are there any other configurations to check? Please help to analyze it again,thank you.

    It would be fine, for SerDes configuration.

    If possible can you please check with SDK 9.2 once. Means while will check PLL locking on 10.0 SDK.

    Best Regards,
    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    Prodigy 26 points

    Hi Sudheer,

    I have seen a problem similar to the one I encountered, which SDK version was used and how was it resolved?

    TDA4VM: Using TDA4's CPSW9G, connecting to phy chip, link fails. - Processors forum - Processors - TI E2E support forums

     If possible can you please check with SDK 9.2 once. Means while will check PLL locking on 10.0 SDK.

    Using SDK 9.2 I need to make a lot of modifications that I will try.

  • 0 in reply to Bruce Lee
    Prodigy 26 points

    Hi,

    I see you have suggested using "serdes-phy", what is the difference between "serdes" and "serdes-phy"?

    And, Is there a problem that we do not use the REFCLK in serdes0?This is different from the TIEVM design.

  • 0 in reply to Bruce Lee
    TI__Guru 52410 points

    Hi,

    Bruce Lee said:
    I see you have suggested using "serdes-phy", what is the difference between "serdes" and "serdes-phy"?

    It is CPSW Driver specific, to configure SerDes, "serdes" is used in am65-cpsw-nuss driver.


    Can you please try to integrate the Cadence Sierra patch and check once.
    7776.0001-phy-cadence-Sierra-Add-Single-link-SGMII-PHY-configu.patch

    After integrating the patch, Build Linux and copy image to SD card root partition.


    Best Regards,
    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    Prodigy 26 points

    Hi Sudheer,

    I have solved this problem using the following configuration. Thank you!

    1.phy-names = "portmode", "serdes-phy";

    2.

    &wiz0_pll1_refclk {
	assigned-clocks = <&wiz0_pll1_refclk>;
	assigned-clock-parents = <&k3_clks 292 0>;
};

  • 0 in reply to Bruce Lee
    TI__Guru 52410 points

    Hi,

    Bruce Lee said:

    2.

    &wiz0_pll1_refclk {
	assigned-clocks = <&wiz0_pll1_refclk>;
	assigned-clock-parents = <&k3_clks 292 0>;
};

    Thanks for the update and I could see by default  "wiz0_pll1_refclk" was set with above configuration.

    Best Regards,
    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    Prodigy 26 points

    Hi,

    In addition to the k3-j721e-main.dtsi, k3-j721e-common-proc-board.dts also has the wiz0_pll1_refclk configuration.
    &wiz0_pll1_refclk {
	assigned-clocks = <&wiz0_pll1_refclk>;
	assigned-clock-parents = <&cmn_refclk1>;
};

     
  • 0 in reply to Bruce Lee
    TI__Guru 52410 points

    HI,

    Thank you for the details.
    Will be closing this thread.

    If you need any help, please create new thread.

    Best Regards,
    Sudheer