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EDMA3 Global configuration register (CCCFG) - Reset has wrong values

barry mohan
Intellectual 580 points

Other Parts Discussed in Thread: OMAPL138

Hi all,

Running OMAPL138 with CCS4.2 (Bios 5_41_07_24, DSPLINK 1_65_00_03, EDMA3_LLD_01_11_02_03).

When I stop emulator in main() before code is run and look at the register view for EDMACC0DSP I get

Register 1 : Peripheral Revision = 0x40019B00

Register 2 : CC Configuration = 0x00213344 (this is the same in a direct memory view at 0x01c00 00004)

The OMAPL138 TRM states the default for CCCFG register is

                                                     RESET VALUE                                                                                            Actual At Reset

31:26   Reserved                      x                                                                                                                     0h = OK

25         MP_EXIST                    0                                                                                                                    0h = OK

24         CHMAP_EXIST            0                                                                                                                    0h = OK

23:22   Reserved                      0                                                                                                                    0h = OK

21:20   NUM_REGN                 2h (equates to 4 regions - correct)                                                        2h = OK

19        Reserved                       x                                                                                                                    0h = OK

18:16  NUM_EVQUE               2h (equates to 2 EDMA3TC/Event Queues - correct)                   1h = WRONG - reserved value

15        Reserved                       x                                                                                                                     0h = OK

14:12   NUM_PAENTRY           3h (equates to 128 sets - correct)                                                          3h = correct

11        Reserved                        x                                                                                                                     0h = OK

10:8     NUM_INTCH               4h (equates to 32 interrupt channels - correct)                                3h = WRONG - reserved value

7          Reserved                        x                                                                                                                     0h = OK

6:4       NUM_QDAMCH            4h (equates to 8 QDMA channels  - correct)                                         4h = OK

3          Reserved                       x                                                                                                                      0h = OK

2:0      NUM_DMACH             5h (equates to 32 DMA channels - correct)                                       4h - WRONG - reserved value

Question is what could cause the reset values to take these values before any code is executed ?

Also the datasheet states these are read only registers, however when the EDMA_DVR_create() function is called and the globalConfig structure is passed it implies these fields are writeable  - is that the case ?

BR

Barry

 

 

 

 

 

 

 

  • 0
    TI__Guru 55797 points

    Barry,

    Those are errors in the documentation. Thanks for notifying us of this. I'll be sure to file this as a bug against the document.

    These regs are not writeable.

    Regards,

    Kyle

  • 0 in reply to kcastille
    Intellectual 580 points

    Hi Kyle

    Thanks for the prompt answer. Guess that raises a few more questions (as always ..:)

    Can I assume the  reset value I see for CCCFG (0x00213344) equate's to

                                         Reset

    MP_EXIST                 0h     =  OK

    CHMAP_EXIST        0h     = OK

    NUM_REGIONS      2h     = 4 regions = OK

    NUM_EVQUE          1h      = 2 event queues/TC's = (correction from 2h = 2 event queues)

    NUM_PAENTRY      3h      = 128 PaRAM entries = OK

    NUM_INTCH            3h     = 32 channels = (correction from 4h = 32 channels)

    NUM_QDMACH       4h     = 8 channels  = OK

    NUM_DMACH          4h     = 32 channels = (correction from 5h = 32 channels)

    And the comments in edma header files etc should still be correct for the API interfaces ?

    BR

    Barry

     

     

  • 0 in reply to barry mohan
    TI__Guru 55797 points

    Barry,

    Yes, that looks correct for EDMACC0.  (You can cross check this against the OMAPL138 TRM. Note that EDMA CC1 only has one queue).

    I didn't double check the EDMA LLD, but since that code is fairly mature on OMAPL138, I expect it to be accurate.

    Regards
    Kyle

     

     

  • 0 in reply to kcastille
    Intellectual 580 points

    Cheers for that Kyle..:)

    BR

    Barry