AM3354: AM3354 Custom SoM – Schematic Check before PCB Design

Hello Marius

Thank you for the review request.

Can you please confirm if you are working with any of the TI sales or support team.

Can you confirm if you shared the schematics in PDF.

Regards,

Sreenivasa

Hello Sreenivasa,

thank you for your response.

We were initially directed to the TI E2E forum by customer support, so I am following up here as well.

I have attached the schematics in PDF format for your review.

Thank you very much for your support.

Best regards,

Marius
MRTB.pdf

Hello Marius

Thank you.

Are you able to confirm you are not working with TI field teams - sales or Support team.

The schematic you shared does not show values. Please review and update.

Regards,

Sreenivasa

6237.MRTB.pdf

Hello Sreenivasa,

thank you for your response.

I apologize for the delayed reply, I was not able to access the forum yesterday.

I can confirm that I am currently not working with any TI field, sales, or support teams.

I have now updated the schematic to include all component values and attached the revised PDF for your review.

Thank you very much for your support.

Best regards,

Marius

Hello Marius

Thank you.

Let me review the inputs and comeback.

Regards,

Sreenivasa

Hello Marius

We have an excel and a detailed PDF checklist. Can you do a quick check or confirm you have had reviewed the checklist.

e2e.ti.com/.../faq-am625-am623-am620-q1-am62ax-am62px-am62d-q1-am62l-am64x-am243x-alv-am335x-design-recommendations-custom-board-hardware-design---schematics-review-checklists

AM335x 

PDF

AM335x Schematic Checklist

https://www.ti.com/lit/pdf/sprabn2

Prevision revision with RTC information

2117.sprabn2.pdf

AM335x Hardware Design Guide

https://www.ti.com/lit/pdf/sprabu5

Excel (includes schematic illustrations for reference)

AM3359, AM3358, AM3357, AM3356, AM3354, AM3352, AM3351_Schematic_Checklist & Design_Guidelines_01282026_Rev1.xlsx

Regards,

Sreenivasa

1067.MRTB.pdf

Hello Sreenivasa,

thank you again for the provided documents and guidance.

I have now carefully reviewed the checklist and design guidelines and made several updates and fixes to my schematic accordingly.

My main goal with this design is to create a flexible System-on-Module that exposes most signals to a carrier board, while still keeping the core system (power, DDR, etc.) stable and functional.

From your perspective, does this approach seem reasonable for a general-purpose SoM design? In particular, I would appreciate your opinion on whether the current design covers the essential requirements, while still allowing maximum flexibility for future carrier boards.

Please let me know if there are any major concerns or areas that should be reconsidered before proceeding further.

Thank you very much for your support.

Best regards,

Marius

Hello Marius

Thank you.

Good to hear the checklist helped and you could make improvements.

Let me review the inputs.

Regards,

Sreenivasa

Hello Marius

Please review the below FAQ and add the recommended capacitors

(+) [FAQ] AM3351 , AM3352 , AM3354 , AM3356 , AM3357 , AM3358 , AM3359 Custom board design – E2E, FAQ references and design guidelines for reference during custom board design - Processors forum - Processors - TI E2E support forums

Inputs related to PDN - capacitors recommendations for Processor and DDR supply rails.

Inputs related to PDN - capacitors recommendations for Processor supply rails.

Regards,

Sreenivasa

Hello Marius

can you help me confirm if the clock generation circuit is planned to be placed on a separate board?

Regards,

Sreenivasa

5504.MRTB.pdf 

Hello Sreenivasa,

thank you for your feedback.

Apologies for the delayed response.

We have updated the schematic based on the checklist, and the latest version with all component values is attached as a PDF.

In the updated schematic, the main system clock (OSC0, 24 MHz) is implemented directly on the SoM using an external oscillator. In addition, a 32.768 kHz oscillator is implemented on OSC1 to support RTC functionality.

These changes are reflected in the attached schematic.

Please let us know if you identify any critical issues or if any adjustments are recommended before proceeding to PCB layout.

Thank you for your support.

Best regards,
Tizian

Hi All, 

Good to note you have been able to make updates based on the checklist.

Let me review and comeback.

Regards,

Sreenivasa

Hi All, 

As i review the schematics, can you please add a E2E query with only the PMIC - TPS65218 schematic review in the title for the PMIC team to review parallelly.

Please share the thread link in this E2E.

Regards,

Sreenivasa

Hi All, 

I see most of the processor connections going to a carrier board.

Please note the review efficiency reduces without the carrier board information.

Regards,

Sreenivasa

Hello Sreenivasa,

thank you for your feedback.

As requested, we have created a separate E2E thread for the PMIC (TPS65218) schematic review. You can find it here:
https://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1633309/tps65218-tps65218d0-pmic-schematic-review-am3354-custom-som

Regarding the carrier board: at this stage, no specific carrier board has been designed yet. The current focus is to ensure that the SoM itself is fully functional and stable (power, clock, DDR, etc.).

Most processor signals are therefore routed to the SODIMM connector to allow flexibility for future carrier board implementations.

We understand that the absence of a defined carrier board may reduce review efficiency, but we would appreciate your feedback on whether the current SoM design covers the essential requirements for reliable operation.

Thank you for your support.

Best regards,
Marius

Hello Marius

Thank you and understand,

Not sure if you have a chance to review the below section of the schematic checklist. 

We expect the resistor to be placed close to the processor pin. I do not see this added.

Peripheral Clocking

Several peripheral clocks are required to have RXACTIVE bit set as input because they are used to retime read data returning to the device. We also recommend a series resistor located as close to the device as possible to reduce reflections on the clock. For the following peripherals, the associated signals should have a series resistor (33 Ω) in line as close to the processor as possible when used in master mode (AM335x drives the clock).

• GPMC - GPMC_CLK • MMC - MMC_CLK • SPI - SPI_CLK • McASP (all clocks and frame syncs)

Regards,

Sreenivasa 

Hello Marius,

Regarding the PMIC outputs

The recommendation is to add a series resistor or a copper jumper created that can be cut to isolate the supplies for testing during initial board bring-up.

Regards,

Sreenivasa

Hello Marius,

The reset signal from SOC connects to the DDR memory and i do not see a pullup.

Please review the use case and add a pullup.

Regards,

Sreenivasa

Hello Marius,

Please revisit the DDR supply, reference generation and addition of bulk caps.

Data sheet reference

7.7.2.3 DDR3 and DDR3L Routing Guidelines including capacitors 

Regards,

Sreenivasa

Hello Marius,

Inputs related to reset implementation:

Leave the reserved pins unconnected.

A buffer may be required to be added
Inputs related to cold and warm reset

www.ti.com/.../spruh73q.pdf

8.1.7 Reset Management
8.1.7.1 Overview

Regards,

Sreenivasa

Hello Marius,

Inputs related to VPP

Regards,

Sreenivasa 

Hello Marius,

Inputs related to Ethernet MAC interface 

Add series resistor provision for the TDx signals
While no series resistors are required for MII/RMII/RGMII, it is prudent include zero-Ω stuff options for the TX and RX lines. Ideally, these option resistors should be as small as possible (0402 or smaller
recommended) and should be placed as close to the transmitter as possible.

MDIO needs a pullup - can be near EPHY

MDC needs a pulldown - EPHY dependent

Regards,

Sreenivasa

Hello Marius,

The voltage ratings for the caps have not been enabled

Recommend using cap with voltage rating > x2 times the worst case applied voltage.

Regards,

Sreenivasa

Hello Marius,

Thank you for adding the clock on the processor board.

Add provision for a series resistor 22R at the output of oscillator for control of possible signal reflections

Add a bulk cap 1uF for the oscillator supply pin

Regards,

Sreenivasa

Hello Marius,

Regarding the USB interface, the recommendation is to follow the checklist for the connections.

Please take nor of the differential trace impedance and signal discontinuities. Minimize addition of series resistor or TP

Regards,

Sreenivasa

Hello Marius,

Inputs related to MMC0 interface 

Add a series resistor near to the MMC0_CLK pin 

Add provision for pullups on the carrier board.

Regards,

Sfeenivasa

Hello Marius,

Inputs regarding the supply rails - bulk cap, decoupling cap and ferrites

Please follow the data sheet for the capacitor values and numbers

Please follow the EVM schematics (multiple, refer FAQ_ for the ferrite filters.

Regards,

Sreenivasa

Hello Marius,

ADC inputs are not fail-safe 

Terminate unused ADCs

Refer to the errata for mapping the LCD signals.

Regards,

Sreenivasa

Hello Marius,

Inputs related to RTC mode and LDO configuration

AM335x Schematic Checklist

https://www.ti.com/lit/pdf/sprabn2

Prevision revision with RTC information

2117.sprabn2.pdf

Since this is a SOM and likely can have multiple use cases, the recommendation is to follow the Table in the above checklist.

Regards,

Sreenivasa

Hello Marius,

Some general notes on the SOM design:

Our review timeline is typically 2.5-5 weeks.

To enable you to continue with the layout, i have done my best to review and add my comments.

As i review i wanted to suggest that you review the checklist and the FAQs i referenced one more time and make any updates that you may find along with any inputs you may receive from the PMIC team.

There are multiple EVMs available. Please review the EVM schematics and ensure you follow the supply pin connection, ferrites and capacitors.

Regards,

Sreenivasa

3225.MRTB.pdf

Hello Marius,

I attached the schematics with all the comments marked.

Rgerads,

Sreenivasa

Hello Marius,

You mentioned that the current focus is on the SOM board.

Any thoughts on the plan to test the SOM board. The reset inputs and many of the analog inputs including ADC and the digital inputs are open and are expected to be driven by the carrier board.

Regards,

Sreenivasa 

Hello Marius,

FYI, i have done my best to support the schematic review at the shortest possible timeline.

This is not something we always support.

Our typical timeline is 2.5 to 4 weeks depending on the complexity.

On the E2E we support specific section review.

I would suggest you make the updates added below, make any updates provided by the PMIC team and also based on rereview of the checklist.

In case you are not sure on the carrier board connection or architecture, i would suggest that you provide provision to connect the IO supply rails individually and provide provision to connect either 1.8V or 3.3V supply.

Regards,

Sreenivasa

Hello Marius,

Please refer below EVM schematic for the separate connection of VDDSHVx  IO supply

The recommendation is to follow the approach for the SOM.

Regards,

Sreenivasa

Hello Marius,

Most of the processor IOs are not fail-safe.

The recommendation is to connect the IO supplies of the attached device and the processor Supply voltage for the dual-voltage I/O domain to the same supply source.

Regards,

Sreenivasa

Hello Marius,

I asked the below queries to our device expert and received the below reply. Please review:

Q1. Can you please comment on the USB connections. Is it OK to implement the USB interface on the carrier board and simply connect the USB signals to the SOM board. Do you have some concerns on the impedance.

Q2. Fail-safe operation

Most of the SOC IOs are not fail-safe. Would there be a concern of residual voltage in case external inputs are applied before the SOM supplies ramp.

I looked at the PMIC and do not see the PMIC supporting residual voltage detection.

Any thoughts on the processor behavior in case there is violation of fail-safe operation.

The USB signals should be routed per the USB specification.  The finger connector approach they appear to be using is not a USB-IF certified connector that provides a shielded 90-ohm differential signal path.  Therefore, they are likely to have signal integrity issues.  We do not recommend routing the USB signals though a connector that is not certified by USB-IF.

 How do they ensure circuits on the carrier board connected to AM335x pins are not powered before the respective AM335x IO power rails?  We do not allow any potential to be applied to AM335x pins before the respective IO power rail is valid.  This is a requirement defined in the Absolute Maximum Ratings table.

Regards,

Sreenivasa

Hello Marius,

Refer below inputs from our power expert and let me know your thoughts.

Do you know if this SOM requires supporting RTC-only low power mode? and when is the customer planning to release the SOM to production?

I asked because, depending on their answer we might want to recommend them to use the same power solution that was used in the latest beagle board (https://www.ti.com/tool/BEAGL-BONE-GRN-ECO).

Regards,

Sreenivasa

1538.MRTB.pdf

Hello Sreenivasa,

thank you very much for your feedback and for checking with your power expert – we really appreciate your support! 

Regarding your questions:

We do not require RTC-only low power mode for this SOM. Our target use case does not rely on ultra-low-power standby operation, so we do not plan to implement or optimize for RTC-only mode.

In terms of production timeline, this design is still in an early stage, and we have sufficient time before any production release. This gives us flexibility to carefully evaluate different design options.

We have reviewed your comments and implemented the recommended updates where applicable. An updated schematic is attached for your review.

Regarding the power architecture, we understand the advantages of the BeagleBone Green Eco solution and will definitely review it in more detail as a strong reference . At the same time, we are also exploring a simpler or alternative PMIC approach and remain open to adjustments based on your and the team’s feedback.

Thank you again for your time and guidance – it really helps us move forward in the right direction 

Best regards,
Marius

Hello Marius,

Thank you for the note.

I see you made a number of changes.

regarding the cap, i see a note that says all caps are rated for 10V.

For the caps connected to 5V, you may want to consider 16V.

Regarding the updated schematics, please share the schematics after you complete the power architecture analysis and make updates.

We typically do not review multiple revisions. I can do a quick review of the updated schematics.

Regards,

Sreenivasa

Hello Sreenivasa,

I hope you are doing well 

We wanted to share a quick update on our progress.

We have implemented the recommended changes from the PMIC team and updated the schematic accordingly. At the moment, we are continuing to review and refine the power architecture, especially with regard to sequencing and overall robustness.

We are also evaluating potential improvements and alternative approaches to further simplify and optimize the design.

Once we have finalized these aspects, we will share an updated version for your review.

Thank you again for your support!

Best regards,
Marius

Hello Marius,

Thank you for the note and good to hear the progress.

Regards,

Sreenivasa

3348.MRTB.pdf

Hello Sreenivasa,

we have incorporated the feedback from the PMIC team and completed our power architecture review.

The updated schematic is attached. We would appreciate a quick check for any major concerns.

Thank you again for your support.

Best regards,
Marius

Hello Marius,

Thank you.

Let me check and comeback.

Regards,

Sreenivasa

Hello Sreenivasa,

I hope you are doing well.

I just wanted to check in and see if there are any updates on your side regarding our project.

No rush at all, we just wanted to stay in touch and see how things are progressing.

Thank you again for your support.

Best regards,
Marius

Hello Marius

Thank you for checking.

I will have a look during the second half of the week.

In case you have an updated schematic, please share.

Regards,

Sreenivasa

Hello Sreenivasa,

thank you for the update, I really appreciate it.

At the moment, we do not have any further updates and are still working with the latest version we shared.

We look forward to your feedback.

Best regards,
Marius

Hello Marius

Thank you for the note.

Regards,

Sreenivasa

Hello Marius

Please review below comments:

All the processor signals are connected to the connector (gold fingers) and do not see any ground shueld between signals
Not sure on the effect on the board performance
Did you have some thoughts or experience designing similar boards
The recommendation is to add ground shield between signals

Regards,

Sreenivasa

8475.MRTB.pdf

Hello Sreenivasa,

thank you for your comments.

Just to clarify, we are using a DDR4 SO-DIMM style connector rather than a generic “gold finger” edge connection. Our intention with the pinout is to provide adjacent ground references for all signals.

For less critical signals, we currently use a GND–Signal–Signal–GND spacing, while for more sensitive and higher-speed signals we use tighter grounding patterns such as GND–Signal–GND–Signal, and GND–pair–GND for differential pairs.

We understand your point regarding signal integrity and shielding, and we will review the connector pinout again to further improve the grounding strategy for high-speed signals.

Regarding high-speed interfaces, we are aware that the connector is not USB-IF certified, and we will take this into consideration during further design and validation.

As always, the latest version of the schematic is attached.

Thank you again for your support.

Best regards,
Marius

Hello Marius

Thank you.

Not sue if the ground is represented in the schematics or taken care in the layout.

Please refer page 25

/cfs-file/__key/communityserver-discussions-components-files/791/2474.schematic.pdf

Do you have an illustration on how the grounding will be implemented.

I have a few observation that i will share 

Regards,

Sreenivasa