DDRSLRATE on the TMS320C6457

Titus, Senthil,

The DDR2 Controller User's Guide sprugk5d shows the DDRSLRATE bit-field as being R/W in the DMCCTL register.

But if the bit truly reflects the state of the DDRSLRATE pin, any write to that bit should always read back whatever the state of the pin is. This effectively makes it a Read-only bit and not R/W.

One question we have is whether that bit is truly R/W or Read-only?

Another question is whether a value written to that bit (if R/W) will change the slew rate used by the DDR2 Memory Controller, or is on the pin's value used regardless of the state of the DMCCTL.DDRSLRATE bit field?

Regards,
RandyP

Jason,

The DDR slew rate is not a characterized value.  The value can be adjusted due to lengths of traces and to manage radiated emissions. IBIS modeling can be used to see the effect of different settings.

Tom