AM3352: DDR issue

Hi Stephen,

I was wrong in my question!

Thank you both. With those changes the data changing appears to be less random, however I'm still seeing "all zeros" and "data changing everywhere".

I've attached a 5 second animated GIF to show what I'm seeing.

Is there somethings else that's just slightly off?

AM335x_DDR_register_calc_tool - micron.xls

3718.RatioSeed_AM335x_boards.xls

Can you try with these timings: (Use table in my post below)

Thank you, I have tried those timings.

Please see attached GIF for behaviour after running the slave ratio search program. It seems to be similar to before?

So this should be the correct one:

7384.AM335x_DDR_register_calc_tool - micron.xls

Unfortunately I still see the same problem.

Thank you for pointing that out though, Dwarakesh - I didn't even notice the other sheets!

The ALLOPP_DDR3_SDRAM_TIMING are now almost identical to Rev A, in fact they actually work on the Rev A board but I have to use different _PHY_ constants:

# This works for Rev A...
#define  CMD_PHY_CTRL_SLAVE_RATIO       0x80
#define  CMD_PHY_INVERT_CLKOUT          0x0

#define  DATA_PHY_RD_DQS_SLAVE_RATIO    0x39
#define  DATA_PHY_FIFO_WE_SLAVE_RATIO   0x97 //RD DQS GATE
#define  DATA_PHY_WR_DQS_SLAVE_RATIO    0x41
#define  DATA_PHY_WR_DATA_SLAVE_RATIO   0x7B  //WRITE DATA

#define ALLOPP_DDR3_READ_LATENCY    0x07        //RD_Latency = (CL + 2) - 1

#define ALLOPP_DDR3_SDRAM_TIMING1   0x0AAAD4DB
#define ALLOPP_DDR3_SDRAM_TIMING2   0x266B7FDA
#define ALLOPP_DDR3_SDRAM_TIMING3   0x501F867F

#define ALLOPP_DDR3_SDRAM_CONFIG    0x61C05332

I can't seem to get the slave ratio program to return anything but zeros for Rev B, even if I try the Rev A seed values. In fact if I do that then the memory browser just shows all zeros as well.

So using what we've discussed...

# This is what I have so far for Rev B...
#define  CMD_PHY_CTRL_SLAVE_RATIO       0x100
#define  CMD_PHY_INVERT_CLKOUT          0x1

#define  DATA_PHY_RD_DQS_SLAVE_RATIO    0x40
#define  DATA_PHY_FIFO_WE_SLAVE_RATIO   0xF4 //RD DQS GATE
#define  DATA_PHY_WR_DQS_SLAVE_RATIO    0x7C
#define  DATA_PHY_WR_DATA_SLAVE_RATIO   0x80  //WRITE DATA

#define ALLOPP_DDR3_READ_LATENCY    0x07        //RD_Latency = (CL + 2) - 1

#define ALLOPP_DDR3_SDRAM_TIMING1   0x0AAAD4DB
#define ALLOPP_DDR3_SDRAM_TIMING2   0x266B7FDA
#define ALLOPP_DDR3_SDRAM_TIMING3   0x501F843F

#define ALLOPP_DDR3_SDRAM_CONFIG    0x61C05332

With the above I still see the same "data changing" in memory browser...

One thing that I think is strange is that the seed values from the RatioSeed spreadsheet don't work and aren't used for Rev A, I would've thought they'd be the same between the two boards if layout hadn't changed? When I originally did the bringup for Rev A I just used the BeagleBone Black seed values from the tutorial and they worked.

Now when I'm trying Rev B, I've tried both the seed values from Rev A and also the ones provided by the RatioSeed spreadsheet. If I use Rev A seeds values I see all zeros in the memory browser, if I use the RatioSeed spreadsheet values then I see the data changing as per the GIFs previously posted.

I'm at a loss now. Could this be an issue with impedance matching on Rev B? Or am I missing something?

Hi,

We all did that mistake. I was referring to the wrong sheet yesterday :) . Biser is the right person to answer, since he is an expert in hardware, but from what I have very limited knowledge, the Seed Ratio spread sheet should be filled with the trace length in your actual layout. If the layout has changed between revA and revB, you might need to provide the correct changed values and by trying out various other Boards' may not help.

Hi James, thank you for the suggestion however it appears that supervisor mode is activated correctly without the need to run a script.

I've uploaded a complete screencast of the CCS session below (5MB animated GIF) in case you spot anything else? In the screencast I use the seed values from the SeedRatio spreadsheet, although I see the same behaviour if I use the seed values from rev A. I also see the same behaviour if I use the timing registers from rev A or, as in the screencast, the timing registers provided by Biser. I've also tried all combinations of the above to the same effect.

When I follow the exact same process for a rev A board, the levelling works correctly (with rev A seed values entered into GEL file and console) either with the rev A timing registers or with the timing registers provided by Biser.

Stephen, can you try increasing your READ_LATENCY by 1.  If it still doesn't work, try by 2

Regards,

James

Paul, that shouldn't be an issue.  We support a DDR clock frequency of 400MHz (ie, 800M T/s).  The minimum speed grade that we support for 400MHz operation is DDR-1600, which both of your devices meet.

Any results of the read_latency tests?

Regards,

James