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AM3352: AM3352 DDR issue

Daniel Cheng1
Mastermind 6355 points
Part Number: AM3352

Hi Expert

We got trouble with running DDR3 at clock 400MHz in our DUT that sometimes the system crashed at 303MHz.

We tried to modify the DDR time parameter with the EMIF configuration Tool and still did not work well.

We need your help to check the attached file which we might have the wrong setting or do you have any other common to solve this issue.

Thanks

Daniel

AM335x_EMIF_Configuration_Tool_v3_V73CBG04808RDJ11_shannon.xlsx

3162.board.c
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#define V73CBG04808RDJ11_CLK 303
#define V73CBG04808RDJ11_EMIF_READ_LATENCY 0x00100208
#define V73CBG04808RDJ11_EMIF_TIM1 0x888A39B
#define V73CBG04808RDJ11_EMIF_TIM2 0x246D7FDA
#define V73CBG04808RDJ11_EMIF_TIM3 0x50FFE6AF
#define V73CBG04808RDJ11_EMIF_SDCFG 0x61A053B2
#define V73CBG04808RDJ11_EMIF_SDREF 0x0000093B
#define V73CBG04808RDJ11_ZQ_CFG 0x50074BE1
#define V73CBG04808RDJ11_RATIO 0x100
#define V73CBG04808RDJ11_INVERT_CLKOUT 0x1
#define V73CBG04808RDJ11_RD_DQS 0x3C
#define V73CBG04808RDJ11_WR_DQS 0xC4
#define V73CBG04808RDJ11_PHY_FIFO_WE 0x118
#define V73CBG04808RDJ11_PHY_WR_DATA 0xFB
#define V73CBG04808RDJ11_IOCTRL_VALUE 0x0000018B
static const struct ddr_data ddr3_pg5902b_data = {
.datardsratio0 = V73CBG04808RDJ11_RD_DQS,
.datawdsratio0 = V73CBG04808RDJ11_WR_DQS,
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
memtester.txt
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login as: root
root@10.0.50.100's password:
# cd /jffs2/
# date && ./memtester 900M
Thu Jul 14 07:45:55 UTC 2022
memtester version 4.3.0 (32-bit)
Copyright (C) 2001-2012 Charles Cazabon.
Licensed under the GNU General Public License version 2 (only).
pagesize is 4096
pagesizemask is 0xfffff000
want 900MB (943718400 bytes)
got 900MB (943718400 bytes), trying mlock ...locked.
Loop 1:
Stuck Address : testing 11FAILURE: possible bad address line at offset 0x0f586000.
Skipping to next test...
Random Value : ok
Compare XOR : ok
Compare SUB : ok
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
SW_Leveling_303M.txt
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AM335x DDR3 Software Leveling -- Version: Beta 3.0
-- Copyright: Texas Instruments China Local Team
*************************** Program Start********************************
Please input the AM335x EMIF Timing Configuration:
-- AM335x Default EMIF Timing configuration (for StarterKit EVM) --
DDR3_EMIF_SDRAM_TIM_1 : 0x0888A39B
DDR3_EMIF_SDRAM_TIM_2 : 0x26337FDA
DDR3_EMIF_SDRAM_TIM_3 : 0x501F830F
DDR3_EMIF_SDRAM_CONFIG : 0x61C04AB2
Your choice: 1. Use the default one; 2. Input your own one.
Please Choose The DDR3 Frequency: 1. 303MHz; 2. 400MHz.
DDR3 Frequency is Set at 303MHz!
Please input your DDR3_EMIF_SDRAM_TIM_1 conifguration (in Hex) :
0888A39B
Please input your DDR3_EMIF_SDRAM_TIM_2 conifguration (in Hex) :
246D7FDA
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
SW_Leveling_400M.txt
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AM335x DDR3 Software Leveling -- Version: Beta 3.0
-- Copyright: Texas Instruments China Local Team
*************************** Program Start********************************
Please input the AM335x EMIF Timing Configuration:
-- AM335x Default EMIF Timing configuration (for StarterKit EVM) --
DDR3_EMIF_SDRAM_TIM_1 : 0x0888A39B
DDR3_EMIF_SDRAM_TIM_2 : 0x26337FDA
DDR3_EMIF_SDRAM_TIM_3 : 0x501F830F
DDR3_EMIF_SDRAM_CONFIG : 0x61C04AB2
Your choice: 1. Use the default one; 2. Input your own one.
Please Choose The DDR3 Frequency: 1. 303MHz; 2. 400MHz.
DDR3 Frequency is Set at 400MHz!
Please input your DDR3_EMIF_SDRAM_TIM_1 conifguration (in Hex) :
0AAAD4DB
Please input your DDR3_EMIF_SDRAM_TIM_2 conifguration (in Hex) :
248F7FDA
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

  • 0
    TI__Guru* 80020 points

    What is your DDR topology?  Do you have 1 DDR device or 2 devices in fly-by topology?  If you have just one device, it is not necessary to run the software leveling algorithm.

    Regards,

    James

  • 0 in reply to JJD
    Mastermind 6355 points

    Hi James

    Fly-By-topology

     

    Thanks

    Daniel

  • 0 in reply to Daniel Cheng1
    TI__Guru* 80020 points

    Can you send the datasheet (or part number if datasheet is available on the web)?  

    It appears that the timing registers that you input in the the software leveling algorithm does not match what is in your xls.  The leveling algorithm shows this:

    Please input your DDR3_EMIF_SDRAM_TIM_1 conifguration (in Hex) :
    0888A39B
    Please input your DDR3_EMIF_SDRAM_TIM_2 conifguration (in Hex) :
    246D7FDA
    Please input your DDR3_EMIF_SDRAM_TIM_3 conifguration (in Hex) :
    50FFE6AF
    Please input your DDR3_EMIF_SDRAM_CONFIG conifguration (in Hex) :
    61A053B2
    Your input EMIF Timing configuration --
    DDR3_EMIF_SDRAM_TIM_1 : 0x888A39B
    DDR3_EMIF_SDRAM_TIM_2 : 0x246D7FDA
    DDR3_EMIF_SDRAM_TIM_3 : 0x50FFE6AF
    DDR3_EMIF_SDRAM_CONFIG : 0x61A053B2

    but your spreadsheet shows this:

    SDRAM_TIM_1 0x4C000018 0x0AAAD4DB
    SDRAM_TIM_2 0x4C000020 0x248F7FDA
    SDRAM_TIM_3 0x4C000028 0x50FFE8BF
    SDRAM_CONFIG 0x4C000008 0x61A053B2

    This may be one reason you are getting poor results

    Regards,

    James

  • 0
    Prodigy 50 points

    Hi James,

    We have done twice with software leveling,

    First with 400MHz, according to spreadsheet, I filled,

    DDR3_EMIF_SDRAM_TIM_1 :         0xAAAD4DB
    DDR3_EMIF_SDRAM_TIM_2 :         0x248F7FDA
    DDR3_EMIF_SDRAM_TIM_3 :         0x50FFE8BF
    DDR3_EMIF_SDRAM_CONFIG :        0x61A053B2

    But it replied 0 at all.

    Second time with 303MHz, I changed frequency to 303 in spreadsheet, then filled,

    DDR3_EMIF_SDRAM_TIM_1 :         0x888A39B
    DDR3_EMIF_SDRAM_TIM_2 :         0x246D7FDA
    DDR3_EMIF_SDRAM_TIM_3 :         0x50FFE6AF
    DDR3_EMIF_SDRAM_CONFIG :        0x61A053B2

    It have found optimal value, but it can't pass memtester and system crashing randomly.

    Jimmy

  • 0 in reply to Jimmy Liao
    Mastermind 6355 points

    Hi James

    7331.DDR3.pdfV73CBG04808RDJJ11I.PDF

    Attached files are DDR Datasheet and Schematic

    Thanks

    Daniel

  • 0 in reply to Daniel Cheng1
    TI__Guru* 80020 points

    Hi Daniel, it looks like everything you are showing me is correct so far.  

    -For the trace length values you have plugged into the tool, is the clock to byte 0 2.22in, and byte 1 61in?  Double check that those are not swapped

    -Have you followed all the DDR layout guidelines in the AM335x datasheet, especially length matching guidelines?

    -at 303MHz, do multiple boards have similar results for the leveling algorithm?

    -for the 303MHz case, can you dump the EMIF registers in u-boot.  Addresses 0x4c000000-0x4c0000E8

    -can you successfully perform single memory write and reads in u-boot?

    -do you ever have a problem booting, or do you only see a problem when running memtester?

    -for the 303MHz memtester run, it appears that byte1 is faulty.  Is this consistent across multiple memtester runs and multiple boards?

    Regards,

    James

  • 0 in reply to JJD
    Mastermind 6355 points

    Hi James

    1.

    I test 3 boards so far, the result as below,

    #1

    ***************************************************************

    DATA_PHY_RD_DQS_SLAVE_RATIO is :0x3C

    DATA_PHY_FIFO_WE_SLAVE_RATIO is : 0x119

    DATA_PHY_WR_DQS_SLAVE_RATIO is : 0xC6

    DATA_PHY_WR_DATA_SLAVE_RATIO is : 0xFF

    ***************************************************************

    #3

    ***************************************************************

    DATA_PHY_RD_DQS_SLAVE_RATIO is :0x3C

    DATA_PHY_FIFO_WE_SLAVE_RATIO is : 0x11D

    DATA_PHY_WR_DQS_SLAVE_RATIO is : 0x8B

    DATA_PHY_WR_DATA_SLAVE_RATIO is : 0xC5

    ***************************************************************

    #4

    ***************************************************************

    DATA_PHY_RD_DQS_SLAVE_RATIO is :0x3C

    DATA_PHY_FIFO_WE_SLAVE_RATIO is : 0x11C

    DATA_PHY_WR_DQS_SLAVE_RATIO is : 0x89

    DATA_PHY_WR_DATA_SLAVE_RATIO is : 0xC3

    ***************************************************************

    2.

    for the 303MHz case, can you dump the EMIF registers in u-boot.  Addresses 0x4c000000-0x4c0000E8

    I using board 1 to display register

    U-Boot# md 0x4c000000 0x3A

    4c000000: 40443403 40000004 61a053b2 00000000    .4D@...@.S.a....

    4c000010: 0000093b 0000093b 0888a39b 0888a39b    ;...;...........

    4c000020: 246d7fda 246d7fda 50ffe6af 50ffe6af    ..m$..m$...P...P

    4c000030: 00000000 00000000 00000000 00000000    ................

    4c000040: 00000000 00000000 00000000 00000000    ................

    4c000050: 00000000 00ffffff 8000140a 00021616    ................

    4c000060: 00002011 00000000 00000000 00000000    . ..............

    4c000070: 00000000 00000000 00000000 00000000    ................

    4c000080: 00600242 000568af 00010000 00000000    B.`..h..........

    4c000090: 3a43ca80 00000000 00050000 00050000    ..C:............

    4c0000a0: 00000000 00000000 00000000 00000000    ................

    4c0000b0: 00000000 00000000 00000000 00000000    ................

    4c0000c0: 00000000 00000000 50074be1 00000000    .........K.P....

    4c0000d0: 00000000 00000000 00000000 00000000    ................

    4c0000e0: 00000000 00100208                      ........

    3.

    can you successfully perform single memory write and reads in u-boot?

    Sorry, I can’t get the point,

    What’s the purpose?

    I can load kernel and file system from eMMC to DDR to booting.

    4.

    -do you ever have a problem booting, or do you only see a problem when running memtester?

    Kernel might be crash during booting or finish booting.

    5.

    -for the 303MHz memtester run, it appears that byte1 is faulty.  Is this consistent across multiple memtester runs and multiple boards?

    The board 3 and 4 seem have different value when software leveling,

    And board 3 and 4 are more difficult to finish kernel booting, usually crash during kernel booting.

    Thanks

    Daniel

  • 0 in reply to Daniel Cheng1
    Mastermind 6355 points

    Hi James

    For the trace length values you have plugged into the tool, is the clock to byte 0 2.22in, and byte 1 61in?

    As the schematic, the DDR U3 connects to the CPU with the net name DQS0. Is it mean that refers to byte0?

    And then the other DDR U4 will represent the byte1. Right.

    From the below Layout trace figure, we might find that the Byte 0 length is longer than Byte 1.

    I have tried to re-calculator the length of the trace, please see the attached file. We might use this value for the EMIF tool.

     

    Have you followed all the DDR layout guidelines in the AM335x datasheet, especially length matching guidelines?

    Yes, we have followed the length matching guidelines, please see the attached excel file.

    6562.Length.docxPG5902_AM335x_Trace Length Report 20220420.xlsx

    Thanks

    Daniel

  • 0 in reply to Daniel Cheng1
    TI__Guru* 80020 points

    Daniel, thank you for the info

    One thing i see in your trace length report is that CK to Addr_ctrl skew is almost 200mil.  This should be <25mil based on table 7-66 (A1+A2 skew < 25mil).  The skew should be calculated for each segment as shown in the table.  I think this may be why you have a little more success as slower frequencies. The excessive skew is severely eating into your timing margin.

    Also, the number of vias on the differential CK signals seems excessive (6).  This is a critical signal to route, and the vias introduce impedance discontinuities which can lead to poor signal quality.  Need to ensure CK and the addr_ctrl signals are routed similarly, with a solid ground reference.

    Were any signal integrity board simulations performed on this board?  

    We can try to get this board functional.  I think you will have to stick with 303MHz.  It appears the software leveling algorithm is having a hard time converging to optimal values, so i think you may have to experiment manually to see if you can get things functional.  Can you try the following experiments

    Build you code with the following values, which are the original seed values from the spreadsheet:

    #define V73CBG04808RDJ11_RD_DQS 0x40
    #define V73CBG04808RDJ11_WR_DQS 0x10E
    #define V73CBG04808RDJ11_PHY_FIFO_WE 0x80
    #define V73CBG04808RDJ11_PHY_WR_DATA 0xC0

    -try to boot and run memtester with this build

    -add 0x10 to both PHY_FIFO_WE and PHY_WR_DATA and repeat the experiment of booting and memtester

    -continue adding 0x10 and repeat the experiment, until you can't boot anymore.  I would expect this to be around when PHY_FIFO_WE is 0xD0 or above

    Record the results.  The experiments are attempting to find the optimal values for the write path.  I think the read path value are ok, based on your algorithm results.  Hopefully this will at least get you functional.

    Regards,

    James

     

  • 0 in reply to JJD
    Prodigy 50 points
    JJD said:
    #define V73CBG04808RDJ11_RD_DQS 0x40
    #define V73CBG04808RDJ11_WR_DQS 0x10E
    #define V73CBG04808RDJ11_PHY_FIFO_WE 0x80
    #define V73CBG04808RDJ11_PHY_WR_DATA 0xC0

    Hi James,

    Are there any typo on the value?

    The spreadsheet shows as below in 303M

    #define  DATA_PHY_RD_DQS_SLAVE_RATIO     0x00000040
    #define  DATA_PHY_FIFO_WE_SLAVE_RATIO    0x0000010E
    #define  DATA_PHY_WR_DQS_SLAVE_RATIO    0x00000080
    #define  DATA_PHY_WR_DATA_SLAVE_RATIO    0x000000C0

  • 0
    Prodigy 50 points

    Hi James,

    I have done below test, it seem that I can't find functional value manually.

    #define V73CBG04808RDJ11_RD_DQS                0x00000040
    #define V73CBG04808RDJ11_WR_DQS                0x00000080
    #define V73CBG04808RDJ11_PHY_FIFO_WE        0x0000010E
    #define V73CBG04808RDJ11_PHY_WR_DATA        0x000000C0
        Crash during boot
        Crash during boot
        Crash during boot

    #define V73CBG04808RDJ11_RD_DQS                0x00000040
    #define V73CBG04808RDJ11_WR_DQS                0x00000080
    #define V73CBG04808RDJ11_PHY_FIFO_WE        0x0000011E
    #define V73CBG04808RDJ11_PHY_WR_DATA        0x000000D0
        Crash during boot
        Crash during boot
        Crash during boot

    #define V73CBG04808RDJ11_RD_DQS                0x00000040
    #define V73CBG04808RDJ11_WR_DQS                0x00000080
    #define V73CBG04808RDJ11_PHY_FIFO_WE        0x0000012E
    #define V73CBG04808RDJ11_PHY_WR_DATA        0x000000E0
        Crash during boot
        memtester 20M 10 fail and crash
        Crash during boot

    #define V73CBG04808RDJ11_RD_DQS                0x00000040
    #define V73CBG04808RDJ11_WR_DQS                0x00000080
    #define V73CBG04808RDJ11_PHY_FIFO_WE        0x0000013E
    #define V73CBG04808RDJ11_PHY_WR_DATA        0x000000F0
        can't boot

    #define V73CBG04808RDJ11_RD_DQS                0x40
    #define V73CBG04808RDJ11_WR_DQS                0x10E
    #define V73CBG04808RDJ11_PHY_FIFO_WE        0x80
    #define V73CBG04808RDJ11_PHY_WR_DATA        0xC0
        can't boot

    #define V73CBG04808RDJ11_RD_DQS                0x40
    #define V73CBG04808RDJ11_WR_DQS                0x10E
    #define V73CBG04808RDJ11_PHY_FIFO_WE        0x90
    #define V73CBG04808RDJ11_PHY_WR_DATA        0xD0
        can't boot

    #define V73CBG04808RDJ11_RD_DQS                0x40
    #define V73CBG04808RDJ11_WR_DQS                0x10E
    #define V73CBG04808RDJ11_PHY_FIFO_WE        0xA0
    #define V73CBG04808RDJ11_PHY_WR_DATA        0xE0
        can't boot

    #define V73CBG04808RDJ11_RD_DQS                0x40
    #define V73CBG04808RDJ11_WR_DQS                0x10E
    #define V73CBG04808RDJ11_PHY_FIFO_WE        0xB0
    #define V73CBG04808RDJ11_PHY_WR_DATA        0xF0
        can't boot

    #define V73CBG04808RDJ11_RD_DQS                0x40
    #define V73CBG04808RDJ11_WR_DQS                0x10E
    #define V73CBG04808RDJ11_PHY_FIFO_WE        0xC0
    #define V73CBG04808RDJ11_PHY_WR_DATA        0x100
        can't boot

    #define V73CBG04808RDJ11_RD_DQS                0x40
    #define V73CBG04808RDJ11_WR_DQS                0x10E
    #define V73CBG04808RDJ11_PHY_FIFO_WE        0xD0
    #define V73CBG04808RDJ11_PHY_WR_DATA        0x110
        can't boot

  • 0 in reply to Jimmy Liao
    Mastermind 6355 points

    Hi James

    The attachment is the signal integrity board simulations performed report.

    Thanks

    Daniel

    DDR_report.pdf

  • 0 in reply to Daniel Cheng1
    TI__Guru* 80020 points

    Jimmy, I'm very sorry, i transposed the parameters that i told you to adjust.  

    You're original values are this:

    #define V73CBG04808RDJ11_RD_DQS 0x3C
    #define V73CBG04808RDJ11_WR_DQS 0x80
    #define V73CBG04808RDJ11_PHY_FIFO_WE 0x10E
    #define V73CBG04808RDJ11_PHY_WR_DATA 0xC0

    -try to boot and run memtester with this build

    -add 0x10 to both PHY_WR_DQS and PHY_WR_DATA and repeat the experiment of booting and memtester

    -continue adding 0x10 and repeat the experiment, until you can't boot anymore.  I would expect this to be around when PHY_WR_DQS is 0xD0 or above

    I took a look at your report, it seems like you have plenty of margin, I'm not sure why the algorithm isn't converging.  Do you have JTAG access to your board.  The latest algorithm is downloadable via JTAG and can be found here:  https://www.ti.com/lit/pdf/SPRACK4 You are using a u-boot version of the tool which I'm not sure is the latest.  Can you try the file in the zip that is in the app note, and use the .out and gel file in there?

    Regards,

    james

  • 0
    Prodigy 50 points

    Hi James,

    I have finished WR DQS manually,

    Unfortunately, the system still unsteady.

    #define V73CBG04808RDJ11_RD_DQS                0x3C
    #define V73CBG04808RDJ11_WR_DQS                0x80
    #define V73CBG04808RDJ11_PHY_FIFO_WE        0x10E
    #define V73CBG04808RDJ11_PHY_WR_DATA        0xC0
        Crash during boot
        memtester 20M 10 fail and crash
        Crash during boot

    #define V73CBG04808RDJ11_RD_DQS                0x3C
    #define V73CBG04808RDJ11_WR_DQS                0x90
    #define V73CBG04808RDJ11_PHY_FIFO_WE        0x10E
    #define V73CBG04808RDJ11_PHY_WR_DATA        0xD0
        Crash during boot
        Crash during boot
        Crash during boot

    #define V73CBG04808RDJ11_RD_DQS                0x3C
    #define V73CBG04808RDJ11_WR_DQS                0xA0
    #define V73CBG04808RDJ11_PHY_FIFO_WE        0x10E
    #define V73CBG04808RDJ11_PHY_WR_DATA        0xE0
        Crash during boot
        Crash during boot
        Crash during boot

    #define V73CBG04808RDJ11_RD_DQS                0x3C
    #define V73CBG04808RDJ11_WR_DQS                0xB0
    #define V73CBG04808RDJ11_PHY_FIFO_WE        0x10E
    #define V73CBG04808RDJ11_PHY_WR_DATA        0xF0
        memtester 20M 10 fail and crash
        Crash during boot
        Crash during boot

    #define V73CBG04808RDJ11_RD_DQS                0x3C
    #define V73CBG04808RDJ11_WR_DQS                0xC0
    #define V73CBG04808RDJ11_PHY_FIFO_WE        0x10E
    #define V73CBG04808RDJ11_PHY_WR_DATA        0x100
        Crash during boot
        memtester 20M 10 fail and crash
        Crash during boot

    #define V73CBG04808RDJ11_RD_DQS                0x3C
    #define V73CBG04808RDJ11_WR_DQS                0xD0
    #define V73CBG04808RDJ11_PHY_FIFO_WE        0x10E
    #define V73CBG04808RDJ11_PHY_WR_DATA        0x110
        Crash during boot
        Crash during boot
        Crash during boot

    #define V73CBG04808RDJ11_RD_DQS                0x3C
    #define V73CBG04808RDJ11_WR_DQS                0xE0
    #define V73CBG04808RDJ11_PHY_FIFO_WE        0x10E
    #define V73CBG04808RDJ11_PHY_WR_DATA        0x120
        Crash during boot
        Crash during boot
        Crash during boot

    #define V73CBG04808RDJ11_RD_DQS                0x3C
    #define V73CBG04808RDJ11_WR_DQS                0xF0
    #define V73CBG04808RDJ11_PHY_FIFO_WE        0x10E
    #define V73CBG04808RDJ11_PHY_WR_DATA        0x130
        memtester 20M 1 fail
        Crash during boot
        Crash during boot

    #define V73CBG04808RDJ11_RD_DQS                0x3C
    #define V73CBG04808RDJ11_WR_DQS                0x100
    #define V73CBG04808RDJ11_PHY_FIFO_WE        0x10E
    #define V73CBG04808RDJ11_PHY_WR_DATA        0x140
        can't boot

    #define V73CBG04808RDJ11_RD_DQS                0x40
    #define V73CBG04808RDJ11_WR_DQS                0x80
    #define V73CBG04808RDJ11_PHY_FIFO_WE        0x10E
    #define V73CBG04808RDJ11_PHY_WR_DATA        0xC0
        memtester 20M 10 fail and crash
        Crash during boot
        Crash during boot

    #define V73CBG04808RDJ11_RD_DQS                0x40
    #define V73CBG04808RDJ11_WR_DQS                0x90
    #define V73CBG04808RDJ11_PHY_FIFO_WE        0x10E
    #define V73CBG04808RDJ11_PHY_WR_DATA        0xD0
        memtester 20M 1 fail
        Crash during boot
        Crash during boot

    #define V73CBG04808RDJ11_RD_DQS                0x40
    #define V73CBG04808RDJ11_WR_DQS                0xA0
    #define V73CBG04808RDJ11_PHY_FIFO_WE        0x10E
    #define V73CBG04808RDJ11_PHY_WR_DATA        0xE0
        Crash during boot
        Crash during boot
        Crash during boot

    #define V73CBG04808RDJ11_RD_DQS                0x40
    #define V73CBG04808RDJ11_WR_DQS                0xB0
    #define V73CBG04808RDJ11_PHY_FIFO_WE        0x10E
    #define V73CBG04808RDJ11_PHY_WR_DATA        0xF0
        Crash during boot
        Crash during boot
        Crash during boot

    #define V73CBG04808RDJ11_RD_DQS                0x40
    #define V73CBG04808RDJ11_WR_DQS                0xC0
    #define V73CBG04808RDJ11_PHY_FIFO_WE        0x10E
    #define V73CBG04808RDJ11_PHY_WR_DATA        0x100
        memtester 20M 10 fail and crash
        Crash during boot
        Crash during boot

    #define V73CBG04808RDJ11_RD_DQS                0x40
    #define V73CBG04808RDJ11_WR_DQS                0xD0
    #define V73CBG04808RDJ11_PHY_FIFO_WE        0x10E
    #define V73CBG04808RDJ11_PHY_WR_DATA        0x110
        Crash during boot
        Crash during boot
        memtester 20M 10 fail and crash

    #define V73CBG04808RDJ11_RD_DQS                0x40
    #define V73CBG04808RDJ11_WR_DQS                0xE0
    #define V73CBG04808RDJ11_PHY_FIFO_WE        0x10E
    #define V73CBG04808RDJ11_PHY_WR_DATA        0x120
        Crash during boot
        Crash during boot
        Crash during boot

    #define V73CBG04808RDJ11_RD_DQS                0x40
    #define V73CBG04808RDJ11_WR_DQS                0xF0
    #define V73CBG04808RDJ11_PHY_FIFO_WE        0x10E
    #define V73CBG04808RDJ11_PHY_WR_DATA        0x130
        Crash during boot
        Crash during boot
        Crash during boot

    #define V73CBG04808RDJ11_RD_DQS                0x40
    #define V73CBG04808RDJ11_WR_DQS                0x100
    #define V73CBG04808RDJ11_PHY_FIFO_WE        0x10E
    #define V73CBG04808RDJ11_PHY_WR_DATA        0x140
        can't boot

    I have got a jTag this morning, and I finished software leveling in CCS today,

    The console information of CCS

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    [CortxA8]
    Enter the PHY_INVERT_CLKOUT value (0 or 1) from the spreadsheet
    1
    Enter the Seed RD_DQS_SLAVE_RATIO Value in Hex to search the RD DQS Ratio Window
    40
    Enter the Seed FIFO_WE_SLAVE_RATIO Value in Hex to search the RD DQS Gate Window
    10e
    Enter the Seed WR_DQS_SLAVE_RATIO Write DQS Ratio Value in Hex to search the Write DQS Ratio Window
    80
    ***************************************************************
    The Slave Ratio Search Program Values are...
    ***************************************************************
    PARAMETER MAX | MIN | OPTIMUM | RANGE
    ***************************************************************
    DATA_PHY_RD_DQS_SLAVE_RATIO 0x074 | 0x003 | 0x03b | 0x071
    DATA_PHY_FIFO_WE_SLAVE_RATIO 0x1e3 | 0x05f | 0x121 | 0x184
    DATA_PHY_WR_DQS_SLAVE_RATIO 0x0fb | 0x00f | 0x085 | 0x0ec
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    My gel date

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    //####################################################
    //AM3358_SK GEL file
    //v1.1 Apr3,2012 Fixed WDT1 disable
    //v1.1 May2,2012 Streamlined DDR3 PHY configuration routines,
    // included proper DDR3 PHY values
    //v1.2 Jun21,2012 Added support for v1.2 board (enable VTT regulator via GPIO)
    //v1.3 Oct25,2012 adjusted MPU freq. to match with DM
    // other minor cleanup
    //v1.4 Jun3, 2014 Added reference to PRU GEL file
    //v1.5 Sep25,2015 Added System Reset at Connect
    // Disabling MMU before loading code
    //v1.6 Nov2,2016 Changed INVERT_CLK=1, PHY_CTRL_SLAVE_RATIO=0x100
    // Changed DDR=400MHz
    // Also reran with new SW leveling algorithm
    // Aligning with SK and IDK GELs
    //####################################################
    //****************************************************
    //PRCM module definitions
    //****************************************************
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    The system still unsteady in 303MHz, too.

    Do you have any suggest about it?

    Jimmy

  • 0 in reply to Jimmy Liao
    TI__Guru* 80020 points

    Jimmy, i'm looking into this offline with Rich.

    James

  • 0
    Prodigy 50 points

    Hi James,

    Get it, thanks for your support.

    Jimmy

  • 0 in reply to Jimmy Liao
    TI__Guru* 80020 points

    ok, still working offline with Rich.

    James