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AM5728: 8 audio channels from 1 McASP

Part Number: AM5728
Other Parts Discussed in Thread: BEAGLEBOARD-X15, TLV320AIC3104, TLV320AIC3204, PCM3168A-Q1

Hello,

I need to output 8 audio channels (each receiver would be single channel; 2 wire; 600Ohm) from a AM5728. 

I read on the documentation that:

"Audio Connectivity Peripherals
• Eight multichannel audio serial ports (McASP):
– Two McASP supporting up to 16 channels each and independent TX/RX clock/sync domains"

So it seems it is possible to transmit 8 different audio channels by using a single McASP interface.

I guess I need to connect 8 different audio CODECs to that McASP interface.

How is the connection done? Is it possible to cascade connect 8 CODECs to a single McASP interface?

What kind of external audio CODECs do I need?

Regards,

  • The McASP experts have been notified. They will respond here.
  • Hi Jorge,

    From software perspective you can have 8 channels on a single MCASP. To achieve this you need to do the following modifications:
    1. Change the TMD slots in arch/arm/boot/dts/am572xx-beagle-x15-common.dtsi:
    tdm-slots = <2>;
    2. Change the audio node in the same dtsi file as above:
    sound0: sound0 {
    compatible = "simple-audio-card";
    simple-audio-card,name = "BeagleBoard-X15";
    simple-audio-card,widgets =
    "Line", "Line Out",
    "Line", "Line In";
    simple-audio-card,routing =
    "Line Out", "LLOUT",
    "Line Out", "RLOUT",
    "MIC2L", "Line In",
    "MIC2R", "Line In";
    simple-audio-card,format = "dsp_b";
    simple-audio-card,bitclock-master = <&sound0_master>;
    simple-audio-card,frame-master = <&sound0_master>;
    simple-audio-card,bitclock-inversion;

    simple-audio-card,cpu {
    sound-dai = <&mcasp3>;
    };

    sound0_master: simple-audio-card,codec {
    sound-dai = <&tlv320aic3104>;
    clocks = <&clkout2_clk>;
    };
    3. Check the maximum number of channels in sound/soc/davinci/davinci-mcasp.c. In latest TI SDK (SDK04.01.00.06, kernel 4.9.41) it should be fine :
    .playback = {
    .channels_min = 1,
    .channels_max = 32 * 16,
    .rates = DAVINCI_MCASP_RATES,
    .formats = DAVINCI_MCASP_PCM_FMTS,
    }

    Then there is the problem with mapping the channels within alsa, see this thread for reference:
    e2e.ti.com/.../313430

    Also there is the problem with the hardware clocking scheme outside the AM5728 device. You should buffer the clocks to supply all the external codecs.

    There is another possibility:
    use two mcasps + two 4-channel codecs (see this thread: e2e.ti.com/.../512683).

    I am not sure what will be the CPU loading using your scheme with 8 audio channels.

    Best Regards,
    Yordan
  • Hello Yordan

    Thank you for the answer.

    First of all, I would like to clarity the hardware design (provided that with SW configuration can work)

    -       Option 1: A single MCASP interface for 8 channels

    What interface with the CODECs is needed? If I choose to cascade connect 8 CODECs with TDM interface, like TLV320AIC3204. Would they reproduce the 8 different channels transmitted from the single MCASP interface? (Buffering the clock signal if needed)

    -       Option 2: Two MCASP interfaces connected to two quad-Audio CODEC

    In which way would it be a better solution? Just for the clocking and routing advantage? (2 clocks and data lines vs 8 clocks and data lines) or is it also better from the SW point of view?

    -       Option 3: A single 8 channel driver like pcm3168a-q1

    Could these 8 channel audio CODEC understand the MCASP interface ?

    Regards,

     

  • Jorge,

    I would go with option 3.  It'll take the least amount of board space, and enable you to just run the McASP clock signals from the SoC to one DAC, as opposed to fanning them out to multiple devices.

    Yes, just about any audio DAC will be able to talk to the McASP.  More than likely, you'll connect McASP to your DAC of choice in I2S mode, so you'll connect:

    -McASPx_AHCLKX to the DAC MCLK (master clock)

    -McASPx_ACLKX to the DAC BCK (bit clock)

    -McASPx_AFSX to the DAC LRCK or WCK (left-right clock, bit clock, frame sync...different names for the same thing)

    -McASPx_AXR[0:3] (or whichever serializer pins you choose) to the DACs data input pins.

    In theory, you could use just one McASP data pin, set up for 8-slot TDM, but then you'll have to run your clocks faster, and that just complicates the layout a bit.  What I'm describing above is I2S mode, which will send out two audio channels per serializer pin.  Here's an example of the hookup:
    http://www.ti.com/lit/df/sprr310/sprr310.pdf

    Check out page 9.  There are two 8-ch DACs there, but you would use just one.

    As far as setting up McASP for I2S mode, please read up on I2S a bit.  It's a specific case of TDM, where:

    -there are two slots per frame (AFSXCTL.XMOD = 2-slot TDM)

    -falling edge on frame sync indicates start of frame (AFSXCTL.FSXP = falling edge)

    -one-bit data delay (XFMT.XDATDLY = 1)

    Please have a look at the TRM chapter on McASP; I've given you some register and bitfield names to look at.  The above is not the complete McASP setup; I'm just pointing out the key settings for I2S mode.

    Just to be clear - these eight output channels are all synchronous with respect to each other, right?  They'd all be running on the same clock?

    Hopefully this will get you started.

    Bobby

  • Thank you Bobby,

    That was a really helpful answer.

    Whether or not audio sources will be all synchronous is hard to tell at this moment (probably they will not). However connecting 8 different MCASP interfaces (in order to have asynchronous channels) is not feasible.

    Should I have asynchronous channels, I would process the channels so that when a mismatch occurs, an audio sample is copied/discarded so that the eight audio channels can be transmitted to a DAC over a single clocking scheme. Does it sound feasible?

    Yes, It gets me started.

    Thanks.

    .

  • Hi, sorry I missed this.  If you have async content and you want to send it all out over one McASP, then you essentially have to perform ASRC on that data before shipping it off to the DAC.  This can be done in software, but not sure what the MIPS price will be.  In principle,you should be OK.