66AK2L06: RFSDK 02.00.03 Source Files

Hello,
Memhet, I am not in that group now. I can provide some input.
There are two third party consultants that can build the DFE configuration, they have the DFE register compiler:
CommAgility - England
Azcom - Italy
The overall Keystone 2 project manager is Greg Wood, you can have your TI Sales engineer contact him, for support, but I think you will have to work with a third party.

The digital radio transports Complex I and Q data from the digital radio to the IQN2 to memory.
You can have a 15bit bypass function (the LSB is rounded), since you have a 14bit ADC this is not a concern.
Bypass functions assume a complex input.

You do not want to change the playback code, serdes config, or IQN2 to DFE, or IQN2 to PktDMA.

ADC -> Serdes -> JESD-DFE -> Rx-DFE -> Rx-DDUC-DFE -> Rx-BB-DFE -> IQN2
The playback code configures the Serdes and IQN2.
The DFE output file is the register programming for DFE.
The playback code also has the initialization procedure for the above blocks.
As you know, the ADC needs to be initialized first, before the 66AK2L06 - RFSDK2.

Note: the serdes and IQN configuration, has source code with the RFSDK. You need to not change this. The serdes to DFE-JESD input configuration has a specific working relationship. The DFE-Baseband output configuration to IQN2 has a specific working relationship

If you are trying to get ADC I data, there are two choices.

a) snapshot - use the DFE GEL file, to capture the JESD Rx format block output, this captures the direct test bus, this is not streamed, this would be captured in the capture buffer. You can modify the GEL file, to capture 8,16,32K samples of data, then you have to read the data from the static capture memory

in order to see the ADC data, the signal processing within the DFE would have to provide no complex filtering, and no frequency tuning. in your configuration, the Rx input performs the Hilbert transform to tune down by Fs/4 and apply a filter. This converts the 245.76Msps ADC to 122.88Msps complex. Also the DDUC Rx PFIR filter would need to be set to an impulse (currently it is an 80% passband low pass filter).

b1) use a Rx complex input, this is not the ADC you have selected Using an Rx receiver with a 122.88Msps output F=2. I and Q, the receiver output is bypassed to within 15bits of the 16 bit output.

b2) modify the DFE configuration so that the JESD Rx so that the real input is treated as an interleaved complex input.
this has not been tested. This is not a standard JESD Rx mode. The DFE bypass processing provides for I = input, Q = input+1.
This is the only answer to your question. It requires research, custom testing, and a new configuration. Note: 15bit bypass has been tested.

b3) have a modified DFE configuration where the Rx input is converted to complex (Hilbert) -Fs/4, the rest of Rx is not filtering. The IQN2 output is a complex output at 122.88Msps. You perform another Hilbert transfer of the complex 122.88 data, back to a real stream at 245.76. This has two filtering processes, so you do not recover the exact ADC codes. This is the easiest for DFE to implement.

The DFE source code, without the cmd5798 register compiler, would not provide you with an answer. There is also a Linux converter after the .reg file output.

Regards,
Joe Quintal

Hello,
The latest MCSDK 3147 was what was used last year for RFSDK work.
The GEL files are part of the MCSDK software package. The appended letter indicates which part in the Keystone family the GEL file is for
"letter L" - TCT6630K2L / 66AK2L06. If you goto the MCSDK software support area, you can request MCSDK 3147 as the last non-Processor SDK version. The DFE GEL file was provided by our application team, this is used for debugging, and extended usage of the capture buffer to snapshot capture various signals in the DFE block. There is also the extraction of IQ data from the 32bit memory capture using CCS, I had sent a matlab script for this before.

Regards,
Joe Quintal

Hello,

If we had an odd and even real sample, packed into 2 JESD lanes, with a bit rate of 2.4576Gbps, they would be presented to 66aK2L06 as 2 JESD lanes, L=2, M=2(this should be a 1, but the JESD block does not process M=1 in this mode, F=2).

Alternately the input can be an odd and even real sampled packed into 1 JESD lane, with a bit rate of 4.9152Gbps, they would be preseted to 66ak2l06 as 1 JESD lane, L=1, M=2, F = 4).   (the JESD Rx mode is called 222ix  odd and even data would be present in JESD Lane 0, JESD Lane 1 is disabled.

Note: the JESD paramters for LMF have to be matched between the data converter output, and the DFE-JESD.   

The Serdes configuration needs to match the case used above (this is built into the playback code, which the RFSDK2 has source code.

The DFE configuration would have to be rebuilt as  different JESD Rx mode, 1 complex input at 122.88Msps to Rx, DFE DDUC Rx PFIR would have to be an impulse,   You would have to post process the IQn2 122.88Msps complex output as odd, even real samples.

This would normally be done through the RFSDK2 third party provider Azcom.   

Regards,

Joe Quintal