AM3358: SD card issue

Hello,

 When I load the MLO and U-Boot.img from the serial interface I mostly get the following output from the second stage bootloader (Without SD-Card inserted), then it hangs:

I am wondering if you could please share the location where the images are getting loaded. Also, what is the  sys-boot pin configuration for the custom board?

If you do not have a CD pin on your controller, please try to comment the line "cd-gpios = <&...."(under mmc1 node) in the file am335x-bone-common.dtsi (uboot).

Regards,

Krunal

Hello,

When I load U-Boot over serial interface the locations are as follow:
<Processor SDK>/board-support/u-boot-<version>/spl/u-boot-spl.bin
<Processor SDK>/board-support/u-boot-<version>/u-boot.img

The boot pin is defined as:
01 00 00 0 0 00 1 11100

- MMC1, MMC0, UART0, USB0
- CLKOUT1 enabled
- 24MHz

I have tried now to disable the "cd-gpios = <&...."(under mmc1 node) in the am335x-bone-common.dts I file, and then boot from SD Card, but still I get the same terminal output as my previous post. I also removed the CD pin definition in Mux.c
I am a bit confused with the MMC numbering. AM335x datasheet state my MMC is connected to MMC0 pins. In U-Boot in 'mux.c'  I define MMC0 pins, in 'am335x-bone-common.dts' it is called MMC1 and then I boot from SD-Card in the terminal is state that is tries to boot from MMC1. I assume it is all mention about the same MMC which I have connected?

In the DTB file I did as follow. I also commented out 'pinctrl' because it is only defining the GPIO6 on the top of the file. I tried with and without this line.

&mmc1 {
	status = "okay";
	bus-width = <0x4>;
	pinctrl-names = "default";
	/*pinctrl-0 = <&mmc1_pins>;
	cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; */
};

In mux.c I did:

static struct module_pin_mux mmc0_pin_mux[] = {
	{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT3 */
	{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT2 */
	{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT1 */
	{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT0 */
	{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CLK */
	{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CMD */
	{OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)},		/* MMC0_WP */
	/*{OFFSET(spi0_cs1), (MODE(7) | RXACTIVE | PULLUP_EN)},	 GPIO0_6 */
	{-1},
};

Hello Krunal,

I would like to add some more information in this post, because I am verifying that there is no hardware issue involved. Maybe it helps to get a better picture.

In the case that I mentioned before that one out of 20 times I see something on my terminal when booting from SD-Card. I have put my oscilloscope on the I2C communication from the AM3358 to the TPS65217B so that I can identify that U-Boot is initializing even when I don't see a terminal output. The result is that every time when I switch on I can see data going over the I2C bus.
Also I check data over from the SD-Card to the AM3358 and that also looks good.

Now the next step. I measured the voltages with the oscilloscope from the TPS65217B.
Below the image of the TPS65217B form my schematic.
For all the scope measurement results, please download V2.0.2 Voltage pictures.zip
Please note that I configured U-Boot for a CPU frequency was 600 when I was making the measurements:    freq = MPUPLL_M_600

After that I have tried to debug in CCS when booting from SD-Card and see where the SD card boot in the SPL get stuck.

1. When I put my breakpoint at "err = mmc_send_cmd(mmc, &cmd, NULL);"  then do a Step-Over, then press continue, then the SPL continues and is loading the second stage bootloader.
2. When I put my breakpoint AFTER the function I mentioned, then it will crash and it will go to:
            bl    1b            /* hang and never return */      ( File:  vertor.S)

I have tried to put a delay before and after as you can see, but that is not helping. I tried to go into "mmc_send_cmd(mmc, &cmd, NULL);"  but when I step through there is no issue.

I have the terminal log in the case when booting from SD-Card the second stage boot-loader is loaded: second_stage_log.log
When it get stuck in this moment, this is the following output without #DEBUG:
U-Boot 2018.01-00569-g7b4e473-dirty (Apr 13 2019 - 22:58:24 +0400)
CPU  : AM335X-GP rev 2.1
Model: TI AM335x BeagleBone Black                                                                                               
DRAM:  256 MiB
NAND:  0 MiB
MMC:

I hope someone can help me with this problem.

Thanks, and regards

Hello,

I have come one step further. I still have an issue with the SD card, what I can see in the log, but I got rid of the problem I have in the SPL loader for reading the SD-Card.

I did disable FIT in the am335x_evm_defconfig and now when I power on the board it loads the SPL in external DDR.
CONFIG_SPL_LOAD_FIT=n

In am335x-bone-common.dtsi I changed to remove the CD pin:
&mmc1 {
    status = "okay";
    bus-width = <0x4>;
    pinctrl-names = "default";
    pinctrl-0 = <&mmc1_pins>;
    /* cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; */
};

In mux.c I removed the CD pin as well:

static struct module_pin_mux mmc0_pin_mux[] = {
	{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT3 */
	{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT2 */
	{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT1 */
	{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT0 */
	{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CLK */
	{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CMD */
	{OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)},		/* MMC0_WP */
	/* {OFFSET(spi0_cs1), (MODE(7) | RXACTIVE | PULLUP_EN)},	 GPIO0_6 */
	{-1},
};

The reason I think I have still a problem with the SD-Card can be seen in this log file which for the seconds stage boot-loader:
second_stage_log_2.log

Problem:
gpio_request_tail: Node 'mmc@481d8000', property 'cd-gpios', failed to request GPIO index 0: -2
gpio_request_tail: Node 'mmc@481d8000', property 'wp-gpios', failed to request GPIO index 0: -2
OMAP SD/MMC: 0, OMAP SD/MMC: 1
initcall: 8080e925 (relocated to 8ff3f925)
fdtdec_get_config_int: load-environment
get_dev_hwpart: No device for iface 'mmc', dev 8
** Bad device mmc 0 **
Using default environment

I hope someone can tell me what is wrong.
Thanks and regards

Hello J,

Can you add broken-cd; label to the mmc1 node and retry?

Best regards,
Kemal

Hello kemal,

Thanks for your reply.

I have tried as you mentioned but I see no difference. This is my output:  7367.minicom.log
I will add also my am335x_evm_defconfig:  am335x_evm_defconfig.zip

My mux.c

static struct module_pin_mux mmc0_pin_mux[] = {
	{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT3 */
	{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT2 */
	{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT1 */
	{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT0 */
	{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CLK */
	{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CMD */
	{OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)},		/* MMC0_WP */
	/* {OFFSET(spi0_cs1), (MODE(7) | RXACTIVE | PULLUP_EN)},   GPIO0_6 */
	{-1},
};

My am335x-bone-common.dtsi
&mmc1 {
    status = "okay";
    bus-width = <0x4>;
    pinctrl-names = "default";
    broken-cd;
    pinctrl-0 = <&mmc1_pins>;
    /* cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; */
};

When I disable my #DEBUG then I can type thing in the u-boot terminal. You want me to check something there related to this issue?
I can already show this from u-boot:
=> mmcinfo
Device: OMAP SD/MMC
Manufacturer ID: 0
OEM: 0
Name: 0000Bus Speed: 24000000
Mode : SD Legacy
Rd Block Len: 512
SD version 1.0
High Capacity: Yes
Capacity: 14.9 GiB
Bus Width: 4-bit
Erase Group Size: 512 Bytes

When I boot my board by not interrupting u-boot, without #DEBUG then I get this output:
U-Boot SPL 2018.01-00569-g7b4e473-dirty (Apr 20 2019 - 16:17:27)
Trying to boot from MMC1
*** Warning - bad CRC, using default environment

U-Boot 2018.01-00569-g7b4e473-dirty (Apr 20 2019 - 16:17:27 +0400)

CPU  : AM335X-GP rev 2.1
Model: TI AM335x BeagleBone Black
DRAM:  256 MiB
NAND:  0 MiB
MMC:   OMAP SD/MMC: 0, OMAP SD/MMC: 1
*** Warning - bad CRC, using default environment

In:    serial@44e09000
Out:   serial@44e09000
Err:   serial@44e09000
<ethaddr> not set. Validating first E-fuse MAC
Net:   Could not get PHY for cpsw: addr 0
cpsw, usb_ether
Hit any key to stop autoboot:  0
switch to partitions #0, OK
mmc0 is current device
SD/MMC found on device 0
** Unable to read file boot.scr **
data abort
pc : [<8ff6c034>]          lr : [<8ff6c031>]
reloc pc : [<8082e034>]    lr : [<8082e031>]
sp : 8df15208  ip : 00000000     fp : 00000005
r10: 8df152a0  r9 : 8df1ded8     r8 : 00000001
r7 : 8ffbb988  r6 : 00000000     r5 : 00000007  r4 : 8ffbbd28
r3 : 00000000  r2 : 8df152a0     r1 : 00000008  r0 : 00000007
Flags: nzCv  IRQs off  FIQs on  Mode SVC_32
Resetting CPU ...
resetting ...

Thank you.

Hello Kemal,

I forgot to run the ./setup-uboot-env.sh so now I have the u-boot.env file on the boot partition as well.
I also copied the am335x-boneblack.dtp from u-boot compilation and the zImage from the 'rootfs/boot' folder to the boot partition. What more do I need to copy? Because from the TI u-boot manual I do not see it stated.

Here is my u-boot environment vars listed:

=> printenv
arch=arm
args_mmc=run finduuid;setenv bootargs console=${console} ${optargs} root=PARTUUID=${uuid} rw rootfstype=${mmcrootfstype}
baudrate=115200
board=am335x
board_name=A335BNLT
boot_a_script=load ${devtype} ${devnum}:${distro_bootpart} ${scriptaddr} ${prefix}${script}; source ${scriptaddr}
boot_efi_binary=if fdt addr ${fdt_addr_r}; then bootefi bootmgr ${fdt_addr_r};else bootefi bootmgr ${fdtcontroladdr};fi;load ${devtype} ${devnum}:${distro_bootpart} ${kernel_addri
boot_extlinux=sysboot ${devtype} ${devnum}:${distro_bootpart} any ${scriptaddr} ${prefix}extlinux/extlinux.conf
boot_fdt=try
boot_fit=0
boot_net_usb_start=usb start
boot_prefixes=/ /boot/
boot_script_dhcp=boot.scr.uimg
boot_scripts=boot.scr.uimg boot.scr
boot_targets=mmc0 legacy_mmc0 mmc1 legacy_mmc1 nand0 pxe dhcp 
bootcmd=if test ${boot_fit} -eq 1; then run update_to_fit; fi; run findfdt; run init_console; run envboot; run distro_bootcmd
bootcmd_dhcp=run boot_net_usb_start; if dhcp ${scriptaddr} ${boot_script_dhcp}; then source ${scriptaddr}; fi;setenv efi_fdtfile ${fdtfile}; if test -z "${fdtfile}" -a -n "${soc};
bootcmd_legacy_mmc0=setenv mmcdev 0; setenv bootpart 0:2 ; run mmcboot
bootcmd_legacy_mmc1=setenv mmcdev 1; setenv bootpart 1:2 ; run mmcboot
bootcmd_mmc0=setenv devnum 0; run mmc_boot
bootcmd_mmc1=setenv devnum 1; run mmc_boot
bootcmd_nand=run nandboot
bootcmd_pxe=run boot_net_usb_start; dhcp; if pxe get; then pxe boot; fi
bootcount=4
bootdelay=20
bootdir=/boot
bootenvfile=uEnv.txt
bootfile=zImage
bootm_size=0x10000000
bootpart=0:2
bootscript=echo Running bootscript from mmc${mmcdev} ...; source ${loadaddr}
console=ttyO0,115200n8
cpu=armv7
dfu_alt_info_emmc=rawemmc raw 0 3751936;boot part 1 1;rootfs part 1 2;MLO fat 1 1;MLO.raw raw 0x100 0x200;u-boot.img.raw raw 0x300 0x1000;u-env.raw raw 0x1300 0x200;spl-os-args.r1
dfu_alt_info_mmc=boot part 0 1;rootfs part 0 2;MLO fat 0 1;MLO.raw raw 0x100 0x200;u-boot.img.raw raw 0x300 0x1000;u-env.raw raw 0x1300 0x200;spl-os-args.raw raw 0x1500 0x200;spl1
dfu_alt_info_nand=SPL part 0 1;SPL.backup1 part 0 2;SPL.backup2 part 0 3;SPL.backup3 part 0 4;u-boot part 0 5;u-boot-spl-os part 0 6;kernel part 0 8;rootfs part 0 9
dfu_alt_info_ram=kernel ram 0x80200000 0x4000000;fdt ram 0x80f80000 0x80000;ramdisk ram 0x81000000 0x4000000
distro_bootcmd=for target in ${boot_targets}; do run bootcmd_${target}; done
efi_dtb_prefixes=/ /dtb/ /dtb/current/
envboot=mmc dev ${mmcdev}; if mmc rescan; then echo SD/MMC found on device ${mmcdev};if run loadbootscript; then run bootscript;else if run loadbootenv; then echo Loaded env from;
eth1addr=f0:b5:d1:35:19:ce
ethact=cpsw
ethaddr=f0:b5:d1:35:19:cc
fdt_addr_r=0x88000000
fdtaddr=0x88000000
fdtcontroladdr=8df15978
fdtfile=undefined
findfdt=if test $board_name = A335BONE; then setenv fdtfile am335x-bone.dtb; fi; if test $board_name = A335BNLT; then setenv fdtfile am335x-boneblack.dtb; fi; if test $board_name 
finduuid=part uuid mmc ${bootpart} uuid
fit_bootfile=fitImage
fit_loadaddr=0x87000000
ice_mii=mii
importbootenv=echo Importing environment from mmc${mmcdev} ...; env import -t ${loadaddr} ${filesize}
init_console=if test $board_name = A335_ICE; then setenv console ttyO3,115200n8;else setenv console ttyO0,115200n8;fi;
kernel_addr_r=0x82000000
load_efi_dtb=load ${devtype} ${devnum}:${distro_bootpart} ${fdt_addr_r} ${prefix}${efi_fdtfile}
loadaddr=0x82000000
loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenvfile}
loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr
loadfdt=load ${devtype} ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}
loadfit=run args_mmc; bootm ${loadaddr}#${fdtfile};
loadimage=load ${devtype} ${bootpart} ${loadaddr} ${bootdir}/${bootfile}
loadramdisk=load mmc ${mmcdev} ${rdaddr} ramdisk.gz
mmc_boot=if mmc dev ${devnum}; then setenv devtype mmc; run scan_dev_for_boot_part; fi
mmcboot=mmc dev ${mmcdev}; setenv devnum ${mmcdev}; setenv devtype mmc; if mmc rescan; then echo SD/MMC found on device ${mmcdev};if run loadimage; then if test ${boot_fit} -eq 1;
mmcdev=0
mmcloados=run args_mmc; if test ${boot_fdt} = yes || test ${boot_fdt} = try; then if run loadfdt; then bootz ${loadaddr} - ${fdtaddr}; else if test ${boot_fdt} = try; then bootz;;
mmcrootfstype=ext4 rootwait
mtdids=nand0=nand.0
mtdparts=mtdparts=nand.0:128k(NAND.SPL),128k(NAND.SPL.backup1),128k(NAND.SPL.backup2),128k(NAND.SPL.backup3),256k(NAND.u-boot-spl-os),1m(NAND.u-boot),128k(NAND.u-boot-env),128k(N)
nandargs=setenv bootargs console=${console} ${optargs} root=${nandroot} rootfstype=${nandrootfstype}
nandboot=echo Booting from nand ...; run nandargs; nand read ${fdtaddr} NAND.u-boot-spl-os; nand read ${loadaddr} NAND.kernel; bootz ${loadaddr} - ${fdtaddr}
nandroot=ubi0:rootfs rw ubi.mtd=NAND.file-system,2048
nandrootfstype=ubifs rootwait=1
netargs=setenv bootargs console=${console} ${optargs} root=/dev/nfs nfsroot=${serverip}:${rootpath},${nfsopts} rw ip=dhcp
netboot=echo Booting from network ...; setenv autoload no; dhcp; run netloadimage; run netloadfdt; run netargs; bootz ${loadaddr} - ${fdtaddr}
netloadfdt=tftp ${fdtaddr} ${fdtfile}
netloadimage=tftp ${loadaddr} ${bootfile}
nfsopts=nolock
partitions=uuid_disk=${uuid_gpt_disk};name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}
pxefile_addr_r=0x80100000
ramargs=setenv bootargs console=${console} ${optargs} root=${ramroot} rootfstype=${ramrootfstype}
ramboot=echo Booting from ramdisk ...; run ramargs; bootz ${loadaddr} ${rdaddr} ${fdtaddr}
ramdisk_addr_r=0x88080000
ramroot=/dev/ram0 rw
ramrootfstype=ext2
rdaddr=0x88080000
rootpath=/export/rootfs
scan_dev_for_boot=echo Scanning ${devtype} ${devnum}:${distro_bootpart}...; for prefix in ${boot_prefixes}; do run scan_dev_for_extlinux; run scan_dev_for_scripts; done;run scan_;
scan_dev_for_boot_part=part list ${devtype} ${devnum} -bootable devplist; env exists devplist || setenv devplist 1; for distro_bootpart in ${devplist}; do if fstype ${devtype} ${e
scan_dev_for_efi=setenv efi_fdtfile ${fdtfile}; if test -z "${fdtfile}" -a -n "${soc}"; then setenv efi_fdtfile ${soc}-${board}${boardver}.dtb; fi; for prefix in ${efi_dtb_prefixe
scan_dev_for_extlinux=if test -e ${devtype} ${devnum}:${distro_bootpart} ${prefix}extlinux/extlinux.conf; then echo Found ${prefix}extlinux/extlinux.conf; run boot_extlinux; echoi
scan_dev_for_scripts=for script in ${boot_scripts}; do if test -e ${devtype} ${devnum}:${distro_bootpart} ${prefix}${script}; then echo Found U-Boot script ${prefix}${script}; rue
scriptaddr=0x80000000
soc=am33xx
spiargs=setenv bootargs console=${console} ${optargs} root=${spiroot} rootfstype=${spirootfstype}
spiboot=echo Booting from spi ...; run spiargs; sf probe ${spibusno}:0; sf read ${loadaddr} ${spisrcaddr} ${spiimgsize}; bootz ${loadaddr}
spibusno=0
spiimgsize=0x362000
spiroot=/dev/mtdblock4 rw
spirootfstype=jffs2
spisrcaddr=0xe0000
static_ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off
stderr=serial@44e09000
stdin=serial@44e09000
stdout=serial@44e09000
update_to_fit=setenv loadaddr ${fit_loadaddr}; setenv bootfile ${fit_bootfile}
usb_boot=usb start; if usb dev ${devnum}; then setenv devtype usb; run scan_dev_for_boot_part; fi
usbnet_devaddr=f0:b5:d1:35:19:cc
vendor=ti
ver=U-Boot 2018.01-00569-g7b4e473-dirty (Apr 22 2019 - 17:17:31 +0400)

Environment size: 9869/131068 bytes

Here is the u-boot start with #DEBUG:  second_stage_log_3.log

It still shows some issue with the SD-Card for some reason.
I have the broken-cd in this case still in my code, like my previous post.

When I start u-boot without #DEBUG:

U-Boot SPL 2018.01-00569-g7b4e473-dirty (Apr 22 2019 - 17:17:31)
Trying to boot from MMC1
*** Warning - bad CRC, using default environment

U-Boot 2018.01-00569-g7b4e473-dirty (Apr 22 2019 - 17:17:31 +0400)

CPU  : AM335X-GP rev 2.1
Model: TI AM335x BeagleBone Black
DRAM:  256 MiB
NAND:  0 MiB
MMC:   OMAP SD/MMC: 0, OMAP SD/MMC: 1
*** Warning - bad CRC, using default environment

<ethaddr> not set. Validating first E-fuse MAC
Net:   Could not get PHY for cpsw: addr 0
cpsw, usb_ether
Hit any key to stop autoboot:  0
=> boot
switch to partitions #0, OK
mmc0 is current device
SD/MMC found on device 0
** Unable to read file boot.scr **
** Unable to read file uEnv.txt **
switch to partitions #0, OK
mmc0 is current device
Scanning mmc 0:1...
30039 bytes read in 6 ms (4.8 MiB/s)
switch to partitions #0, OK
mmc0 is current device
SD/MMC found on device 0
data abort
pc : [<8ff6c0bc>]          lr : [<8ff6c0af>]
reloc pc : [<8082e0bc>]    lr : [<8082e0af>]
sp : 8df14e18  ip : 00000000     fp : 0000000c
r10: 00000001  r9 : 8df1ded8     r8 : 8ffbb92c
r7 : 00000000  r6 : 00001000     r5 : 00007c00  r4 : 00000081
r3 : 00000003  r2 : 000003b2     r1 : 00000081  r0 : 8ffbb8c8
Flags: nzCv  IRQs off  FIQs on  Mode SVC_32
Resetting CPU ...
resetting ...

Hello J,

I can run my BBB with the same setting as in your am335x_evm_defconfig file and the U-Boot environment variables.

Can you enter these commands one by one on your board and tell me on which command the data abort occurs?

run findfdt;
run init_console;
setenv mmcdev 0;
setenv bootpart 0:2 ;
mmc dev ${mmcdev};
setenv devnum ${mmcdev};
setenv devtype mmc;
mmc rescan;
run loadimage;
run args_mmc;
run loadfdt;
bootz ${loadaddr} - ${fdtaddr};

Best regards,
Kemal

Hello Kemal,

Thank you for your reply.
I did the test and the output is at the bottom of this post.
It is like it has trouble reading from the SD card. If I give loadimage, it is reading the file 'zImage' from the boot partition, right?

I did 2 attempts and the 'bad device mmc 0' is not always visible.


FIRST ATTEMPT

U-Boot SPL 2018.01-00569-g7b4e473-dirty (Apr 22 2019 - 20:07:08)
Trying to boot from MMC1
*** Warning - bad CRC, using default environment

U-Boot 2018.01-00569-g7b4e473-dirty (Apr 22 2019 - 20:07:08 +0400)

CPU : AM335X-GP rev 2.1
Model: TI AM335x BeagleBone Black
DRAM: 256 MiB
NAND: 0 MiB
MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
** Bad device mmc 0 **
Using default environment

<ethaddr> not set. Validating first E-fuse MAC
Net: Could not get PHY for cpsw: addr 0
cpsw, usb_ether
Hit any key to stop autoboot: 0
=> run findfdt;
=> run init_console;
=> setenv mmcdev 0;
=> setenv bootpart 0:2 ;
=> mmc dev ${mmcdev};
switch to partitions #0, OK
mmc0 is current device
=> setenv devnum ${mmcdev};
=> setenv devtype mmc;
=> mmc rescan;
=> run loadimage;
** Bad device mmc 0 **
=> run args_mmc;
** Bad device mmc 0 **
=> run loadfdt;
** Bad device mmc 0 **
=> bootz ${loadaddr} - ${fdtaddr};
data abort
pc : [<8ff4c8be>] lr : [<8ff4c4d9>]
reloc pc : [<8080e8be>] lr : [<8080e4d9>]
sp : 8df156a0 ip : 8ff84a5e fp : 00000004
r10: 8ff9e2ac r9 : 8df1ded8 r8 : 8df211b0
r7 : 00000000 r6 : 00000001 r5 : 20000000 r4 : 8ffa00b0
r3 : 04000000 r2 : 08000000 r1 : 8df146a0 r0 : 000000aa
Flags: nzcv IRQs off FIQs on Mode SVC_32
Resetting CPU ...

resetting ...

SECONDS ATTEMPT

U-Boot SPL 2018.01-00569-g7b4e473-dirty (Apr 22 2019 - 20:07:08)
Trying to boot from MMC1
*** Warning - bad CRC, using default environment


U-Boot 2018.01-00569-g7b4e473-dirty (Apr 22 2019 - 20:07:08 +0400)

CPU  : AM335X-GP rev 2.1
Model: TI AM335x BeagleBone Black
DRAM:  256 MiB
NAND:  0 MiB
MMC:   OMAP SD/MMC: 0, OMAP SD/MMC: 1
*** Warning - bad CRC, using default environment

<ethaddr> not set. Validating first E-fuse MAC
Net:   Could not get PHY for cpsw: addr 0
cpsw, usb_ether
Hit any key to stop autoboot:  0
=>
=> run findfdt;
=> run init_console;
=> setenv mmcdev 0;
=> setenv bootpart 0:2 ;
=> mmc dev ${mmcdev};
switch to partitions #0, OK
mmc0 is current device
=> setenv devnum ${mmcdev};
=> setenv devtype mmc;
=> mmc rescan;
=> run loadimage;
3871232 bytes read in 393 ms (9.4 MiB/s)
=> run args_mmc;
=> run loadfdt;
36805 bytes read in 41 ms (876 KiB/s)
=> bootz ${loadaddr} - ${fdtaddr};
data abort
pc : [<8ff4c8be>]          lr : [<8ff4c4d9>]
reloc pc : [<8080e8be>]    lr : [<8080e4d9>]
sp : 8df156a0  ip : 8ff84a5e     fp : 00000004
r10: 8ff9e2ac  r9 : 8df1ded8     r8 : 8df27140
r7 : 00000000  r6 : 00000001     r5 : 20000000  r4 : 8ffa00b0
r3 : 04000000  r2 : 08000000     r1 : 8df146a0  r0 : 000000aa
Flags: nzcv  IRQs off  FIQs on  Mode SVC_32
Resetting CPU ...

resetting ...

So no matter is the kernel image loaded or not this data abort occurs. I suspect that the error can be oscillator or RTC related. What oscillator and RTC you used on your design? Can you comment out the #define CONFIG_BOOTCOUNT_AM33XX in include/configs/am335x_evm.h file and check if the board boots?

Hmm, interesting. Can that cause issues on reading from SD card as well?

I did a little stress test from the MLO with a home made external DDR writing/reading. I noticed, when I use a FOR loop to write/read to external DDR from 0x80000000 for 256MB long, from address 0x81FFF7FC multiple addresses are getting written at the same time.
What I did was connect my JTAG, then when it reaching address 0x81FFF7FC to write to I just step through the program, then I see multiple adreses in the memory browser being updated at one write command. Not sure if the procedure I test in my script is OK. But if I write manually to the addresses in CCC, then it looks ok. The DDR test with the GEL from TI website turns out OK.
Everything below this address work perfect in a fast loop, reading and writing. No data error. Not sure if I do it wrong in this test.
So when I run this ddr test in the SPL the CPU is just hanging and goes to:  /* hang and never return */   It is a little weird if I am only writing to external DDR..
ddrtest_spl.patch.zip

I commented out the define you mentioned, but it did not make any difference. I have to say that the AutoBoot counter was still counting down after commenting out the define.

For 24MHz OSC I use farnell number 1841952:

For RTC I use farnell number 1652572:

Have you run the DDR diagnostic script on your board so far? If not, can you run it and attach the results? You can find the script in this post.

I did not know it exist.

Here is the output. It says that the EMIF clock is not enabled, but I tried that over the GEL file, did not work out I think.

Skipping read of EMIF registers since EMIF clock disabled.
 * EMIF registers are not readable when in DS0 state
 * If you are attempting to enter DS0 this is normal.

************************
*** IOCTRL Registers ***
************************

CONTROL: DDR_CMD0_IOCTRL = 0x00000000
  * ddr_ba2 Pullup/Pulldown disabled
  * ddr_wen Pullup/Pulldown disabled
  * ddr_ba0 Pullup/Pulldown disabled
  * ddr_a5 Pullup/Pulldown disabled
  * ddr_ck Pullup/Pulldown disabled
  * ddr_ckn Pullup/Pulldown disabled
  * ddr_a3 Pullup/Pulldown disabled
  * ddr_a4 Pullup/Pulldown disabled
  * ddr_a8 Pullup/Pulldown disabled
  * ddr_a9 Pullup/Pulldown disabled
  * ddr_a6 Pullup/Pulldown disabled
  * Bits 9:5 control ddr_ck and ddr_ckn
    - Slew fastest
    - Drive Strength 5 mA
  * Bits 4:0 control ddr_ba0, ddr_ba2, ddr_wen, ddr_a[9:8], ddr_a[6:3]
    - Slew fastest
    - Drive Strength 5 mA
CONTROL: DDR_CMD1_IOCTRL = 0x00000000
  * ddr_a15 Pullup/Pulldown disabled
  * ddr_a2 Pullup/Pulldown disabled
  * ddr_a12 Pullup/Pulldown disabled
  * ddr_a7 Pullup/Pulldown disabled
  * ddr_ba1 Pullup/Pulldown disabled
  * ddr_a10 Pullup/Pulldown disabled
  * ddr_a0 Pullup/Pulldown disabled
  * ddr_a11 Pullup/Pulldown disabled
  * ddr_casn Pullup/Pulldown disabled
  * ddr_rasn Pullup/Pulldown disabled
  * Bits 4:0 control ddr_15, ddr_a[12:10], ddr_a7, ddr_a2, ddr_a0, ddr_ba1, ddr_casn, ddr_rasn
    - Slew fastest
    - Drive Strength 5 mA
CONTROL: DDR_CMD2_IOCTRL = 0x00000000
  * ddr_cke Pullup/Pulldown disabled
  * ddr_resetn Pullup/Pulldown disabled
  * ddr_odt Pullup/Pulldown disabled
  * ddr_a14 Pullup/Pulldown disabled
  * ddr_a13 Pullup/Pulldown disabled
  * ddr_csn0 Pullup/Pulldown disabled
  * ddr_a1 Pullup/Pulldown disabled
  * Bits 4:0 control ddr_cke, ddr_resetn, ddr_odt, ddr_csn0, ddr_[a14:13], ddr_a1
    - Slew fastest
    - Drive Strength 5 mA
CONTROL: DDR_DATA0_IOCTRL = 0x00000000
  * ddr_d8 Pullup/Pulldown disabled
  * ddr_d9 Pullup/Pulldown disabled
  * ddr_d10 Pullup/Pulldown disabled
  * ddr_d11 Pullup/Pulldown disabled
  * ddr_d12 Pullup/Pulldown disabled
  * ddr_d13 Pullup/Pulldown disabled
  * ddr_d14 Pullup/Pulldown disabled
  * ddr_d15 Pullup/Pulldown disabled
  * ddr_dqm1 Pullup/Pulldown disabled
  * ddr_dqs1 and ddr_dqsn1 Pullup/Pulldown disabled
  * Bits 9:5 control ddr_dqs1, ddr_dqsn1
    - Slew fastest
    - Drive Strength 5 mA
  * Bits 4:0 control ddr_d[15:8], ddr_dqm1
    - Slew fastest
    - Drive Strength 5 mA
CONTROL: DDR_DATA1_IOCTRL = 0x00000000
  * ddr_d0 Pullup/Pulldown disabled
  * ddr_d1 Pullup/Pulldown disabled
  * ddr_d2 Pullup/Pulldown disabled
  * ddr_d3 Pullup/Pulldown disabled
  * ddr_d4 Pullup/Pulldown disabled
  * ddr_d5 Pullup/Pulldown disabled
  * ddr_d6 Pullup/Pulldown disabled
  * ddr_d7 Pullup/Pulldown disabled
  * ddr_dqm0 Pullup/Pulldown disabled
  * ddr_dqs0 and ddr_dqsn0 Pullup/Pulldown disabled
  * Bits 9:5 control ddr_dqs0, ddr_dqsn0
    - Slew fastest
    - Drive Strength 5 mA
  * Bits 4:0 control ddr_d[7:0], dqm0
    - Slew fastest
    - Drive Strength 5 mA
CONTROL: DDR_IO_CTRL = 0x00000000
  * Bit 31: DDR_RESETn controlled by EMIF.
  * Bit 28 (mddr_sel) configured for SSTL, i.e. DDR2/DDR3/DDR3L operation.
CONTROL: VTP_CTRL = 0x00000000
  * VTP disabled (expected in DS0).
CONTROL: VREF_CTRL = 0x00000000
  * VREF supplied externally (typical).
CONTROL: DDR_CKE_CTRL = 0x00000000
  * CKE gated (forces pin low).

Hello Brad,

No problem at all.

Here is the file with the output, as it is DDR we talk about I added my DDR configuration as well:  5808.DDR.zip

I don't know what to read from this output to be honest.

What is the full orderable part number of your DDR2 IC (be sure to include speed grade)?

Hello Brad,

Thank you. The product name is:

MT47H128M16RT-25E:C -  SDRAM, DDR2, 128M x 16bit, 2.5ns, FBGA-84

Specs:

VDD = 1.8V ±0.1V, VDDQ = 1.8V ±0.1V
JEDEC-standard 1.8V I/O (SSTL_18-compatible)
Differential Data Strobe (DQS, DQS#) Option
4n-bit Pre-fetch Architecture
Duplicate Output Strobe (RDQS) Option for x8
DLL to Align DQ and DQS Transitions with CK
8 Internal Banks for Concurrent Operation
Programmable CAS Latency (CL)
Posted CAS Additive Latency (AL)
WRITE Latency = READ Latency - 1 tCK
4 or 8 Programmable Burst Length
Adjustable Data-output Drive Strength
64ms, 8192-cycle Refresh
On-die Termination (ODT)
Supports JEDEC Clock Jitter Specification

Link to the product:

Datasheet:
2221262.pdf

Hello Brad,

Thanks a lot. I will do those tests onight. Now local time is 7:22 am, from 7pm I will go through it all. Thank you.

Hello Brad,

Here is the rd1 file. My scope is only 25MHz, I doubt it will be sufficient.
am335x-ctt_2019-04-25_174609.rd1.zip

Here are the u-boot changes. You will see added code for a DDR test in 'SPL.c' but it is not called. If I perform this test it hangs around 0x81FFF7FC and u-boot goes to interrupt vector HANG.
all_diff.patch.zip

I did a little test with the debugger. I had u-boot initialized the DDR and I checked the memory browser. From 0x80000000 scrolling down a lot everything is fine. The data sticks.
Then I went to almost the end of the memory (0x8F424000) then I scrolled up. I am able to write the data and it sticks. Sometimes I could see an address changing its value there, but very rare.

J E said:

Here is the rd1 file. My scope is only 25MHz, I doubt it will be sufficient.
(Please visit the site to view this file)

The rd1 file shows you have the DDR2 interface configured for 266 MHz operation.  That looks ok.

J E said:

Then I went to almost the end of the memory (0x8F424000) then I scrolled up. I am able to write the data and it sticks. Sometimes I could see an address changing its value there, but very rare.

That's concerning.  Can you test that again, but this time maximize the memory window so you're looking at a lot more addresses?  Do you see any red?  If so, can you tell which bit(s) flipped?

When I do see it happening (red registers) on different places then it is this bit, in hex:  0x00000004
It is not happening often. To give an impression what I mean by not often, I made video's attached below.

Here is a movie from when I boot from SD card and I halt the program over J-Tag (no data flipping):
1346.Boot from SD card.zip

Here is a movie from when I boot from program that is loaded from J-Tag and I halt the program over J-Tag (data is flipping):
Boot from Jtag SPL.zip

I could not find how to make a skew report in Eagle Layout 7.7.0. The trace lengths I have.
Below the screenshot of the trace lengths and also the signal D2 from my board which I just spotted to have a very sharp corner. No other signal has it like this, for this signal I did not notice it sadly.

I would like to understand, the 2 data buses, are they each for one range of memory? Or are they always working parallel together for any address in the memory. Because I am wondering if this would only give a problem in the highest memory part of the DDR. When U-Boot tries to start in that case I expect it to at least start the kernel.

I am going to try what you mentioned and see what happens.

I have tested the new values you mentioned and I do not see any difference.

I also tried using the GEL file and scrolled a bit longer through the memory browser. I have seen that also 0x00040000 was swapping. I have not seen 0x00040000 and 0x00000004 both at the same time . This is with old and new DDR settings. If I look at my board design DDR_A2 does not have any sharp corners.
Very strange.

Is it an idea to check to reduce the clock speed to 133MHz to see if that will give any more stable result. If so, can you help me tune it that way? For the ratio sheet it is easy, but register calc is a bit more tricky.
Thanks a lot

J E said:

I have not seen 0x00040000 and 0x00000004 both at the same time .

The physical bus is only 16 bits wide, so when you're looking at 32-bit words the upper and lower half correspond to the same bits of the bus.  In other words, both corruptions shown above relate to ddr_d2.  It might be simpler to understand if you configure the window in a 16-bit data mode.  That way the data width will match the bus width.

J E said:

Is it an idea to check to reduce the clock speed to 133MHz to see if that will give any more stable result.

Yes, that's what I was going to suggest next.  The main thing is just to change the DPLL frequency.  Slowing down the clock in general will make all the parameters longer (more conservative).  The one exception is the refresh rate which is a "max" time and not a "min" time.  So change your refresh register from 0x81A to 0x40D.

I have tried it, and I don't see any difference. This badboy keeps flipping. Maybe the trace on the board is not even good for 133MHz.

#define  DATA_PHY_FIFO_WE_SLAVE_RATIO    0xD0 //0xE1(266MHz)  0xD0(133MHz)
#define  DATA_PHY_WR_DQS_SLAVE_RATIO    0x7F //0x7E(266MHz)  0x7F(133MHz)
#define DDR2_REF_CTRL                                        0x0000040D  //0x0000081A(266MHz)   0x0000040D(133MHz)

I have added the RD1, can you please check if the change actually worked? I initiated and tested with a GEL file that I updated.
am335x-ctt_2019-04-25_232806.rd1.zip

The view in 16-bit is more clear now. I understand now and is much better in viewing and I only see 0x0004 flipping.

Hello,

I like your script for the DDR analysis. Very convenient to see the registers set-up.

I have put the GEL file in 100MHz. The result is that I see these 2 bits flipping now (16-bit format window):  0x0004  0x0001.  I don't see anything odd on my board for trace D0.
If I write 0xDDDD into the registers then the values are not flipping at all. If I put the original value back, then it starts flipping again.
I made a small screen cast of it, initiated by the GEL file:
100MHz_memory_window.zip

The RD1 file at 100 MHz:
am335x-ctt_2019-04-26_114446_(100MHz).rd1.zip

The DDR analysis at 100MHz:

CONTROL: device_id = 0x2b94402e
  * AM335x family
  * Silicon Revision 2.1

CONTROL: control_status = 0x0040033c
  * SYSBOOT[15:14] = 01b (24 MHz)
CM_CLKSEL_DPLL_DDR = 0x00010a17
  * DPLL_MULT = 266 (x266)
  * DPLL_DIV = 23 (/24)
CM_DIV_M2_DPLL_DDR = 0x00000201
  * CLKST = 1: M2 output clock enabled
  * DIVHS = 1 (/1)

DPLL_DDR Summary
 -> F_input = 24 MHz
 -> CLKOUT_M2 = DDR_PLL_CLKOUT = 266 MHz

EMIF: SDRAM_CONFIG = 0x41805332
  * Bits 31:29 (reg_sdram_type) set for DDR2
  * Bits 28:27 (reg_ibank_pos) set to 0
  * Bits 26:24 (reg_ddr_term) set for 75 Ohm (001b)
  * Bit  23    (reg_ddr2_ddqs) set to differential DQS.
  * Bits 19:18 (reg_sdram_drive) set for normal drive (00b)
  * Bits 15:14 (reg_narrow_mode) set to 1 -> 16-bit EMIF interface
  * Bits 13:10 (reg_cl) set to 4 -> CL = 4
  * Bits 09:07 (reg_rowsize) set to 6 -> 15 row bits
  * Bits 06:04 (reg_ibank) set to 3 -> 8 banks
  * Bits 02:00 (reg_pagesize) set to 2 -> 10 column bits

EMIF: PWR_MGMT_CTRL = 0x00000000
 * ERROR: Bits 7:4 (reg_sr_tim) are in violation of Maximum Self-Refresh Command Limit
 * Please see the silicon errata for more details.

DDR PHY: DDR_PHY_CTRL_1 = 0x00000006
  * WARNING: reg_phy_enable_dynamic_pwrdn disabled.
  * Bits 9:8 (reg_phy_rd_local_odt) to 0 -> no termination
  * Bits 4:0 (reg_read_latency) set to 6 -> Ok: CL+2 is typical with PHY_INVERT_CLKOUT=1.

*********************
*** Register Dump ***
*********************

*(0x4c000000) = 0x40443403
*(0x4c000004) = 0x40000004
*(0x4c000008) = 0x41805332
*(0x4c00000c) = 0x00000000
*(0x4c000010) = 0x0000030c
*(0x4c000014) = 0x0000030c
*(0x4c000018) = 0x0666a391
*(0x4c00001c) = 0x0666a391
*(0x4c000020) = 0x143631ca
*(0x4c000024) = 0x143631ca
*(0x4c000028) = 0x0000033f
*(0x4c00002c) = 0x0000033f
*(0x4c000038) = 0x00000000
*(0x4c00003c) = 0x00000000
*(0x4c000054) = 0x00ffffff
*(0x4c000058) = 0x8000140a
*(0x4c00005c) = 0x00021616
*(0x4c000080) = 0x00000000
*(0x4c000084) = 0x00000000
*(0x4c000088) = 0x00010000
*(0x4c00008c) = 0x00000000
*(0x4c000090) = 0x69eda095
*(0x4c000098) = 0x00050000
*(0x4c00009c) = 0x00050000
*(0x4c0000a4) = 0x00000000
*(0x4c0000ac) = 0x00000000
*(0x4c0000b4) = 0x00000000
*(0x4c0000bc) = 0x00000000
*(0x4c0000c8) = 0x00000000
*(0x4c0000d4) = 0x00000000
*(0x4c0000d8) = 0x00000000
*(0x4c0000dc) = 0x00000000
*(0x4c0000e4) = 0x00000006
*(0x4c0000e8) = 0x00000006
*(0x4c000100) = 0x00000000
*(0x4c000104) = 0x00000000
*(0x4c000108) = 0x00000000
*(0x4c000120) = 0x00000305

************************
*** IOCTRL Registers ***
************************

CONTROL: DDR_CMD0_IOCTRL = 0x0000018b
  * ddr_ba2 Pullup/Pulldown disabled
  * ddr_wen Pullup/Pulldown disabled
  * ddr_ba0 Pullup/Pulldown disabled
  * ddr_a5 Pullup/Pulldown disabled
  * ddr_ck Pullup/Pulldown disabled
  * ddr_ckn Pullup/Pulldown disabled
  * ddr_a3 Pullup/Pulldown disabled
  * ddr_a4 Pullup/Pulldown disabled
  * ddr_a8 Pullup/Pulldown disabled
  * ddr_a9 Pullup/Pulldown disabled
  * ddr_a6 Pullup/Pulldown disabled
  * Bits 9:5 control ddr_ck and ddr_ckn
    - Slew slow
    - Drive Strength 9 mA
  * Bits 4:0 control ddr_ba0, ddr_ba2, ddr_wen, ddr_a[9:8], ddr_a[6:3]
    - Slew slow
    - Drive Strength 8 mA
CONTROL: DDR_CMD1_IOCTRL = 0x0000018b
  * ddr_a15 Pullup/Pulldown disabled
  * ddr_a2 Pullup/Pulldown disabled
  * ddr_a12 Pullup/Pulldown disabled
  * ddr_a7 Pullup/Pulldown disabled
  * ddr_ba1 Pullup/Pulldown disabled
  * ddr_a10 Pullup/Pulldown disabled
  * ddr_a0 Pullup/Pulldown disabled
  * ddr_a11 Pullup/Pulldown disabled
  * ddr_casn Pullup/Pulldown disabled
  * ddr_rasn Pullup/Pulldown disabled
  * Bits 4:0 control ddr_15, ddr_a[12:10], ddr_a7, ddr_a2, ddr_a0, ddr_ba1, ddr_casn, ddr_rasn
    - Slew slow
    - Drive Strength 8 mA
CONTROL: DDR_CMD2_IOCTRL = 0x0000018b
  * ddr_cke Pullup/Pulldown disabled
  * ddr_resetn Pullup/Pulldown disabled
  * ddr_odt Pullup/Pulldown disabled
  * ddr_a14 Pullup/Pulldown disabled
  * ddr_a13 Pullup/Pulldown disabled
  * ddr_csn0 Pullup/Pulldown disabled
  * ddr_a1 Pullup/Pulldown disabled
  * Bits 4:0 control ddr_cke, ddr_resetn, ddr_odt, ddr_csn0, ddr_[a14:13], ddr_a1
    - Slew slow
    - Drive Strength 8 mA
CONTROL: DDR_DATA0_IOCTRL = 0x0000018b
  * ddr_d8 Pullup/Pulldown disabled
  * ddr_d9 Pullup/Pulldown disabled
  * ddr_d10 Pullup/Pulldown disabled
  * ddr_d11 Pullup/Pulldown disabled
  * ddr_d12 Pullup/Pulldown disabled
  * ddr_d13 Pullup/Pulldown disabled
  * ddr_d14 Pullup/Pulldown disabled
  * ddr_d15 Pullup/Pulldown disabled
  * ddr_dqm1 Pullup/Pulldown disabled
  * ddr_dqs1 and ddr_dqsn1 Pullup/Pulldown disabled
  * Bits 9:5 control ddr_dqs1, ddr_dqsn1
    - Slew slow
    - Drive Strength 9 mA
  * Bits 4:0 control ddr_d[15:8], ddr_dqm1
    - Slew slow
    - Drive Strength 8 mA
CONTROL: DDR_DATA1_IOCTRL = 0x0000018b
  * ddr_d0 Pullup/Pulldown disabled
  * ddr_d1 Pullup/Pulldown disabled
  * ddr_d2 Pullup/Pulldown disabled
  * ddr_d3 Pullup/Pulldown disabled
  * ddr_d4 Pullup/Pulldown disabled
  * ddr_d5 Pullup/Pulldown disabled
  * ddr_d6 Pullup/Pulldown disabled
  * ddr_d7 Pullup/Pulldown disabled
  * ddr_dqm0 Pullup/Pulldown disabled
  * ddr_dqs0 and ddr_dqsn0 Pullup/Pulldown disabled
  * Bits 9:5 control ddr_dqs0, ddr_dqsn0
    - Slew slow
    - Drive Strength 9 mA
  * Bits 4:0 control ddr_d[7:0], dqm0
    - Slew slow
    - Drive Strength 8 mA
CONTROL: DDR_IO_CTRL = 0x00000000
  * Bit 31: DDR_RESETn controlled by EMIF.
  * Bit 28 (mddr_sel) configured for SSTL, i.e. DDR2/DDR3/DDR3L operation.
CONTROL: VTP_CTRL = 0x00000067
  * VTP not disabled (expected in normal operation, but not DS0).
CONTROL: VREF_CTRL = 0x00000000
  * VREF supplied externally (typical).
CONTROL: DDR_CKE_CTRL = 0x00000001
  * CKE controlled by EMIF (normal/ungated operation).

The settings:
DDR2_REF_CTRL                                           0x30C            //0x81A(266MHz)     0x40D(133MHz)    0x30C(100MHz)
DATA_PHY_WR_DQS_SLAVE_RATIO        0x7F               //0x7E(266MHz)       0x7F(133MHz)       0x7F(100MHz)
DATA_PHY_FIFO_WE_SLAVE_RATIO        0xCC              //0xE1(266MHz)       0xD0(133MHz)      0xCC(100MHz)

Question, is the tool you are loading the RD1 file at available for public?

Your 100 MHz dump indicates the DDR is still running at 266 MHz. The tool I used earlier is called Clock Tree Tool. However, I now do the DDR DPLL analysis directly in the script to avoid needing multiple scripts and tools.

Tell me more about the DDR data signals. Are the signals directly connected or do you have series resistors?  If directly connected then enabling thevenin termination in ddr_phy_ctrl_1 may get things working.

Hmm, that is strange that it is still 266 MHz. I see that clock in the analysis script now, so I can verify myself now.

My trace lines do not have any series resistors on my board. I connect all traces directly, but all trace lines have 2 via's which I checked in design spec what the max size is allowed to be. So all traces have 2 via's to prevent copper lenght/thickkness difference.

I am checking for the register that you mentioned, but I got a bit confused. When I look at the Wiki for AM335x_EMIF_Configuration_tips I do see register 'DDR_PHY_CTRL_1 (@0x4C0000E4)'. And within that register I see 'REG_PHY_RD_LOCAL_ODT' that I can set to '10: Full thevenin load'.
But I do not understand where I can specifically see which bits that are inside the 'DDR_PHY_CTRL_1' register, because the wiki does not specify the length or position of each setting inside the register.

Can you please clarify this for me? Where do you look these details up which bit to set specifically?

J E said:

Can you please clarify this for me? Where do you look these details up which bit to set specifically?

AM335x Technical Reference Manual
http://www.ti.com/lit/spruh73

See Section 7.3.5.33 DDR_PHY_CTRL_1 Register.  Bits 9:8 are the ones you're looking for.  Try setting them to 10b.  Use the script to verify you have set them correctly.  It will tell you "full thevenin termination" when decoding that register if you have done it correctly.

Thank you for the information. I was searching at the DDR datasheet for this before. My mistake.

The solution looks very promising. I have enabled the full ODT and initalized using the GEL file. I have scrolled 5 minutes and did not see any flipping value. Also I can write values and they stick.
Here is the analysis file. Strange thing is that I configure it for 133MHz, but it always keeps working on 266 MHz according to this analysis. I don't know why.

CONTROL: device_id = 0x2b94402e
  * AM335x family
  * Silicon Revision 2.1

CONTROL: control_status = 0x0040033c
  * SYSBOOT[15:14] = 01b (24 MHz)
CM_CLKSEL_DPLL_DDR = 0x00010a17
  * DPLL_MULT = 266 (x266)
  * DPLL_DIV = 23 (/24)
CM_DIV_M2_DPLL_DDR = 0x00000201
  * CLKST = 1: M2 output clock enabled
  * DIVHS = 1 (/1)

DPLL_DDR Summary
 -> F_input = 24 MHz
 -> CLKOUT_M2 = DDR_PLL_CLKOUT = 266 MHz

EMIF: SDRAM_CONFIG = 0x41805332
  * Bits 31:29 (reg_sdram_type) set for DDR2
  * Bits 28:27 (reg_ibank_pos) set to 0
  * Bits 26:24 (reg_ddr_term) set for 75 Ohm (001b)
  * Bit  23    (reg_ddr2_ddqs) set to differential DQS.
  * Bits 19:18 (reg_sdram_drive) set for normal drive (00b)
  * Bits 15:14 (reg_narrow_mode) set to 1 -> 16-bit EMIF interface
  * Bits 13:10 (reg_cl) set to 4 -> CL = 4
  * Bits 09:07 (reg_rowsize) set to 6 -> 15 row bits
  * Bits 06:04 (reg_ibank) set to 3 -> 8 banks
  * Bits 02:00 (reg_pagesize) set to 2 -> 10 column bits

EMIF: PWR_MGMT_CTRL = 0x00000000
 * ERROR: Bits 7:4 (reg_sr_tim) are in violation of Maximum Self-Refresh Command Limit
 * Please see the silicon errata for more details.

DDR PHY: DDR_PHY_CTRL_1 = 0x00000206
  * WARNING: reg_phy_enable_dynamic_pwrdn disabled.
  * Bits 9:8 (reg_phy_rd_local_odt) to 2 -> full thevenin termination
  * Bits 4:0 (reg_read_latency) set to 6 -> Ok: CL+2 is typical with PHY_INVERT_CLKOUT=1.

*********************
*** Register Dump ***
*********************

*(0x4c000000) = 0x40443403
*(0x4c000004) = 0x40000004
*(0x4c000008) = 0x41805332
*(0x4c00000c) = 0x00000000
*(0x4c000010) = 0x0000040d
*(0x4c000014) = 0x0000040d
*(0x4c000018) = 0x0666a391
*(0x4c00001c) = 0x0666a391
*(0x4c000020) = 0x143631ca
*(0x4c000024) = 0x143631ca
*(0x4c000028) = 0x0000033f
*(0x4c00002c) = 0x0000033f
*(0x4c000038) = 0x00000000
*(0x4c00003c) = 0x00000000
*(0x4c000054) = 0x00ffffff
*(0x4c000058) = 0x8000140a
*(0x4c00005c) = 0x00021616
*(0x4c000080) = 0x00000000
*(0x4c000084) = 0x00000000
*(0x4c000088) = 0x00010000
*(0x4c00008c) = 0x00000000
*(0x4c000090) = 0xf45c760b
*(0x4c000098) = 0x00050000
*(0x4c00009c) = 0x00050000
*(0x4c0000a4) = 0x00000000
*(0x4c0000ac) = 0x00000000
*(0x4c0000b4) = 0x00000000
*(0x4c0000bc) = 0x00000000
*(0x4c0000c8) = 0x00000000
*(0x4c0000d4) = 0x00000000
*(0x4c0000d8) = 0x00000000
*(0x4c0000dc) = 0x00000000
*(0x4c0000e4) = 0x00000206
*(0x4c0000e8) = 0x00000206
*(0x4c000100) = 0x00000000
*(0x4c000104) = 0x00000000
*(0x4c000108) = 0x00000000
*(0x4c000120) = 0x00000305

************************
*** IOCTRL Registers ***
************************

CONTROL: DDR_CMD0_IOCTRL = 0x0000018b
  * ddr_ba2 Pullup/Pulldown disabled
  * ddr_wen Pullup/Pulldown disabled
  * ddr_ba0 Pullup/Pulldown disabled
  * ddr_a5 Pullup/Pulldown disabled
  * ddr_ck Pullup/Pulldown disabled
  * ddr_ckn Pullup/Pulldown disabled
  * ddr_a3 Pullup/Pulldown disabled
  * ddr_a4 Pullup/Pulldown disabled
  * ddr_a8 Pullup/Pulldown disabled
  * ddr_a9 Pullup/Pulldown disabled
  * ddr_a6 Pullup/Pulldown disabled
  * Bits 9:5 control ddr_ck and ddr_ckn
    - Slew slow
    - Drive Strength 9 mA
  * Bits 4:0 control ddr_ba0, ddr_ba2, ddr_wen, ddr_a[9:8], ddr_a[6:3]
    - Slew slow
    - Drive Strength 8 mA
CONTROL: DDR_CMD1_IOCTRL = 0x0000018b
  * ddr_a15 Pullup/Pulldown disabled
  * ddr_a2 Pullup/Pulldown disabled
  * ddr_a12 Pullup/Pulldown disabled
  * ddr_a7 Pullup/Pulldown disabled
  * ddr_ba1 Pullup/Pulldown disabled
  * ddr_a10 Pullup/Pulldown disabled
  * ddr_a0 Pullup/Pulldown disabled
  * ddr_a11 Pullup/Pulldown disabled
  * ddr_casn Pullup/Pulldown disabled
  * ddr_rasn Pullup/Pulldown disabled
  * Bits 4:0 control ddr_15, ddr_a[12:10], ddr_a7, ddr_a2, ddr_a0, ddr_ba1, ddr_casn, ddr_rasn
    - Slew slow
    - Drive Strength 8 mA
CONTROL: DDR_CMD2_IOCTRL = 0x0000018b
  * ddr_cke Pullup/Pulldown disabled
  * ddr_resetn Pullup/Pulldown disabled
  * ddr_odt Pullup/Pulldown disabled
  * ddr_a14 Pullup/Pulldown disabled
  * ddr_a13 Pullup/Pulldown disabled
  * ddr_csn0 Pullup/Pulldown disabled
  * ddr_a1 Pullup/Pulldown disabled
  * Bits 4:0 control ddr_cke, ddr_resetn, ddr_odt, ddr_csn0, ddr_[a14:13], ddr_a1
    - Slew slow
    - Drive Strength 8 mA
CONTROL: DDR_DATA0_IOCTRL = 0x0000018b
  * ddr_d8 Pullup/Pulldown disabled
  * ddr_d9 Pullup/Pulldown disabled
  * ddr_d10 Pullup/Pulldown disabled
  * ddr_d11 Pullup/Pulldown disabled
  * ddr_d12 Pullup/Pulldown disabled
  * ddr_d13 Pullup/Pulldown disabled
  * ddr_d14 Pullup/Pulldown disabled
  * ddr_d15 Pullup/Pulldown disabled
  * ddr_dqm1 Pullup/Pulldown disabled
  * ddr_dqs1 and ddr_dqsn1 Pullup/Pulldown disabled
  * Bits 9:5 control ddr_dqs1, ddr_dqsn1
    - Slew slow
    - Drive Strength 9 mA
  * Bits 4:0 control ddr_d[15:8], ddr_dqm1
    - Slew slow
    - Drive Strength 8 mA
CONTROL: DDR_DATA1_IOCTRL = 0x0000018b
  * ddr_d0 Pullup/Pulldown disabled
  * ddr_d1 Pullup/Pulldown disabled
  * ddr_d2 Pullup/Pulldown disabled
  * ddr_d3 Pullup/Pulldown disabled
  * ddr_d4 Pullup/Pulldown disabled
  * ddr_d5 Pullup/Pulldown disabled
  * ddr_d6 Pullup/Pulldown disabled
  * ddr_d7 Pullup/Pulldown disabled
  * ddr_dqm0 Pullup/Pulldown disabled
  * ddr_dqs0 and ddr_dqsn0 Pullup/Pulldown disabled
  * Bits 9:5 control ddr_dqs0, ddr_dqsn0
    - Slew slow
    - Drive Strength 9 mA
  * Bits 4:0 control ddr_d[7:0], dqm0
    - Slew slow
    - Drive Strength 8 mA
CONTROL: DDR_IO_CTRL = 0x00000000
  * Bit 31: DDR_RESETn controlled by EMIF.
  * Bit 28 (mddr_sel) configured for SSTL, i.e. DDR2/DDR3/DDR3L operation.
CONTROL: VTP_CTRL = 0x00000067
  * VTP not disabled (expected in normal operation, but not DS0).
CONTROL: VREF_CTRL = 0x00000000
  * VREF supplied externally (typical).
CONTROL: DDR_CKE_CTRL = 0x00000001
  * CKE controlled by EMIF (normal/ungated operation).

Now I have the following problem. When I configure the full ODT in u-boot, then it crashes. I do not see any print out on my screen and it is going into an interrupt vector to HANG. When I remove the 'full ODT' bit, then u-boot is working.

u-boot settings (I tried 133MHz and 266 MHz):
/* Micron MT47H128M16RT-25E */
#define MT47H128M16RT25E_EMIF_READ_LATENCY    0x206            // The 2 is full ODT for read
#define MT47H128M16RT25E_EMIF_TIM1          0x0666A391
#define MT47H128M16RT25E_EMIF_TIM2          0x143631CA
#define MT47H128M16RT25E_EMIF_TIM3          0x0000033F
#define MT47H128M16RT25E_EMIF_SDCFG         0x41805332
#define MT47H128M16RT25E_EMIF_SDREF         0x81A                         //0x81A(266MHz)   0x40D(133MHz)  0x30C(100MHz)
#define MT47H128M16RT25E_RATIO              0x100
#define MT47H128M16RT25E_INVERT_CLKOUT      0x1
#define MT47H128M16RT25E_RD_DQS             0x40
#define MT47H128M16RT25E_WR_DQS             0x7E                                 //0x7E(266MHz)  0x7F(133MHz)  0x7F(100MHz)
#define MT47H128M16RT25E_PHY_WR_DATA        0xC0
#define MT47H128M16RT25E_PHY_FIFO_WE        0xE1                           //0xE1(266MHz)  0xD0(133MHz)  0xCC(100MHz)
#define MT47H128M16RT25E_IOCTRL_VALUE       0x18B

When I tried with this GEL file settings it worked for reading the DDR:
#define  CMD_PHY_CTRL_SLAVE_RATIO           0x100
#define  CMD_PHY_INVERT_CLKOUT                    0x1
#define  DATA_PHY_RD_DQS_SLAVE_RATIO     0x40
#define  DATA_PHY_FIFO_WE_SLAVE_RATIO    0xD0                          //0xE1(266MHz)  0xD0(133MHz)  0xCC(100MHz)
#define  DATA_PHY_WR_DQS_SLAVE_RATIO     0x7F                          //0x7E(266MHz)  0x7F(133MHz)  0x7F(100MHz)
#define  DATA_PHY_WR_DATA_SLAVE_RATIO    0xC0
#define  DDR_IOCTRL_VALUE                                 (0x18B)
#define DDR2_READ_LATENCY                              0x206         
#define DDR2_SDRAM_TIMING1                             0x0666A391
#define DDR2_SDRAM_TIMING2                           0x143631CA
#define DDR2_SDRAM_TIMING3                             0x0000033F
#define DDR2_SDRAM_CONFIG                              0x41805332
#define DDR2_REF_CTRL                                         0x0000040D         //0x81A(266MHz)   0x40D(133MHz)  0x30C(100MHz)

In your u-boot board.c file do you have code along these lines:

config_ddr(266, &ioregs, &ddr2_data,
&ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);

The highlighted number is the argument that determines the DPLL_DDR frequency.  Try 133 along with your other associated changes.  Mainly it's just the REF_CTRL definition that matters.  Those other numbers are barely changing at all.

This seems to work perfectly. In 133 MHz I don't see any bits flipping and I still use the half ODT. I tested this with u-boot and GEL file.
For some reason full ODT makes u-boot crash. very strange.

Now I have the feeling that he DDR is more under control now. Unless you think different and might require more testing?
I get back to trying to get the kernel loaded. In my am335x_evm_defconfig I have defined the 'CONFIG_BOOTDELAY=5'. When I start my board I do see 2 different behaviors which I before related to an issue with the SD-card. Sometime I get ** Bad device mmc 0 **.

One situation when I power on the board u-boot boot delay is 20 seconds, and another time it is 5 seconds. very strange. When it is the correct 5 seconds it complains about the SD card, when it is the wrong 20 seconds, then it continues reading from SD-Card but fails..

What do you suggest is the next step? before with Kemal we tried things like "broken-cd;" parameter and looking at the oscillator, and I measured the SD-Card communication lines with a scope.

Really thanks a lot for all your support.

u-boot count down timer is 20 seconds.


U-Boot 2018.01-00569-g7b4e473-dirty (Apr 26 2019 - 18:24:49 +0400)

CPU  : AM335X-GP rev 2.1
Model: TI AM335x BeagleBone Black
DRAM:  256 MiB
NAND:  0 MiB
MMC:   OMAP SD/MMC: 0, OMAP SD/MMC: 1
Net:   Could not get PHY for cpsw: addr 0
cpsw, usb_ether
Hit any key to stop autoboot:  0
=> boot
** Unable to read file uEnv.txt **
3871232 bytes read in 393 ms (9.4 MiB/s)
36805 bytes read in 41 ms (876 KiB/s)
## Flattened Device Tree blob at 88000000
   Booting using the fdt blob at 0x88000000
   Loading Device Tree to 8df08000, end 8df13fc4 ... OK

Starting kernel ...

u-boot count down timer is 5 seconds.


U-Boot 2018.01-00569-g7b4e473-dirty (Apr 26 2019 - 18:24:49 +0400)

CPU  : AM335X-GP rev 2.1
Model: TI AM335x BeagleBone Black
DRAM:  256 MiB
NAND:  0 MiB
MMC:   OMAP SD/MMC: 0, OMAP SD/MMC: 1
** Bad device mmc 0 **
Using default environment

<ethaddr> not set. Validating first E-fuse MAC
Net:   Could not get PHY for cpsw: addr 0
cpsw, usb_ether
Hit any key to stop autoboot:  0
switch to partitions #   
SD/MMC found on device 0
** Bad device mmc 0 **
** Bad device mmc 0 **
switch to partitions #0, OK
mmc0 is current device
** Bad device mmc 0 **
** Bad device mmc 0 **
switch to partitions #0, OK
mmc0 is current device
SD/MMC found on device 0
** Bad device mmc 0 **
SD/MMC found on device 1
** Bad device mmc 1 **
## Error: "bootcmd_nand0" not defined
starting USB...
USB0:   Port not available.
using musb-hdrc, OUT ep1out IN ep1in STATUS ep2in
MAC f0:b5:d1:35:19:cc
HOST MAC de:ad:be:ef:00:00
RNDIS ready
missing environment variable: pxeuuid
Retrieving file: pxelinux.cfg/01-f0-b5-d1-35-19-cc
using musb-hdrc, OUT ep1out IN ep1in STATUS ep2in
MAC f0:b5:d1:35:19:cc
HOST MAC de:ad:be:ef:00:00
RNDIS ready

J E said:

This seems to work perfectly. In 133 MHz I don't see any bits flipping and I still use the half ODT. I tested this with u-boot and GEL file.
For some reason full ODT makes u-boot crash. very strange.

At 133 MHz, does it still work well with the DDR_PHY_CTRL_1 read ODT disabled altogether?  Ordinarily ODT is used with DDR3.  Although DDR2 also supports ODT, I can't remember if the TI controller properly supports it for DDR2.  I'm checking with a colleague to see if I can get a more definitive answer.  For now though, a good data point would be to use DDR2 at 133 MHz without any read ODT enabled and see if it works.

J E said:

Now I have the feeling that he DDR is more under control now. Unless you think different and might require more testing?
I get back to trying to get the kernel loaded. In my am335x_evm_defconfig I have defined the 'CONFIG_BOOTDELAY=5'. When I start my board I do see 2 different behaviors which I before related to an issue with the SD-card. Sometime I get ** Bad device mmc 0 **.

I was about to suggest starting a new thread, though I see the topic of this thread is in fact related to the SD card!  So I guess we're back on topic after a HUGE diversion into DDR.  :-)

Are you able to probe the MMC interface to see the signaling?  Do the signals look any different between these two cases (voltage levels, slew rates, etc.)?

A more software-centric approach would be to enable DEBUG either globally or in the MMC driver.  For example, you can add a line to your board header file (e.g. include/configs/am335x_evm.h or similar):

#define DEBUG 1

Please don't post all the output though as it will dump out a TON.  It is better to capture to files so they can be diff'd, etc.

Brad Griffis said:

At 133 MHz, does it still work well with the DDR_PHY_CTRL_1 read ODT disabled altogether?  Ordinarily ODT is used with DDR3.  Although DDR2 also supports ODT, I can't remember if the TI controller properly supports it for DDR2.  I'm checking with a colleague to see if I can get a more definitive answer.  For now though, a good data point would be to use DDR2 at 133 MHz without any read ODT enabled and see if it works.

When I disable the ODT, then I can see at 133 MHz the DDR is also working as it should from the memory browser. So with 266 MHz and ODT it works and 133MHz without ODT it works. I clearly need to fix something at my design for this.

Brad Griffis said:

Are you able to probe the MMC interface to see the signaling?  Do the signals look any different between these two cases (voltage levels, slew rates, etc.)?

My scope is at home and working abroad at the moment, so after 5 days I can measure things with a scope sadly.

Brad Griffis said:

A more software-centric approach would be to enable DEBUG either globally or in the MMC driver.  For example, you can add a line to your board header file (e.g. include/configs/am335x_evm.h or similar):

I have worked with the #DEBUG and it sure give some interesting outputs.

So I have 3 log files now, two are moments where is get stuck, and one is where is eventually is loading and posting all the environment variables. Why it get stuck is unclear for me yet. Before I had the idea that the data from the SD-Card got corrupted perhaps. From that moment the topic jumped to DDR and now we got back here :)

Log file when loading continues and SD card issue is logged:
Debug_SDcard_fail.log

Here is one point where is got stuck, happens very rare:
Debug_Stuck_second_stage.log

Here is another point when it should jump to second stage, but hangs. Happens rare:
Debug_Stuck_Jump_To_Uboot.log

Brad Griffis said:

1. Some kind of power or timing issue related to the MMC interface itself. I think it works when you type in the commands one at a time because there's a lot of time between them. Something suspicious there.

When I type in the commands separately it is not working any better, it still get stuck at starting the kernel. My post referring to what Kemal mentioned earlier might be a little pointless at the moment. Because sometimes when I do not see the SD card issue it is giving the same result.

Brad Griffis said:

2. Something wrong with your kernel or kernel device tree. Is your terminal on UART0? Do the kernel bootargs specify ttyS0?

Where exactly do I verify this?
Also, I don'y trust myself loading the right files to the boot partition at the moment. there is ofcourse the MLO, u-boot.img and the generated u-boot.env, but which other file names would be present, and what would be the source I should take these files from?
The SD-Card I have made using the ./create-sdcard script in the /bin folder, and I have chosen the pre-build image:         2:tisdk-rootfs-image-am335x-evm.tar.xz

Brad Griffis said:

Do you have a 32k clock connected to RTC_XTALIN in your design?

Yes, I do have the RTC XTAL on my board.