TDA3XEVM: [DSS]Abnormal timing of HSYNC vs VSYNC

Hi,

We have configured Display Subsystem module for 1280x720 resolution, 74.25MHz pixel clock  and horizontal/vertical Blanking time according to VESA standards.  

For the above configuration we should be able to observe Hsync toggling data 16ms .But able to observe only for 7.5ms.Please refer to the below screenshot. May we know the reason,

1. Is it because of oscilloscope bandwidth issue?
2. Is it because of capturing waveforms of different frequencies(Lower-Hz and Higher-KHz)?

Additional Info:

Time taken to send one pixel is = 13.5ns

Time taken to send one frame = 1280x720x13.5ns = 15.9ms ~ 16ms

Time taken to send one frame should be equal to the Hsync toggling time(720 times) = 16ms.

Thank you,

Sai Vineel