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Part Number: TDA4VM On the TDA4VM EVM, GPIO0_0 is connected to SW10. See TDA4VM EVM User Guide for SW10 location.
https://www.ti.com/lit/pdf/spruis4
Can SW10 + GPIO0_0 be used to generate an interrupt on TDA4VM A72, with QNX running?
Part Number: SK-AM62
Problem Statement: Customers are facing problems interfacing SoC_I2C2 to external sensors using the User Expansion Connector (J3) .
They are having hardware connections by interfacing sensors with EXP_I2C2_SDA and EXP_I2C2_SCL…
Part Number: TDA4VM In the rti_app_uc(1-4) and the rti_test_app tested on SDK 8.6, 9.0 and 9.1, the interrupt callback is received much before the wait delay in the code sequence. The program does not wait for the callback to be triggered.
Observed…
Part Number: TDA4VM Hello,
We need a CAN example which runs on MCU2_1 with freeRTOS OS along with Linux running on A72 with SPL boot flow and also the CAN instance used in CAN example has to be MCAN0( Main domain CAN0).
SDK version: 9.1
Regards…
Part Number: AM62A7
Could you confirm that the voltage domains are correct for the MMC1_SDCD and MMC1_SDWP pins? The datasheet shows both MMC0 and MMC2 as having all member pins bellowing to the same voltage domain. For MMC1 however, the pins are shown…
Other Parts Discussed in Thread: SYSCONFIG , TDA4VH TI’s SysConfig PinMux Tool is a GUI interface which allows the user to select the desired device pin configurations for their system. The SysConfig PinMux Tool outputs customer-selected configurations…
Part Number: AM623
Team,
A few more questions about decoupling as I couldn’t find anything in the TI documentation regarding some pins of the AM62X:
Do the following pins need their own decoupling capacitors (it doesn’t look like the TI EVM had…
Hi TI Expert,
I am developing on an AM62x SKEVM and an AM64x EVM and I'm planning on using Ethernet. Where do the MAC addresses associated with the Ethernet interfaces on these EVMs originate from? How do I change the MAC addresses?
Part Number: AM6442 Other Parts Discussed in Thread: TMDS64EVM , , SYSCONFIG
I am using a Sitara processor with Linux cores, RTOS cores, and PRU_ICSSG cores (AM64x family). I want to use an RTOS core to control PRU_ICSSG cores, which are being used…
