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Hi,
Please tell me how to use this device and the following to solve the problem I am having with my customer's board.
LMK04821 is used for the following purposes.
DCLKout0: IQ modulator clock (84.384MHz, to FPGA)
SDCLKout1: SYSREF (2.637MHz, to FPGA)
DCLKout2: DACCLK (2025.216MHz, to DAC38RF83)
SDCLKout3: SYSREF (2.637MHz, to DAC38RF83)
Register settings are written in order from register 0
Finally, write 0x03 to Reg0x0139-> Used in Continuous SYSREF mode.
Confirmation details
Q1 : The register settings are written in order from address 0x00, but is there any problem?
Please let me know if there is a procedure.
·also,
Q2 : Is it possible to use it for SYSREF / DACCLK of DAC38RFxx in this mode?
When actually tried, spurious occurs near the 64QAM carrier. It disappears when this mode is stopped.
I don't know how the current continuous SYSREF was used.
The current SYSREF continuous use has spurious issues and should be avoided.
If we stop SYSREF continuous
I'm worried that "out of sync"-> "device will not be able to resync if out of sync".
(I'm sorry. I don't understand the operation of JESD204B well)
Q3 : Please tell me the recommended setting procedure when using this method.
Best regards,
Hiroshi
Hello Hiroshi-san,
Additionally, in order to guarantee the phase alignment of LMK04821 SYSREF is consistent with device clocks, the device clock and SYSREF dividers must be synchronized after programming. Carefully follow the programming instructions in section 9.3.2.1.1 of the datasheet to properly set up SYSREF and device clock delays to meet the DAC's setup and hold times.
Regards,
Derek Payne
Derek-san,
Thank you for your detailed commentary and great support.
Best regards,
Hiroshi