LMK04821: About Continuous SYSREF

Hello Hiroshi-san,

1. Per the datasheet instructions in section 9.5.1, we recommend the sequence below. You must follow this order to ensure that several VCO gain coefficients are properly set, the PLL and VCOs are powered up, and the VCO post-divider is properly programmed if used, otherwise calibration will not be successful and lock over temperature may not be stable.
   1. Program register R0 (0x0) with RESET = 1 initially to restore the device registers to a known state
   2. Program registers in order from R0 (0x0) to R357 (0x165).
   3. Program R369 (0x171) to 0xAA, and program R370 (0x172) to 0x02.
   4. Program register R372 (0x174)
   5. Program registers R358 (0x166) and onward. The repeated registers may be skipped or reprogrammed, whatever is easiest.

   Additionally, in order to guarantee the phase alignment of LMK04821 SYSREF is consistent with device clocks, the device clock and SYSREF dividers must be synchronized after programming. Carefully follow the programming instructions in section 9.3.2.1.1 of the datasheet to properly set up SYSREF and device clock delays to meet the DAC's setup and hold times.

2. JESD204B SYSREF only needs to be established once at initialization. The SYSREF can be enabled in continuous mode temporarily just for lane alignment, then the SYSREF can be disabled to reduce spurious interference. If lane alignment must be repeated in the future, the SYSREF can be re-enabled just for the lane realignment - the LMK04821 SYSREF divider will maintain its phase with respect to the device clocks even when continuous SYSREF mode is not used, as long as the SYSREF divider remains powered on internally (SYSREF_PD=0).
3. Usually the easiest way to set up JESD204B lane alignment is to prepare the data converter to receive a SYSREF signal, then provide one or more SYSREF pulses to perform the lane alignment. LMK04821 supports using a pulsed SYSREF divider in SYSREF pulser mode. The procedure in datasheet section 9.3.2.1.1 explains how to configure the device in pulsed SYSREF mode.

Regards,

Derek Payne