CDCLVC1104: Input Capacitance

Hi Asim,

Regarding the Slew Rate.
Normally the output impedance of the clock source, and the input capacitance of the CLKIN pin create an RC time-constant that slows the input clock edge.
If the design has no overshoot, then there is a "rounding" of the edge as it approaches V_OH (output high) for a rising-transition.

I believe there should be some input voltage range the slew rate is specified for.
For example, the slew rate needs to be 1~4V/ns for the rising/falling edge at is passes the threshold voltage.

The exact threshold voltage varies across PVT, so usually we use the input high/low max-min values to get the range requirements.
Datasheets usually spec the Slew Rate from 20%~80%Vcc to give an idea of the critical slew rate when passing the threshold voltage.

For example, see Table 6.14 in the CDCM6208 datasheet (link) where the output slew rate is specifed for a specific voltage range and load capacitance.

Can you double-check and see what the required input range for the slew rate is? (20%~80%Vcc is typical)

Regarding the minimum pulse width.
Do I understand correctly that whatever the input duty cycle is, the output duty cycle will be the same?

So let's say 25MHz input clock has an ideal 0[ns] rise/fall time.
The pulse width (tpw) for an ideal 50% duty cycle = 20ns (20ns High and Low = 40ns total = 25MHz)
But now let's add some duty cycle error (±10% = 40%~60%) because nothing is ideal.

Now tpw_high = 22[ns] and tpw_low = 18[ns].
Will the output duty cycle be the same as this input duty cycle, or will it be different?

Is there a required input max. duty cycle limit?

Regards,
Darren

Hi Asim,

Just to clarify.

1) The datasheet doesn't list the clock input slew rate as 20~80% of input swing, as your attached image shows.
Where does this come from, and am I safe in understanding this also applies to all cdclvc11xx family devices?

2) I understand the clock buffer is different from a clock generator which reconstructs an output clock using internal PLL, etc.
Because of this, the output duty cycle tracks the input duty cycle, with added degradation due to the pulse width (tpLH - tpHL) skew.

I have attached an excel sheet with some super simple calculations to understand duty cycle degradation.
Is my understanding correct?

For example, considering the following:

VDD = 2.5V
f_in = 125MHz
p_skew = 220ns (because VDD = 2.5V)

Here, assuming 50% input duty cycle, the expected max degradation is ±2.75%, right?

The ±5% you gave in your example above, is because at the "max" conditions:

VDD = 3.3V
f_in = 250MHz
p_skew = 180ns (because VDD = 3.3V)

We get a max duty cycle degradation of ±4.5%, right?
(Can also be confirmed using the attached excel sheet)

duty_cycle_degradation.xlsx

Regards,
Darren