Hi,
We meet a problem: we use two CDCE62005 multistage cascaded, some the 2nd chip's lock signal on the board is unlock.
Our SCH is the same as TI 6678 EVM, using SPI interface from FPGA, and the config file is created from TI software.
We produce a few batch, but the problem appeared from last year. Last year had 2 cases totle, but this year have 7 cases so far.
All unlock problem only happened on the 2nd chip position. And happened on the 2nd position when swapping the chip beteween the 1st and the 2nd.
The 2nd chip can be locked when using the 1st chip config file. This means the circuit of the 2nd chip is faultless.
And the hardware and the config file we used is over 5 years.
We find similar problems on E2E forum, some is 10 years ago, but none had a clear reply.
Please inform us of the possible causes and solutions to the problem.
Thanks.
