LMK04832: Half step dynamic digital delay

Hi Shunya, 
1. 
Yes. 

2. 

SYSREF outputs have their own digital delay & half step options.

3. I am not following what you're asking here? 

Setup and hold times are typically only relevant when the timing relationship between SYSREF & Device clock matters. Meeting setup & hold time matters when sync pin goes low to ensure deterministic reset of PLL2 R divider if attempting PLL2 R divider sync. 

There is also the timing requirements for SDI which has it's own setup and hold time but that is different. 

Regards, 

Vicente

Hi, Vicente

2.3. What I want to ask about is the method of dynamic digital delay and the constraints for CLKin0 and CLKin1.

For example, if the delay is executed based on the VCO, I believe that if CLKin is not input while observing the setup/hold times of the VCO, metastability will occur.

In that case, the constraints are strict, but if the delay is based on SYSREF, the frequency is lower, so I think there is no problem with no care.

On the other hand, if dynamic digital delay is implemented like switching the delay elements ON/OFF, I think timing constraints are unnecessary.

Thanks, 

Shunya

Dynamic digital delay and half-step are implemented as separate features.

Dynamic digital delay substitutes a divide value one greater than the programmed divide value for one full divider period per dynamic digital delay step requested. Dynamic digital delay is triggered by writing the register for the total step count over SPI. The trigger timing is orchestrated automatically by the state machine. I would not describe this as switching delay elements ON/OFF; I would describe it instead as a triggered write, where each time the number of steps is written to the register, the affected output clocks adjust their delay by the number of steps written, where one step is one VCO cycle of delay. In either case, there is no setup/hold time like with a latch. There is naturally a minimum duration for the number of dynamic digital delay steps to take place, since single-cycle substitutions can only happen at most once per divider period - also, I believe each substitution is surrounded by several normal divider cycles to avoid sudden changes in output frequency for long durations, but I'd have to check this on the bench to confirm. There are rarely cases where multiple dynamic digital delay step adjustments need to be triggered in rapid succession, so the duration from register write to dynamic digital delay adjustment complete is not characterized. In case it matters for your application, the duration should be consistent to within ±30% for the same step count, VCO frequency, and divider settings, so a practical duration to wait between triggers could be determined experimentally.

Half-step is implemented like switching the delay elements ON/OFF, for both device clock and SYSREF paths within the output channels. In the device clock, when the half-step is on, the output of the divider is effectively toggled on the VCO falling edge instead of the rising edge, introducing a delay of one-half VCO cycle. The half-step ON/OFF behavior takes effect almost immediately after the SPI write to the register completes, and SPI cannot be written fast enough for there to be any setup/hold constraints or minimum durations between writes.

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There are two outputs to each channel divider, and CLKout0 and CLKout1 share the same divider, delay, and half-step circuitry. If you want to observe the effect of the half step, you should compare CLKout0 or CLKout1 against an output at the same frequency and phase on a separate channel divider.

Hi, Vicente

Thank you. I understand for the most part. If it is possible to dynamically turn the half-clock delay ON/OFF by writing to DCLKX_Y_HS, then there is no problem at all.

>Half-step is implemented like switching the delay elements ON/OFF, for both device clock and SYSREF paths within the output channels. In the device clock, >when the half-step is on, the output of the divider is effectively toggled on the VCO falling edge instead of the rising edge, introducing a delay of one-half >VCO cycle. The half-step ON/OFF behavior takes effect almost immediately after the SPI write to the register completes, and SPI cannot be written fast >enough for there to be any setup/hold constraints or minimum durations between writes.

In the method mentioned above, it is said that toggling occurs on the falling edge of the clock. In that case, I wonder if setup and hold times would occur during the toggle. I would be glad if they are not necessary, but is my understanding incorrect?

Hi, Vicente 

The reason I am concerned about the setup/hold of CLKin is that I believe the direction of phase delay might become uncertain.

I am worried whether the data phase of CLKin0 and 1 will move in a single direction when dynamically switching the half-clock delay ON/OFF by writing to DCLKX_Y_HS.

For example, when the half-clock delay is turned ON at 2.5GSPS, I intuitively think the CLKin signal will be delayed by 200ps. Similarly, when it is turned OFF, I think it will advance by 200ps.

If this is the case, there is no problem at all. However, if the function of DCLKX_Y_HS is "only shifting the phase by 180° with the time direction being uncertain," then we cannot use this device for our application.

Is there no need to worry about the above concern?

Thanks,

Shunya