LMK05028: LMK05028 OUT-DELAY IN TICS PRO SIMULATION

Hello Kyle Yamabe,

We are majorly generating 2 outputs CKSYNC (312.5M) and SYSREF(156.25M) in LMK05028,  And I need delay for SYSREF, it should start rising at the CKSYNC  falling edge, as shown in attached image. For that i need delay for LMK05028 outputs.

I am not able to generate all the required frequencies with other parts in TICS PRO, But,the LMK05028  part it is possible to generate all the required frequencies in TICS PRO. The CKSYNC and SYSREF is not a stable frequency,It will be changing depends upon the sampling frequency.

For this LMK5C33216A it is possible to disable PLL1 P1 (or) PLL1 P2 & PLL2 P1 dividers or create the division of 1 in PLL1 P1 &PLL2 P1 in TICS PRO Tool.

Hello Sarathi,

What is your frequency plan? The LMK5B33216 will work with generating both a 312.5MHz and 156.25MHz outputs. The LMK5B33216 has a BAW frequency of 2500MHz which is integer related to 312.5MHz and 156.25MHz and will give you the best performance. Since the difference between the LMK5B33216 and the LMK5C33216A is the different BAW frequencies the LMK5B33216 would work best based off of these two output frequencies.

For both the LMK5B33216 and LMK5C33216A you can toggle off the PLL1_PRI_DIV_EN which will disable that APLL post divider but it is not the same as dividing by 1 because you will not get an output from that divider.

Hello Kyle Yamabe,

Due to the confidential nature of our frequency plan, I cannot share the specifics in an open forum. Could we continue this conversation via email? Please share the email address, and I will send all the details.