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Tool/software:
Setups:,
In case of two LMK04832, where one in single loop 0-delay mode (master) and another in distribution mode (slave) with CLKin1 used on both.
1. master get 100MHz REF IN while slave get A output clock from the master, for example CLKout8 at 156.25MHz
2. both master and slave get the same SYNC signal from the pin
Questions:
1. was it feasible to have both Device clock and SYSREF outputs aligned from both master and slave?
2. was there any registers settings in particular need to be done in this setup?
Thank you.
Please see the SCH about PLL. the CLKIN0 is connected to an 100M OSC and OSCin from an onboard 100M VCXO.
It was reviewed in 2021 by TI.
We use CLKin1 and do not use CLKIN0 nor OSCin because we need distribution mode beside single loop.
About PLL SYNC pin, it's connected to either external or the FPGA via a OR gate.
When from FPGA, the SYNC signal can be from external source via another connector and re-timed inside FPGA.
PLL OSCout can be from FBMUX.
Actually, I got it work about half year ago with SYNC_POL and could not reproduce it now with same FPGA and PLL registers.
Thank you very much.
Hi Michael,
#1
I did the same routine as above and also below, which is from TICS Pro v1.7.7.9.
The SYSREF outputs are still not aligned before and after toggling the PLL SYNC pin. I have a question about register 0x44, why was it set to 0x80 not 0xFF?
0x010200,
0x0144FE,
0x010200,
0x0144FE,
0x010A00,
0x0144FC,
0x010A00,
0x0144FC,
0x011200,
0x0144F8,
0x011200,
0x0144F8,
0x011a00,
0x0144F0,
0x011a00,
0x0144F0,
0x012200,
0x0144E0,
0x012200,
0x0144E0,
0x012A00,
0x0144C0,
0x012A00,
0x0144C0,
0x013200,
0x014480,
0x013200,
0x014480
#2
I have also tested with SYSREF as the feedback clock at 1.25MHz and 3.125MHz plus set SYSRED DDLY_PD to '1'. The phases are still not aligned.
Thank you very much.
#3
1. Please attached SYSREF from two boards.
2. The phase delta is the same before and after toggling the PLL SYNC.
3. The same PLL SYNC signal to both boards.
4. However, the phase delta differs on each time programming the PLL.
Thank you very much.
Hi Vicente,
1. Please see below the diagram, where one PLL per board.
2. The tcs file is attached too. Which indicate one of the configuration I'm currently testing.
The PLL will be in single loop 0-delay mode that will get the same 100MHz clock reference (phase aligned) to CLKin1.
There is no master or slave relationship.
Thank you very much.
Hi New2day,
There is no master or slave relationship.
You say this - so you simply require the second device to operate as a buffer.
You only care about the master device having its output sync'd - is that correct?
I see you have a 100MHz VCXO - I assume CPout1 is driving that correct?
I see you're setting the SYSREF divider as the feedback.
Can you try setting CLKOUT6 as the feedback?
This will make one of the 100MHz outputs will be fed back to a 100MHz PFD.
You can still use the outputs - the feedback happens internally.
In the configuration you provide you have all sync disable bits enabled.
So, in other words, you're preventing all OUTPUTS and the SYSREF divider from SYNC itself.
Try this new configuration I provided.
A sync event should now give you deterministic phase.
Are you using an EVM + TICSpro or your own board and custom controller?
Best regards,
Vicente
Hi New2day,
1. Understood - all you want is two LMK04832 operating in single loop ZDM mode with phase aligned outputs.
If you could share a clock tree that would be extremely helpful. From the schematic you showed I have no idea how these two boards are connected together or whether they share a reference you you require outputs on both to be deterministic in regards to the ref clk.
2.
I've tried with both CLKout6 and CLKout8 as FB clock. Could not get SYSREF outputs aligned nor CLKout10/CLKout12.
When you tried both of these - after performing a sync event would you have deterministic phase?
Many times your outputs will not be phase aligned due to external factors such as prop delay on board due to layout.
A sync event would be successful if every time you had deterministic phase - not necessarily aligned rising edges.
I utilized CLKOU8 as FB_MUX and was able to get deterministic phase every time between DCLKOUT & SYSREF.
Now they are not edge aligned but you can use the digital delays to account for this.
R324 (0x144) controls the following;
I get a stable continuous SYSREF output when i press "sync divider."
Can you give me a step by step procedure of what you're doing? I
Best regards,
Vicente
New2Day,
I am assuming that your clock tree looks something like this, but in single loop mode. Can you confirm?
In this case, once all PLLs are locked, all SYSREF clocks and all clocks which have a (greatest common divisor) GCD(SYSREF Frequency, Clock Frequency) = to the SYSREF Frequency, provided SYSREF frequency less than clock frequency, will have deterministic phase with one another.
If you want to share your desired output frequencies, we can confirm if this configuration will work. But assuming they are all you need to do to achieve synchronization is to sync the output dividers.
Let me know if you have any other specific questions.
Best,
Will
