LMK040xx Evaluation Board

Hi Charles,

Sorry for the inconvenience. I've attached the schematics to this post, and will get the users guide updated. Please let me know if anything else. Thanks!

Regards,

Brian Wang

LMK040xx schematics.docx

Hi Bryan,
I am connecting 10Mhz as the external reference input (clkin0*) on the evaluation board and wanted 17.92MHz on the clkout2.
Below are the settings done on the codeloader software.
PLL1: R counter=5, N counter=13, Phase detector frequency=2000. VCO is 26MHz.
PLL2: R counter=25, N counter=896, Phase detector frequency=1040. VCO is 1863.68MHz.
On the code loader application, I am able to see 17.92MHz.
NOTE: I am providing 26MHz from externally to OSCin.

But on the evaluation board, I see 18.63MHz on the clkout2 instead of 17.92MHz.

Basically code loader shows me 17.92MHz, but on the board I measure 18.63MHz.

Can you please let me know if I am missing anything.

Thanks,
Charles

Hi Charles,

That is odd, 17.92 is div-by-104 and 18.63 is div-by-100.

Have you tried other div values? do you get the same offset error by divide value?

Firstly, I assume you are using LMK04033B, and you have removed R16 / R32 and populated R14 / R33 for external source OSCin.

See if you have proper lock on PLL2. Go to the "Bits/Pins" tab of codeloader and under the PLL section --> PLL_MUX change to 'PLL2 DLD Active High'. Remember to load the registers (Keyboard Controls --> Load Device), just to make sure. Then if PLL2 is locking correctly you should see D1 LED light up.

In the mean time you can send my your codeloader settings (in a .mac file), File --> Save.

Thanks

Regards,
Brian Wang

Hi Brian,

When the divider is changed on PLL2, I could see a change in the output clock.
Yes I am using LMK04033B and connected external 26MHz directly to the OSCin on the PCB (Other parts on the OSC line are disconnected).
I do not see the D1 LED on, whe the "PLL2 DLD Active High" is loaded.

I am not able to file files from this forum. Please let me know how to attach the file.
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In another context; This is regarding the actual problem that we are seeing in our system.we are using the the LMK04033B chip on our board.
We are able to program the correct frequency 17.92MHz. But we see a difference in the clk output (more jitter) during reprogramming. Does the way the programming is done can affect the Clk output in terms of jitter. We are getting the correct frequency after reprogramming.
I observed from the uwire interface (Clk,data and latch enable) on the eval board. The clock is around 64KHz, and clock to clock delay (register to next register programming) is around 2.4ms. But where as on our board, we have clock frequency of 100KHz and clock to clock delay (register to next register programming) is 12us. Can this cause any problem for jitter. Also I observe that for changing the output frequency only R2 register changes on the eval board.
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Thanks & Regards,
Charles

Hi Charles,

 

If you are able to get the correct frequency after reprogramming, your programming methodology should be correct. As you've observed the Clk, data, latch enable are the three pins used to program the device. Just make sure you don't violate the timing requirements in the microwire interface timing section (bottom of page 18 and top of page 19 in datasheet). Once you are in lock, the three signals clk/data/LE are held at low state, thus any changes including reprogramming or unintended toggling of these lines can introduce phase degradation and as a result more jitter.

 (for attachments, switch to "use rich formatting", bottom right of the reply box)

Also, jitter depends a lot on your loop configurations. Since you are configuring your system and loop characteristics, here is a simulation tool that can greatly help you: http://www.ti.com/tool/clockdesigntool

With the Clock Design Tool you can select the device you are using, configure the PLL block by block while observing the loop bandwidth, phase noise, and jitter numbers. Here is an example screenshot of your configuration I set in the tool as well as a screenshot of clicking on the simulate button at CLKout0 to see phase noise contribution and jitter. Let me know if any further questions. Thanks!

Hi Brian,

Now we are able to reprogram the synthesizer and it works.
Thanks for your support.
I have another question, if there way to calculate the register values for different frequencies analytically without looking at the look up table from the codeloader.

Regards,
Charles

Hi Charles,

The lookup table is basically an analytical calculation using the OSCin, R, N values, converting to binary and entering into corresponding registers specified by datasheet. Did you want something more excel-based, or displaying formulas? Thanks!

Regards,

Brian Wang

Hi Brian,

Excel based settings would help us out.


Thanks & Regards,
Charles

Hi Brian,

I am finding difficult to get the register values for the below output clock frequency (CLK2):
1) 17.024MHz
2) 8.512 MHz
3) 12.544 MHz
4) 6.272 MHz

Can you please send me the register values for these frequencies.

Also as I requested you earlier, is it possible to get an excel formula. By providing the output clock frequency we can get the corresponding register values.

Thanks & Regards,
Charles
+1 650 743 5200

Hi Brian,

Thank you, this one helps a lot.

Regards,
Charles