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LMK04828: Low power SYSREF generation

Mark Guastaferro
Genius 11115 points
Part Number: LMK04828
Other Parts Discussed in Thread: ADC32RF45, , LMK04610, LMX2582, LMK01010

I'm investigating a lower power clocking solution for  an ADC32RF45 based receiver design.  I posted questions on the High Speed Forum related to this:

The concern is that the ADC32RF45 EVM uses the LMK04828 to generate SYSREF for the ADC as well as the EVM FPGA, as well as the FPGA clock.  The data sheet for the LMK04828 indicates power dissipation of 1.9W.  

Is this power dissipation accurate if the device only outputs SYSREF signals, or is there another, simpler clocking device that could be used instead of the LMK04828?

  • 0
    TI__Genius 11115 points

    Small correction from my original post. I realized that the LMK04828 data sheet includes a section on estimating the power consumption of a specific configuration and also found a spreadsheet calculator on another post. Using the spreadsheet and inserting what I think the typical configuration would be for a set-up similar to the ADC32RF45 EVM, I get the LMK04828 power dissipation to be about 1.2W.

    However, since the ADC32RF45 will be clocked from the LMX2582, my question still holds as to maybe there's a lower power method to generate the needed SYSREF and probable FPGA clocks. For example, the second output of the LMX2582 could be used to generate the FPGA clock (ADC sampling rate is 3 GSPS and ADC decimation is 24). Or maybe the LMK04610 might be a lower power option since 3 GHz clock is generated in LMX device. 

  • 0 in reply to Mark Guastaferro
    TI__Expert 8865 points
    Hi Mark

    You pretty much have the optimized setup in terms of power. LMK0461x devices are low power devices with 10 or 16 outputs with a flexibility to have each Clock output to act as a SYSREF or a Device clock and also the output power supplies can be 1.8V with good PSRR to run directly with DCDC converter, but the 3GHz output is not supported there.

    Best regards
    Puneet
  • 0 in reply to Puneet Sareen
    TI__Genius 11115 points

    Hi Puneet,
    Thanks for your comments.

    I have a power budget for the SYREF generation of 500 mW.  Do you think the LMK0461x type device can achieve this? Only need 3 LVDS outputs FPGA clock, SYSREF for FPGA, SYSREF for ADC.  LMX582 would provide 3 GHz clock for ADC. . 


    Another idea I have is to use a clock buffer like the LMK01010 to generate the SYSREF signals from the FPGA clock. My thinking is to use the LMX2582 to generate the ADC clock (near 3 GHz) and the FPGA clock (ADC clock/24). Use the FPGA clock to feed the LMK01010 to generate SYSREF signals that would be around FPGA clock/ 32. The LMK0101 would output three LVDS signals: FPGA clock, and two SYSREF signals. This should be much lower power than the LMK04610, under 200 mW if my estimate is correct. However, I'm not sure if this would support the required set-up/hold times for the ADC/SYSREF timing relationship, plus how to  handle cleanly turning off SYSREF after initialization.

    Is this a legitimate approach?

  • 0 in reply to Mark Guastaferro
    TI__Expert 8865 points
    Hi Mark

    The ADC clock in your case is 3GHz. You will have setup hold time requirements for ADC. if you use LMK01010 to generate SYSREF, then you will have to conside the TPD varriation from this device and see if you can still hit setup/hold times.

    Best regards
    Puneet