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Hello Team
My customer is using LMK04011 as jitter cleaner. Input clock is 74.25. VCXO 74.25Mhz, output 74.25Mhz. Following are register setup. but no clock out put. If changed R14 to 0x0C9E001E, the clock have output. But I am confused about it. This change is only change PLL_mux,. so cloud you help review it?
R7 (INIT) 0x00000017
R0 0x01030500
R1 0x010B0501
R2 0x01080102
R3 0x01080103
R4 0x01000104
R7 0x00000007
R10 0x2150000A
R11 0x006501EB
R12 0xE002002C
R13 0x0A04000D
R14 0x0C97001E
R15 0x148000AF
Hello,
Your programming looks ok.
As for programming...
R14 = 0x0C97001E --> Resulting in no clock output, then
R14 = 0x0C9E001E --> Resulting in clock output.
The 1st setting shows PLL_MUX = 23 (0x17) = PLL1/2 DLD Active High
The 2nd setting shows PLL_MUX = 30 (0x1E) = Reserved
This should not cause a difference for the purpose of an output clock.
* Can you confirm the state of the SYNC* pin? Since you are using a divided output, if this pin is low, then no clock output would exist.
* Can you confirm the state of the GOE pin? If low, then no clock output would exist.
Note, the programming sets OSCin_FREQ = 100; this is ok, although you could set it to 74, closer to OSCin frequency you are currently using (74.25 MHz). This would not cause the device to not provide a clock output.
If not solved,
* When there is no clock output, what is the voltage on each clock output pin of a clock pair (CLKout0 & CLKout0*) in question?
* What does the output termination look like from one of the LVPECL clock outputs?
* What is the voltage at CPout2? Does PLL1/2 DLD report high (locked?).
73,
Timothy