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LMK5B12204: Need help configuring one output to generate 38.4 MHz clock

Stefan Vos
Prodigy 70 points
Part Number: LMK5B12204
Other Parts Discussed in Thread: LMK05318B, USB2ANY

Hello,
We have a design using the LMK5B12204 that uses Input XO of 19.2 MHz in the CMOS (SE no term) configuration. We would like to generate an output CMOS +/- clock of 38.4 MHz that is synchronized on a 1 pps signal. Could you please provide us with the register settings for this configuration ? We have tried using the TICS Pro wizard in generating the register values but with no success so far. When programming the register values we follow the steps:
1. Pull PDN pin high.
2. Program values of the registers in low to high order
3. Write 1b to the RESET_SW bit in register 0x0C
4. Write 0b to the RESET_SW bit in register 0x0C

When programming the registers we mask the appropriate registers R12, R157,R164 and R353 to R435

We are using SPI at 5 MHz to communicate with the chip. After we write the registers and we read them back the values are not set correctly. Also we can't see any output on the oscilloscope.


Any help will be greatly appreciated.
Thank You

  • 0
    TI__Mastermind 18070 points

    Hi Stefan,

    Did you get a chance to read the last page of the wizard and read back status register values? That'll give you a clue of what's not working. I'd manually enable the BAW lock detect first just for evaluation purposes and see if the BAW VCO can lock. 

    If there's some setting that you don't understand, click "show instructions" and read the notes there.

    Regards,

    Hao

  • 0 in reply to Hao Z
    Prodigy 70 points

    Hello Hao,

    Thanks for the suggestion.

    I've enabled BAW lock detect with the default settings from the wizard.

    Regarding the last page of the wizard, I've read the Registers ( that I could find, for example PLL2_VM_INSIDE and PLL1_VM_INSIDE are nowhere to be found in the register programming manual).

    LOS_FDET_XO bit is 0, while LOL_PLL2 and LOS_XO bits are 1.  Value of 0x0D register is 0x09.

    LOPL_DPLL, LOFL_DPLL and HLDOVR bits are 1 and  LOR_MISSCLK, LOR_FREQ and LOR_AMP bits are 0.  The value of 0x0E register is 0x0D. I don't know if these values are relevant since DPLL is disabled (as per recommandation of wizard when enabling BAW lock detect).

    BAW_LOCK bit si 0. Value of 0x50 register is 0x00.

    I could not find PLL1_VM_INSIDE and PLL2_VM_INSIDE bits in any registers.

    Could you please guide me in what should I do next ?

    Thank you for your help.

    Regards,

    Stefan 

  • 0 in reply to Stefan Vos
    TI__Mastermind 18070 points

    Hi Stefan,

    Actually, you don't need a register manual and you can find all the information in Ticspro. Go to the status page and find all the status registers. Click "read status" button to read back status registers. By the way, the register information can be found in the lower left pane when you hover the mouse over a field register.

    If DPLL is disabled then it'll be a lot easier. The final goal is to get the BAW locked. First make sure that LOS_FDET_XO is cleared which means that XO is valid. If there's still a problem, can you upload your configuration so that I can have a quick look?

    Regards,
    Hao

  • 0 in reply to Hao Z
    Prodigy 70 points

    Hello Hao,

    Thank you for your response.

    I cannot read the status from the TICS Pro software as I do not have any connection with it. (Is there any evaluation board of the LMK5B12204 that can be connected to this software ? ).

    We are only using the TICS Pro software to configure the outputs that we want and then export the Hex file with the register values.

    After that we have a microcontroller connected through SPI to the LMK5b12204 and that's the way we program the values of the registers.

    I have attached the register values that we export from the TiCS Pro software. Can you tell us if there's something wrong with these register values ?

    Thank you.

    Stefan

    HexRegisterValuesBAWLock.txt 
    R0	0x000010
R1	0x00010B
R2	0x000235
R3	0x000332
R4	0x000404
R5	0x00050E
R6	0x000617
R7	0x00078E
R8	0x000802
R10	0x000AC8
R11	0x000B00
R12	0x000C1B
R13	0x000D08
R14	0x000E00
R15	0x000F00
R16	0x001000
R17	0x00111D
R18	0x0012FF
R19	0x001308
R20	0x001420
R21	0x001501
R22	0x001600
R23	0x001755
R24	0x001855
R25	0x001900
R26	0x001A00
R27	0x001B00
R28	0x001C01
R29	0x001D13
R30	0x001E40
R32	0x002044
R35	0x002300
R36	0x002403
R37	0x002500
R38	0x002600
R39	0x002703
R40	0x002803
R41	0x002900
R42	0x002A11
R43	0x002BC2
R44	0x002C00
R45	0x002D03
R46	0x002E11
R47	0x002F87
R48	0x003050
R49	0x00314A
R50	0x003237
R51	0x003380
R52	0x003400
R53	0x00352F
R54	0x003600
R55	0x003700
R56	0x00380F
R57	0x003900
R58	0x003A0F
R59	0x003BBE
R60	0x003C2F
R61	0x003D00
R62	0x003E63
R63	0x003F00
R64	0x004000
R65	0x004100
R66	0x004200
R67	0x004318
R68	0x004408
R69	0x004500
R70	0x004600
R71	0x004700
R72	0x004833
R73	0x004900
R74	0x004A01
R75	0x004B00
R76	0x004C00
R77	0x004D0F
R78	0x004E00
R79	0x004F11
R80	0x005080
R81	0x00510A
R82	0x005200
R83	0x00530B
R84	0x005440
R85	0x005500
R86	0x005600
R87	0x00571E
R88	0x005884
R89	0x005980
R90	0x005A00
R91	0x005B14
R92	0x005C00
R93	0x005D0B
R94	0x005E40
R95	0x005F00
R96	0x006000
R97	0x00611E
R98	0x006284
R99	0x006380
R100	0x006428
R101	0x006501
R102	0x006622
R103	0x00670F
R104	0x00681F
R105	0x006905
R106	0x006A00
R107	0x006B64
R108	0x006C00
R109	0x006D41
R110	0x006E1A
R111	0x006FAA
R112	0x0070AA
R113	0x0071AA
R114	0x0072AB
R115	0x007303
R116	0x007400
R117	0x007500
R118	0x007600
R119	0x007700
R120	0x007800
R121	0x007900
R122	0x007A00
R123	0x007B28
R124	0x007C00
R125	0x007D11
R126	0x007E79
R127	0x007F7A
R128	0x008000
R129	0x008101
R130	0x008200
R131	0x008301
R132	0x008401
R133	0x008577
R134	0x008600
R135	0x008790
R136	0x008800
R137	0x008900
R138	0x008A00
R139	0x008B03
R140	0x008C02
R141	0x008D00
R142	0x008E01
R143	0x008F01
R144	0x009077
R145	0x009101
R146	0x009289
R147	0x009320
R149	0x00950D
R150	0x009600
R151	0x009701
R152	0x00980D
R153	0x009929
R154	0x009A24
R155	0x009B32
R156	0x009C01
R157	0x009D00
R158	0x009E00
R159	0x009F00
R160	0x00A0FC
R161	0x00A132
R162	0x00A200
R164	0x00A400
R165	0x00A500
R167	0x00A701
R178	0x00B200
R180	0x00B400
R181	0x00B500
R182	0x00B600
R183	0x00B700
R184	0x00B800
R185	0x00B904
R186	0x00BA08
R187	0x00BB00
R188	0x00BC00
R189	0x00BD00
R190	0x00BE2C
R191	0x00BF00
R192	0x00C050
R193	0x00C100
R194	0x00C200
R195	0x00C300
R196	0x00C400
R197	0x00C51D
R198	0x00C600
R199	0x00C700
R200	0x00C81D
R201	0x00C900
R202	0x00CA00
R203	0x00CB00
R204	0x00CC15
R205	0x00CD00
R206	0x00CE00
R207	0x00CF15
R208	0x00D000
R209	0x00D114
R210	0x00D200
R211	0x00D316
R212	0x00D400
R213	0x00D514
R214	0x00D600
R215	0x00D716
R216	0x00D80F
R217	0x00D900
R218	0x00DA00
R219	0x00DB19
R220	0x00DC6E
R221	0x00DD00
R222	0x00DE03
R223	0x00DF0D
R224	0x00E047
R225	0x00E100
R226	0x00E200
R227	0x00E319
R228	0x00E46E
R229	0x00E500
R230	0x00E603
R231	0x00E70D
R232	0x00E847
R233	0x00E90A
R234	0x00EA0A
R235	0x00EB00
R236	0x00ECC3
R237	0x00ED50
R238	0x00EE00
R239	0x00EF00
R240	0x00F0C3
R241	0x00F150
R242	0x00F200
R243	0x00F300
R244	0x00F400
R249	0x00F912
R250	0x00FA00
R251	0x00FB13
R252	0x00FC24
R253	0x00FD00
R254	0x00FE00
R255	0x00FF00
R256	0x010000
R257	0x010101
R258	0x010200
R259	0x010301
R260	0x010402
R261	0x010580
R262	0x010600
R263	0x010700
R264	0x010800
R265	0x010900
R266	0x010AC8
R267	0x010BA0
R268	0x010C0C
R269	0x010D0A
R270	0x010E02
R271	0x010F14
R272	0x011000
R273	0x011100
R274	0x011200
R275	0x01130E
R276	0x01140C
R277	0x01150E
R278	0x011609
R279	0x011708
R280	0x011809
R281	0x011907
R282	0x011A0D
R283	0x011B07
R284	0x011C1E
R285	0x011D1E
R286	0x011E02
R287	0x011F30
R288	0x012000
R289	0x0121EE
R290	0x012202
R291	0x0123CA
R292	0x012409
R293	0x012501
R294	0x012600
R295	0x01272C
R296	0x012808
R297	0x01290C
R298	0x012A08
R299	0x012B01
R300	0x012C00
R301	0x012D1C
R302	0x012E20
R303	0x012F01
R304	0x013001
R305	0x013100
R306	0x013200
R307	0x013300
R308	0x013410
R309	0x0135AA
R310	0x0136AA
R311	0x0137AA
R312	0x0138AA
R313	0x0139AA
R314	0x013AFF
R315	0x013BFF
R316	0x013CFF
R317	0x013DFF
R318	0x013EFF
R319	0x013F03
R320	0x014000
R321	0x01410A
R322	0x014200
R323	0x014324
R324	0x01449F
R325	0x014500
R326	0x014600
R327	0x014798
R328	0x014896
R329	0x014980
R330	0x014A00
R331	0x014B64
R332	0x014C00
R333	0x014D00
R334	0x014E27
R335	0x014F10
R336	0x015000
R337	0x015198
R338	0x015296
R339	0x015300
R340	0x015400
R341	0x015500
R342	0x015600
R343	0x015700
R344	0x015800
R345	0x015900
R346	0x015A02
R347	0x015B00
R348	0x015C00
R349	0x015D00
R350	0x015E00
R351	0x015F00
R352	0x016000
R357	0x016528
R367	0x016F00
R411	0x019B0C

    HexRegisterValuesBAWLock.txt 
    R0	0x000010
R1	0x00010B
R2	0x000235
R3	0x000332
R4	0x000404
R5	0x00050E
R6	0x000617
R7	0x00078E
R8	0x000802
R10	0x000AC8
R11	0x000B00
R12	0x000C1B
R13	0x000D08
R14	0x000E00
R15	0x000F00
R16	0x001000
R17	0x00111D
R18	0x0012FF
R19	0x001308
R20	0x001420
R21	0x001501
R22	0x001600
R23	0x001755
R24	0x001855
R25	0x001900
R26	0x001A00
R27	0x001B00
R28	0x001C01
R29	0x001D13
R30	0x001E40
R32	0x002044
R35	0x002300
R36	0x002403
R37	0x002500
R38	0x002600
R39	0x002703
R40	0x002803
R41	0x002900
R42	0x002A11
R43	0x002BC2
R44	0x002C00
R45	0x002D03
R46	0x002E11
R47	0x002F87
R48	0x003050
R49	0x00314A
R50	0x003237
R51	0x003380
R52	0x003400
R53	0x00352F
R54	0x003600
R55	0x003700
R56	0x00380F
R57	0x003900
R58	0x003A0F
R59	0x003BBE
R60	0x003C2F
R61	0x003D00
R62	0x003E63
R63	0x003F00
R64	0x004000
R65	0x004100
R66	0x004200
R67	0x004318
R68	0x004408
R69	0x004500
R70	0x004600
R71	0x004700
R72	0x004833
R73	0x004900
R74	0x004A01
R75	0x004B00
R76	0x004C00
R77	0x004D0F
R78	0x004E00
R79	0x004F11
R80	0x005080
R81	0x00510A
R82	0x005200
R83	0x00530B
R84	0x005440
R85	0x005500
R86	0x005600
R87	0x00571E
R88	0x005884
R89	0x005980
R90	0x005A00
R91	0x005B14
R92	0x005C00
R93	0x005D0B
R94	0x005E40
R95	0x005F00
R96	0x006000
R97	0x00611E
R98	0x006284
R99	0x006380
R100	0x006428
R101	0x006501
R102	0x006622
R103	0x00670F
R104	0x00681F
R105	0x006905
R106	0x006A00
R107	0x006B64
R108	0x006C00
R109	0x006D41
R110	0x006E1A
R111	0x006FAA
R112	0x0070AA
R113	0x0071AA
R114	0x0072AB
R115	0x007303
R116	0x007400
R117	0x007500
R118	0x007600
R119	0x007700
R120	0x007800
R121	0x007900
R122	0x007A00
R123	0x007B28
R124	0x007C00
R125	0x007D11
R126	0x007E79
R127	0x007F7A
R128	0x008000
R129	0x008101
R130	0x008200
R131	0x008301
R132	0x008401
R133	0x008577
R134	0x008600
R135	0x008790
R136	0x008800
R137	0x008900
R138	0x008A00
R139	0x008B03
R140	0x008C02
R141	0x008D00
R142	0x008E01
R143	0x008F01
R144	0x009077
R145	0x009101
R146	0x009289
R147	0x009320
R149	0x00950D
R150	0x009600
R151	0x009701
R152	0x00980D
R153	0x009929
R154	0x009A24
R155	0x009B32
R156	0x009C01
R157	0x009D00
R158	0x009E00
R159	0x009F00
R160	0x00A0FC
R161	0x00A132
R162	0x00A200
R164	0x00A400
R165	0x00A500
R167	0x00A701
R178	0x00B200
R180	0x00B400
R181	0x00B500
R182	0x00B600
R183	0x00B700
R184	0x00B800
R185	0x00B904
R186	0x00BA08
R187	0x00BB00
R188	0x00BC00
R189	0x00BD00
R190	0x00BE2C
R191	0x00BF00
R192	0x00C050
R193	0x00C100
R194	0x00C200
R195	0x00C300
R196	0x00C400
R197	0x00C51D
R198	0x00C600
R199	0x00C700
R200	0x00C81D
R201	0x00C900
R202	0x00CA00
R203	0x00CB00
R204	0x00CC15
R205	0x00CD00
R206	0x00CE00
R207	0x00CF15
R208	0x00D000
R209	0x00D114
R210	0x00D200
R211	0x00D316
R212	0x00D400
R213	0x00D514
R214	0x00D600
R215	0x00D716
R216	0x00D80F
R217	0x00D900
R218	0x00DA00
R219	0x00DB19
R220	0x00DC6E
R221	0x00DD00
R222	0x00DE03
R223	0x00DF0D
R224	0x00E047
R225	0x00E100
R226	0x00E200
R227	0x00E319
R228	0x00E46E
R229	0x00E500
R230	0x00E603
R231	0x00E70D
R232	0x00E847
R233	0x00E90A
R234	0x00EA0A
R235	0x00EB00
R236	0x00ECC3
R237	0x00ED50
R238	0x00EE00
R239	0x00EF00
R240	0x00F0C3
R241	0x00F150
R242	0x00F200
R243	0x00F300
R244	0x00F400
R249	0x00F912
R250	0x00FA00
R251	0x00FB13
R252	0x00FC24
R253	0x00FD00
R254	0x00FE00
R255	0x00FF00
R256	0x010000
R257	0x010101
R258	0x010200
R259	0x010301
R260	0x010402
R261	0x010580
R262	0x010600
R263	0x010700
R264	0x010800
R265	0x010900
R266	0x010AC8
R267	0x010BA0
R268	0x010C0C
R269	0x010D0A
R270	0x010E02
R271	0x010F14
R272	0x011000
R273	0x011100
R274	0x011200
R275	0x01130E
R276	0x01140C
R277	0x01150E
R278	0x011609
R279	0x011708
R280	0x011809
R281	0x011907
R282	0x011A0D
R283	0x011B07
R284	0x011C1E
R285	0x011D1E
R286	0x011E02
R287	0x011F30
R288	0x012000
R289	0x0121EE
R290	0x012202
R291	0x0123CA
R292	0x012409
R293	0x012501
R294	0x012600
R295	0x01272C
R296	0x012808
R297	0x01290C
R298	0x012A08
R299	0x012B01
R300	0x012C00
R301	0x012D1C
R302	0x012E20
R303	0x012F01
R304	0x013001
R305	0x013100
R306	0x013200
R307	0x013300
R308	0x013410
R309	0x0135AA
R310	0x0136AA
R311	0x0137AA
R312	0x0138AA
R313	0x0139AA
R314	0x013AFF
R315	0x013BFF
R316	0x013CFF
R317	0x013DFF
R318	0x013EFF
R319	0x013F03
R320	0x014000
R321	0x01410A
R322	0x014200
R323	0x014324
R324	0x01449F
R325	0x014500
R326	0x014600
R327	0x014798
R328	0x014896
R329	0x014980
R330	0x014A00
R331	0x014B64
R332	0x014C00
R333	0x014D00
R334	0x014E27
R335	0x014F10
R336	0x015000
R337	0x015198
R338	0x015296
R339	0x015300
R340	0x015400
R341	0x015500
R342	0x015600
R343	0x015700
R344	0x015800
R345	0x015900
R346	0x015A02
R347	0x015B00
R348	0x015C00
R349	0x015D00
R350	0x015E00
R351	0x015F00
R352	0x016000
R357	0x016528
R367	0x016F00
R411	0x019B0C

  • 0 in reply to Stefan Vos
    TI__Mastermind 18070 points

    Hi Stefan,

    I see. You should be able to use a USB2ANY box and bluewire the SPI/I2C lines in order to use Ticspro for evaluation. There's no dedicated EVM for LMK5B12204 and it can be evaluated on a LMK05318B EVM.

    Can you send me the .tcs file instead (File -> Save)? Registers don't contain all the information, such as selections you made in the wizard. You can zip the .tcs file if unable to upload it.

    Regards,
    Hao

  • 0 in reply to Hao Z
    Prodigy 70 points

    Hi Hao,

    Attached is the .tcs file with the configuration we use. For now PRI and SEC references are disabled and all we have configured is an output of 38.4 MHz on OUT2.

    Thank you, 

    StefanBawLock.tcs

  • 0 in reply to Stefan Vos
    TI__Mastermind 18070 points

    Hi Stefan,

    Now I see. You're not using APLL1 and that's why the BAW is never locked. Still you should see that LOL_PLL2 is cleared and PLL2_VM_INSIDE = 1 if the PLL2 is locked. 

    Can you try enabling the APLL1 and see if you can get the BAW to lock? To do so, you can use cascaded mode (which will provide better performance anyways):

    If you still can't get any PLL to lock, check the capacitor value on pin 29 and 34.

    Regards,
    Hao

  • 0 in reply to Hao Z
    Prodigy 70 points

    Hello Hao,

    Thank you for your response. After using the USB2ANY interface and changing the pin 29 capacitor to 0.47 we managed to get the desired frequency and BAW lock.

    Next step for us would be to sync the clock output on a 1 Hz signal incoming on PRIREF input. The signal is a 1 Hz 50% duty cycle signal.

    Can you please give me some starting point on what the settings should be ?

    The DPLL is enabled and  the APLL2 uses  VCO1.

    We set the priref frequency to 1 Hz, DC, hysteresisi enabled.

    We set validation timer to 3.2768s and enabled the 1PPS phase detector with Cntr:64, 1.64 us Jitter.

    We set the DPLL LBW to 0.01

    BAW Lock disabled and DPLL Frequency Lock Detect Phase Detect and Tuning word History set to default.DPLL.tcs

    Is there any status registers that we can check to see if the settings are correct and the DPLL works ?

    We can see on the oscilloscope that the output clock is not synced with the 1 Hz signal.

    Thank you for your help,

    Stefan

  • 0 in reply to Stefan Vos
    TI__Mastermind 18070 points

    Hi Stefan,

    Yes. The first register to check is PRIREF_VALSTAT (or SECREF_VALSTAT, depending on which reference you use) which stands for "primary reference valid state". When this register becomes 1 then it means your 1pps signal has been validated and accepted. Only after that will the DPLL start to try to lock.

    You will need a TCXO/OCXO for high frequency precision and low wander otherwise the DPLL won't be able to follow and the reference validation won't pass. The frequency error between the TCXO and 1pps input shouldn't be more than 1ppm.

    If you're able to get the PRIREF to be valid, check DPLL_LOFL and DPLL_LOFL. If both are 0 then you're good to go. The PRIREF_VALSTAT takes about 9 seconds to become valid. DPLL_LOPL usually takes 150-200s. LOFL is faster than LOPL and I can't remember the exact numbers.

    Regards,
    Hao

  • 0 in reply to Hao Z
    Prodigy 70 points

    Hello Hao,

    Thank  you for your response.

    We were unable to validate the PRIREF_VALSTAT with 1 Hz input, because we are using 19.2 MHz XO that has +/- 10 ppm. 

    So we decided to switch the PRIREF input to 1 KHz, and now the PRIREF_VALSTAT bit is set, but the LOPL and LOFL of DPLL bits are never cleared ( even after 20 minutes)

    We changed the validation timer to 102.4 ms and disabled all the detectors.

    Should we have any detector enabled for the 1 KHz input ? 

    Can you tell me what I could do next in order to get the DPLL to lock ?

    I have also attached our schematic in case it will help.

    Thank you for your support,

    Stefan.LMK5B12204-TI.pdf

  • 0 in reply to Stefan Vos
    TI__Mastermind 18070 points

    Hi Stefan,

    Make sure that you click this button every time you change something. Otherwise the DPLL settings won't be updated.

    In order to run this script, you need to download the matlab runtime engine, which is for free and the link is in the first wizard page. 

    Regards,
    Hao

  • 0 in reply to Hao Z
    Prodigy 70 points

    Hi Hao,

    We click the Run Script every time we do any changes.

    But we have set the DPLL LBW to 100 Hz as it was suggested in the instructions.

    Should we set it to 200 Hz ?

    Thank you,

    Stefan

  • 0 in reply to Stefan Vos
    TI__Mastermind 18070 points

    Hi Stefan,

    No 100Hz is good. Can you always check if PRIREF_VALSTAT is read back as 1? If the reference is valid and the DPLL script is run then DPLL should be able to lock with no problem. If the reference is indeed valid and the DPLL is not locked, can you read back all the registers and send me the .tcs file for review?

    Regards,
    Hao