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Whilst operating in holdover 1PPS mode, what is the behaviour when not operating in ZDM or Hitless modes when a 1PPS input becomes valid? If not using fastlock will the transition back to the input phase be more gradual?
For context, our application is to be able to automatically select one of two 1PPS inputs, sync a clock to the input and produce a 1PPS output. When neither of these inputs is valid we want to enter the holdover mode. When automatically exiting the holdover mode, it is important that there is a reasonably smooth transition to becoming realigned with a valid input, with the shift back to realignment being spread over a few PPS pulses.
Thanks.
Hi Matt,
Without hitless switching there won't be any guarantee in the output phase transition for LMK05318B. However, the LMK5C33216 (the prototype version of which will be released next week) has a feature for phase slew control, meaning that you can control the speed of phase change so that the phase transition is smooth.
Regards,
Hao
Hi Hao,
Thanks for your reply, do you have any further information on the LMK5C33216? Do you know when this is going into production?
Thanks