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LMK05318: Generating and Jitter cleaning 245.76Mhz using APLL1

Part Number: LMK05318
Other Parts Discussed in Thread: , LMK05028, LMK5C33216

Hi Team,

Is it possible to generate 245.76Mhz using APLL1? (We understand that VCO1 frequency is fixed to 2.5Ghz)

We have a requirement to generate one 245.76Mhz output ( Initially 245.76Mhz need to be generated using XO input and once the reference through primary reference(368.76Mhz)is available it has to switch automatically and enter into jitter cleaning mode)  and three 156.25Mhz output in synchronizer mode( Only using XO input) Plz refer attached TICS pro screenshot.

TICSPro tool indicates that 245.76Mhz cannot be generated using PLL1.  But I cannot use PLL2 to generate 245.76Mhz because I need to generate 156.25Mhz using Non-Cascaded APLL2 mode.

Do you have any solution or suggestion for this?

Regards,

Gireesh

  • Hello, it is not possible to get 245.76 MHz from VCO1 since only integer dividers exist.

    I suggest 245.76 MHz from VCO2 and the other frequencies from VCO1.  You can cascade VCO1 --> VCO2, however there will be a small ppm frequency error depending on your settings.  ~1.62  ppt error is possible using cascading dividers of 5 and 19.  However then PLL2 performance will not be as good due to the lower phase detector frequency.  A frequency error of less than 0.3 ppb is possible using the default cascading dividers of 3 and 6.

    Example:

    --

    If exact frequency is what you need, the LMK05318B has a PLL2 with a programmable fractional denominator, this enables you to achieve exact frequency.

    In both cases using cascade mode will have the frequency generated based on XO, then convert to the locked frequency.

    73,
    Timothy

  • Hi Timothy,

    I need only 245.76Mhz output to be used in Jitter cleaner mode. 245.76Mhz clock needs to switch over to PRIREF clock input when the input becomes valid. Whereas, 156.76Mhz clock need to be always generated using the XO input( I do not want 156.76Mhz to refer to PRIREF clock input).  

    Having said that, If I use VCO2 for 245.76 MHz with a cascade of VCO1 --> VCO2. PLL configuration will be in "DPLL Mode With Cascaded APLL2". 

    Can you please suggest me an alternate solution to generate three 156.76Mhz independently using XO input(only as clock synthesizer) and one 245.76Mhz (jitter cleaner) to operate in a DPLL mode that switches over to PRIREF when valid?

    Regards,

    Gireesh

  • Hello Gireesh,

    Please note, when we talk about jitter cleaning -- anything with a VCO and a loop filter performs jitter cleaning.  Also a DPLL and an XO/TCXO/OCXO perform jitter cleaning above the LBW of the DPLL.  Above the loop bandwidth the noise of the reference is replaced with the noise of the VCO (or XO) to the limit of the loop bandwidth.  I.e. a brick-wall filter would be ideal.  See this powerpoint for further discussion.  Note, this document does not discuss DPLLs, but the concept is the same which basically allow an XO to perform jitter cleaning using XO phase noise performance above the DPLL loop bandwidth.  In fact the DPLL is very much like the cascaded jitter cleaning example except a DPLL + XO replace PLL1 + VCXO.

    The LMK05318 has a DPLL only on PLL1 which allows the XO to perform jitter cleaning on the reference in addition to a low noise PLL/VCO combination for frequency multiplication.  The BAW VCO performance is good enough that it can also be considered to have good jitter cleaning properties.  I'm not sure your output performance requirements in terms of jitter or phase noise.  However the method I suggested above would basically use PLL1 for jitter cleaning + 156.25 MHz generation then PLL2 for frequency translation -- which the LMK05318B will do a better job providing 0-ppm error frequency translation.
       > However, sounds like you need the phase of 156.25 MHz and 245.76 MHz to not be locked long term?  Is it ok for them to be locked at start-up before the reference becomes active that the 245.76 MHz follow?

    ---

    I think in this case we may need to consider another device?  I have two suggestions.

    First, the LMK05028 provides two separate DPLLs/APLLs/VCOs.  You could then easily configure PLL1 to output the 245.76 MHz and lock to the reference when needed, and have PLL2 provide the 156.25 MHz locked only to the XO for independent operation.  Note, up until the moment that DPLL1 locks to the reference, PLL1 and PLL2 would have phase lock.  This device does not have the BAW.

    Second, the LMK5C33216 provides three separate DPLLs/APLLs/VCOs.  VCO3 is actually a BAW at 2457.6 MHz.  So this would give the best performance for a 245.76 MHz jitter cleaned clock.  One of the other PLLs could generate the 156.25 MHz (I suggest VCO2 for best performance).

    How do these options sound?  If you provided me with jitter or phase noise specifications for the outputs and some more details on the phase requirements between 156.25 MHz and 245.76 MHz I could advise better.  For example, it's not apparent why the 156.25 MHz and 245.76 MHz cannot be at 0 ppm to one other.
       - Perhaps it is just that the 156.25 MHz should not change phase at all given concern as it could be a CPU clock?  Please note that a narrow loop bandwidth DPLL would constrain the rate of phase change that I should would be acceptable for a CPU.  In fact, an XO will provide so much wander (compared to a TCXO) that a DPLL cannot lock with very low loop bandwidths using an XO!

    73,
    Timothy

  • Hi Timothy,

    Thanks for the detailed explanation. 

    Regards,

    Gireesh