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LMH0397: SDI-Layout Review

Shifali N
Expert 2145 points
Part Number: LMH0397

Hi,

I am using LMH0397RTVT IC in my design for 3G SDI Output and Input interface. I will be using BNC connector BNC7T-J-P-GN-RA-BH2D from Samtec. I have designed layout for this IC in two different approaches.

Approach 1: 75ohm impedance signal have ground reference in N-2 layer. As per stackup keep out is provided in N-1 layer

Approach 2: 75ohm impedance signal have ground reference in N-2 layer, but 36mils of trace length of signal doesn't have ground reference.

Layout design for both SDI output and input interface will be similar. I have attached layout design of SDI Input interface. I have attached schematics and stack up for reference.

Can you please review layout files provided for both the approaches and let us know which is the correct layout design that we should consider and proceed. Also let us know  your suggestions to improve the layout design.

Thanks in Advance!iW-EMFCY-BF-01-R1_0-REL1_0_27-08-2021-1900-SDI-APPROACH1.PcbDocAPPROACH2.pdfUPDATED-APPROACH 1.pdfiW-EMFCY-BF-01-R1_0-REL1_0_27-08-2021-1900-SDI-APPROACH2.PcbDocIWAVE-8LAY-08JUNE2021-21364.pdf

  • 0
    TI__Guru* 93670 points

    Hi Shifalli,

    Please note some comments below:

    1). Schematic looks good.

    2). Typically under high speed pins and component pads we have void. Meaning there is no GND or VCC under these. Looking at your pcb layout it seems there is some GND plane. If there is not a void then this causes impedance drop. It may not be a big thing at 3G but we typically use this guideline on our designs. I believe pcb layout guidelines in the data sheet mentions this as well.

    3). High speed traces we typical arc this - this means we don't have sharp turns. On your 100-ohm signal you seem to have this sharp turn. Again this may not be a major issue but we typically avoid these sharp turns.

    4). Please note figure 36 of the data sheet. It was not clear to me that you are using four squares for solder paste. I see the vias but not the solder paste.

    Regards ,, Nasser

      - 

  • 0 in reply to Nasser Mohammadi
    Expert 2145 points

    Hi Nasser,

    The above shared comments are general layout guidelines. Thanks for sharing those guideline. I want your feedback on the layout design that I have shared.

    In one of the approach I shared, the 75ohm impedance signal is routed with trace length 254mils from Driver IC to SDI connector in Layer 8( bottom layer).
    As per the stack-up the Ground reference is provided in Layer6. Void is present in layer1 to layer5 and layer7. Out of 254mils trace of SDI 75ohm signal,36mils of trace wont be having any ground reference in layer6.
    36mils of trace will be having a void. Is that acceptable. Wont there be any impedance mismatch.

    Reattaching the image for reference. In the attached image I have highlighted portion of signal that wont behaving Ground reference and will be having a complete void. Please provide your input on the same.

  • 0 in reply to Shifali N
    TI__Guru* 93670 points

    Hi Shifalli,

    In our designs, we always have reference plane and prevent any impedance discontinuity - even with 36mils trace length. In this case, 3G SDI, this trace goes to the BNC connector and this higher impedance may compensate for the BNC pin anti-pad. Suggestion is to contact your BNC connector vendor to get their comments for optimum BNC connector anti-pad. 

    Regards , Nasser