LMH1219: cannot output when 12G

Hi Jianyang,

I have some thoughts that may help with debugging:

1. Is the customer performing the LMH1218 initialization sequence specified in the LMH1218 Programming Guide, Section 4.2.2.3? Please confirm.

2. At 12G, can you request that they check the lock status and readback the locked data rate? This can be done by following the sequence in Section 4.2.11 of the Programming Guide. If the LMH1218 is unable to lock to the incoming 12G signal, then this may be an issue with incorrect CTLE settings at the LMH1218 input.

3. Please check the CTLE setting by implementing the sequence in Section 4.2.9. By default, the CTLE value in LMH1218 Reg 0x03 = 0x80, which helps to equalize approximately 10-15 in. of PCB FR4 trace. Depending on the amount of trace between the LMH1219 and LMH1218, you may need to apply more or less gain. Please refer to the table below for CTLE boost setting recommendations:

Thanks,

Michael

hi Michael,

thanks a lot!

1.Yes, LMH1218 is configured according to Section 4.2.2.3.

2.At 12G, LMH1218 cannot lock, readback the locked data rate has been Changing.(reg 0x02:  0x9B->0x92->0x89->0x80->A4->0x9B)

3.  the pcb trace length about 14in. , the CTLE value in Reg 0x03 = 0x80, /0x50 /etc. The issue still exists.

test result: 

1. LMH1219 Output CH1 can output image at 3G/6G/12G，output CH0 connect to LMH1218 Input CH0. LMH1218 output can output image at 3G/6G, but cannot ouput at 12G.

2. LMH1218 can locked at 3G/6G, cannot locked at 12G.

Can you support the LMH1218 and LMH1219 12G configuration file.

Hi Jianyang,

Thanks for the information and the block diagram.

When the LMH1218 is unable to lock, it will remain in a state where it is cycling through the different data rates in an attempt to find one that locks. This is likely why you are seeing the locked data rate value changing.

Since the LMH1218 is able to lock at 3G/6G, this could be a signal integrity issue with the board trace going from LMH1219 OUT0 to LMH1218 IN0 rather than an issue with the LMH1218 register setup. Otherwise, I would have expected to see issues at the lower data rates as well.

Given that there is 14" trace, our LMH1218 should be well-suited to equalize this distance. Is it possible for your customer to share the board layout with us?

Also, is your customer using SigCon Architect to control our device?

Michael

HI Michael,

thanks for your support. 

please check the pcb layout.

thanks!

12GSDI.rar

Customer use MCU control LMH1218/LMH1219.

Hi Jianyang,

Thanks for the information. Looking at the layout, I am only measuring about 31.9 mm from LMH1219 OUT0 to LMH1218 IN0. This is only about 1.25" trace, not 14."

Given that the trace is so short, I would recommend a few things:
1. On the LMH1219, lower the output VOD to 400 mVpp and ensure that de-emphasis is set to 0 dB.
2. Bypass the EQ gain stages 3 and 4 on the LMH1218 (Channel Reg 0x13[1]) to see if this improves the ability for the LMH1218 to lock.

I believe the reason that the FPGA can lock at 12G is because there is enough signal attenuation from LMH1219 OUT1 to the FPGA input to allow the FPGA to incorporate a small amount of CTLE gain to the video signal. In contrast, the LMH1218 on this board is placed very close to the LMH1219.

Thanks,

Michael