DS90UB927Q-Q1: DS90UB927Q-Q1 Test Pattern issue on custom board

Oguzhan Kemal

Part Number: DS90UB927Q-Q1
Other Parts Discussed in Thread: DS25BR110, DS25BR120

Hi all,

I have two different custom pcbs which are one of them has ds90ub927q-q1 FPD LINK III Serializer and the other has ds90ub928 FPD LINK III Deserializer ICs. I can completely read and write all registers via iic channels.

My system diagram shown like below,

In test pattern mode, When i try to get test pattern image, every time i get that screen which is shown below. Is there any suggestion for that sissue?

In normal datapass mode, I get some color mismatch problems which are shown below,

DS90UB927 design;

DS90UB928 design;

over 5 years ago

0 Casey McCrea over 5 years ago

TI__Guru** 103215 points

Hello Oguzhan,

These buffers DS25BR120 and DS25BR110 can not be used in the FPD-Link channel since they are unidirectional. FPD-Link is a bidirectional protocol and the deserializer has its own equalization to compensate for channel loss. I think it is likely that there are some link issues getting caused by having these parts in the middle

Best Regards,

Casey

0 Oguzhan Kemal over 5 years ago in reply to Casey McCrea

Prodigy 60 points

Hello Casey,

Firstly, thank you for your response. Unfortunately, there is no effect to eject DS25BR120 and 110.

I have ds90ub927q-evm board and I have already tested receiver side using 927evm board and image on the screen looks properly. I think, there is a problem on Serializer side.

0 Vijaya Ceekala over 5 years ago in reply to Oguzhan Kemal

TI__Intellectual 2930 points

Hello Oguzhan,

These parts are tested as point to point links and cannot have any devices (buffers or retimers in the middle)

Thanks

Vijay

0 Oguzhan Kemal over 5 years ago in reply to Vijaya Ceekala

Prodigy 60 points

Hi Vijay,

Thank you for your reply. There arent any changes on screen between with buffer and without buffer. I couldnt find any solution..

0 Aaron Heng over 5 years ago in reply to Oguzhan Kemal

TI__Mastermind 37370 points

Hi Oguzhan,

May I know why you are using the buffer between the link?

Aaron

0 Oguzhan Kemal over 5 years ago in reply to Aaron Heng

Prodigy 60 points

Hello Aaron Heng

I used it to increase the communication range but it isnt neccessary for fpd link iii. But it can be used when interface is Fpd link ii. (https://www.ti.com/lit/an/snla111a/snla111a.pdf?ts=1591463249623&ref_url=https://www.ti.com/product/DS25BR120)

0 Oguzhan Kemal over 5 years ago

Prodigy 60 points

Hi all,

Finally, I could solve the problem but I dont know how it was solved.

I am using 24-bit color (8-bit RGB) and VESA bit mapping. Reserved bit (bit27) was logic low in my fpga design. I decided to change reserved bit status as high state and problem solved. Let us know, if you know how it works.

Thank you all.

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DS90UB927Q-Q1: DS90UB927Q-Q1 Test Pattern issue on custom board