TI E2E support forums
TI E2E support forums
  • User
  • Site
  • Search
  • User
  • E2E™ design support >
  • Forums
    • Amplifiers
    • API solutions
    • Audio
    • Clock & timing
    • Data converters
    • DLP® products
    • Interface
    • Isolation
    • Logic
    • Microcontrollers
    • Motor drivers
    • Power management
    • Processors
    • RF & microwave
    • Sensors
    • Site support
    • Switches & multiplexers
    • Tools
    • Wireless connectivity
    • Archived forums
    • Archived groups
  • Technical articles
  • TI training
    • Tech days
    • Online training
    • Live events
    • Power Supply Design Seminar
  • Getting started
  • 简体中文
  • More
  • Cancel
Interface

Interface

Interface forum

  • Mentions
  • Tags
  • More
  • Cancel
  • Ask a new question
  • Ask a new question
  • Cancel
Texas Instruments (TI) Interface support forum is an extensive online knowledge base where millions of technical questions and solutions are available 24/7. You can search interface IC content or ask technical support questions on everything from ESD protection to interfacing with USB, Ethernet, and HDMI. Find the right solution for your circuit design challenges by using our TI E2E™ support forums that are supported by thousands of contributing TI experts.
Frequent questions
  • [FAQ] What is the difference between RMII slave signaling and RMII master signaling?

    Hillman Lin
    Hillman Lin
    RMII slave signaling is connecting 50MHz Crystal to two XI pin of the PHY and/or MAC RMII master signaling is connection 25MHz Crystal to one Master and provide a 50MHz reference lock through REF_CLK pin to the XI pin of the slave side. Slave side does…
    • over 3 years ago
    • Interface
    • Interface forum
  • [FAQ] DP83TC812R-Q1: How can I connect PHYs back to back over RMII?

    Hillman Lin
    Hillman Lin
    Part Number: DP83TC812R-Q1 There are two type of mode that RMII can support: RMII normal mode and RMII Repeater mode: RMII normal mode is also known as MAC to PHY RMII connection. This mode is set as default mode in DP83TC812 so it did not need…
    • over 3 years ago
    • Interface
    • Interface forum
  • [FAQ] DP83TC811S-Q1: Why is Slave/Managed mode PHY linking up with Master/Autonomous PHY link partner?

    Gerome Cacho
    Gerome Cacho
    Part Number: DP83TC811S-Q1 Other Parts Discussed in Thread: DP83TC811R-Q1 When using DP83TC811S-Q1 (or DP83TC811R-Q1), and setting the PHY into managed mode as a slave device via bootstrapping settings, if this device is connected to a master link partner…
    • over 3 years ago
    • Interface
    • Interface forum
  • [FAQ] DS90UH949-Q1: Disable HDCP to work with UB Deserializer

    Alex Reid1
    Alex Reid1
    Part Number: DS90UH949-Q1 Hello, My customer would like to use DS90 UH949 -Q1 devices in place of the DS90 UB949A -Q1 to keep production running. In reviewing the details they have the following questions. Can the HDCP function be disabled? If…
    • Answered
    • over 3 years ago
    • Interface
    • Interface forum
  • [FAQ] Why am I getting "clause-45 not supported" and "error-95" errors with PHY drivers?

    Vikram Sharma
    Vikram Sharma
    Possible reason can be : - "phy_read_mmd" and "phy_write_mmd" are not supported in your kernel version (if version is old). Possible solution to be evaluated : - Change "phy_write_mmd" to "phy_write_mmd_indirect" function and do the corresponding…
    • over 3 years ago
    • Interface
    • Interface forum
  • [FAQ] DS90UB960-Q1: BIST Duration

    ReedKacz
    ReedKacz
    Part Number: DS90UB960-Q1 Hi Team, What is the recommended duration to run the BIST? Thanks Reed
    • Answered
    • over 3 years ago
    • Interface
    • Interface forum
  • [FAQ] How to select correct RGMII delay mode for PHY and MAC?

    Vikram Sharma
    Vikram Sharma
    RGMII standard asks for the introduction of delay in the clock (RX_CLK/TX_CLK) with respect to the respective data (RX_D*/RX_CTRL or TX_D*/TX_CTRL). This delay can be introduced at the source of the clock or at the receiver side. Following table should…
    • over 3 years ago
    • Interface
    • Interface forum
  • [FAQ] How to select the crystal's ppm specification for an Ethernet system?

    Vikram Sharma
    Vikram Sharma
    Other Parts Discussed in Thread: DP83TC811 Ethernet data travels effectively from one MAC to another MAC with two Ethernet PHYs in between. Each of these 4 ICs can have their own reference clocks and crystal attached to each is the usual source of this…
    • over 3 years ago
    • Interface
    • Interface forum
  • [FAQ] DP83867IR: DP83867 digital loopback fail, how to set MII and PCS loopback

    Richard Yang1
    Richard Yang1
    Part Number: DP83867IR Hi Team: Customer side need our help to find the root cause of DP83867 Communication failure issue from one failed board . could you please help to take a look at the attached , customer need to know How to enable MII and PCS…
    • over 3 years ago
    • Interface
    • Interface forum
  • [FAQ] RGMII Timing - Align and Shift mode

    Gokul Koraganji
    Gokul Koraganji
    Definitions: TX_DATA[3:0], TX_CLK (naming of TI Ethernet PHYs) are transmitted by the MAC/(Repeater PHY) and RX_DATA[3:0], RX_CLK (naming of TI Ethernet PHYs) are transmitted by Ethernet PHY. S.No Mode Definition 1 PHY: RX Align…
    • over 3 years ago
    • Interface
    • Interface forum
<>

View FAQ threads
  • Tags
  • RSS
  • More
  • Cancel
  • Suggested Answer

    DS92LX1621: Compatibility Channel Link III serializer and FPD Link deserializer 0 Locked

    1299 views
    5 replies
    Latest over 7 years ago
    by Ikechukwu Anyiam
  • Not Answered

    TUSB4041I: unable to connect to downstream side 0 Locked

    410 views
    3 replies
    Latest over 7 years ago
    by Shinichi Inoue
  • Suggested Answer

    ONET1151L: ONET1151L connecting to TOS with cathode of the photodiode is common with the anode of the laser driver… 0 Locked

    1108 views
    1 reply
    Latest over 7 years ago
    by Sriharsha Kota Pavan
  • Suggested Answer

    DS90C387A: DS90C387A under what conditions support 170M clock input? 0 Locked

    393 views
    1 reply
    Latest over 7 years ago
    by Palaniappan Manickam
  • Suggested Answer

    DS90C387A: Can DS90C387A work in 138M's input clock and single pixel mode? 0 Locked

    458 views
    1 reply
    Latest over 7 years ago
    by Palaniappan Manickam
  • Answered

    DS90UB940-Q1: 7/8-bit Address 0 Locked

    607 views
    1 reply
    Latest over 7 years ago
    by Palaniappan Manickam
  • Answered

    DS90UB960-Q1: virtual channel 0 Locked

    458 views
    1 reply
    Latest over 7 years ago
    by Palaniappan Manickam
  • Suggested Answer

    DS90UR910-Q1: BIST mode 0 Locked

    601 views
    1 reply
    Latest over 7 years ago
    by Palaniappan Manickam
  • Answered

    DS90LV027A: Input Hysteresis 0 Locked

    525 views
    1 reply
    Latest over 7 years ago
    by Yaser Ibrahim
  • Answered

    XIO3130: Bitween EP and EP communication on XIO3130 0 Locked

    527 views
    2 replies
    Latest over 7 years ago
    by Charley Cai
  • Suggested Answer

    DS90UR910-Q1: Configure register 0 Locked

    598 views
    1 reply
    Latest over 7 years ago
    by Palaniappan Manickam
  • Suggested Answer

    DS90UB934-Q1: compatibility check about DS90UB953 - DS90UB934, DS90UB913 - DS90UB934 0 Locked

    687 views
    1 reply
    Latest over 7 years ago
    by Palaniappan Manickam
  • Suggested Answer

    HD3SS214: Reference Schematic 0 Locked

    588 views
    2 replies
    Latest over 7 years ago
    by Malik Barton57
  • Suggested Answer

    TUSB1002: Optimizing Eq Settings 0 Locked

    427 views
    3 replies
    Latest over 7 years ago
    by Malik Barton57
  • Suggested Answer

    SN65DSI83: Do we have the android 7.1 drive of the device SN65DSI83? 0 Locked

    549 views
    1 reply
    Latest over 7 years ago
    by Joel Jimenez0
  • Suggested Answer

    TUSB8041: Solution Inquiry 0 Locked

    276 views
    3 replies
    Latest over 7 years ago
    by Michael.Walker
  • Not Answered

    BQ24392: BQ24392 spec Table 1 says "Charge with 100mA" for CDP when GOOD_BAT is LOW, CHG_AL_N is LOW and CHG_DET is HIGH 0 Locked

    750 views
    1 reply
    Latest over 7 years ago
    by JMMN
  • Suggested Answer

    MAX3232: Asking for the MAX3232 abnormal waveform 0 Locked

    5565 views
    11 replies
    Latest over 7 years ago
    by Miguel Robertson
  • Suggested Answer

    TRS213: Questions and Schematic Review 0 Locked

    847 views
    2 replies
    Latest over 7 years ago
    by Miguel Robertson
  • Suggested Answer

    TUSB1210: If tusb1210 could be both host and device under UART mode 0 Locked

    373 views
    1 reply
    Latest over 7 years ago
    by JMMN
<>