SN74HC595: Logic forum

For newer chips, the letters "TI" are the correct logo.

I suspect that your CS_CLK waveform has ringing at the edges. Please show two waveforms, zoomed in so that it is possible to see the slope of a rising and a falling edge.

Here are the rising and falling edge, does that have an impact?

What confuses me is why SN74HC595DR can be used, but SN74HC595DRG4 cannot be used if their parameters are the same

That sounds reasonable. I'll try to eliminate the ringing first and see if it will return to normal, thanks.

Hi Clemens, I tried to solve the ringing problem, but later I found that it was caused by the oscilloscope probe. After I replaced the oscilloscope probe and connected it to the pin as soon as possible, the ring was reduced to less than 1V, which should not affect the normal clk signal, but the output of the 595D chip is still abnormal, do you have any other suggestions? thanks.

Hi Clemens, the clock frequency I am using is approximately 100KHz, and this device supports a maximum of 25MHz. If the clk speed is too slow, may it cause poor device performance?

Hi Clemens, I have optimized the CLK signal, and now there is no ringing, but there are still problems with the output. QA to QH are all 0, and the shift period of the QH_ is also wrong. Do you have any other suggestions?

QA…QH change when triggered with RCLK.

The last two input bits are 0, so when each clock pulse is read as four pulses, you get all zeros.

Might this chip be damaged? Does this still happen when you replace it?

What did you do to optimize the CLK signal?

This is a common issue for SN74HC595DRG4, which own a "TI" letter logo. The 8 pieces I purchased cannot be used, and the waveform is similar. I purchased them from an official designated supplier, so the quality should not be a problem. Regarding the elimination of ringing, I connected a 33R resistor to the clk signal line.

This is my all schematic, the input signal is reversed and isolated by optocoupler, the data chain is DAC+595D+595D, there are 25bits data every period, DAC retains 16 bits, do you currently prefer to think that this is a timing issue or a signal quality issue?

Hi Clemens, this is the layout and the location of the 33R.I am trying to buy and test S595 chip.

Hi Clemens, I used sn74HCS595DR for testing, unfortunately the output is still incorrect, similar to the phenomenon I encountered before. I am looking for the reason. Do you have any other suggestions or ideas

Hi Albert, it's still ringing on the rising edge. s595d does not seem to suppress oscillations.

Hi Albert&Clemens, I have found the root cause, due to the long rise time of the input signal of SN74LVC3G34, uncertain signal appeared in the output, causing clock oscillation,do you have a recommended chip that can replace SN74LVC3G34 and accept long rise time input without causing output uncertainty? Thanks.

Hi Clemens, thanks, I will try SN74LVC3G17.

By the way, since the ring's frequency is larger than 100MHz, does it mean that the SN74HC595DR can operate at frequencies larger than 100MHz?