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When a capacitor is discharged as a result of power-down, current flows to an internal protection diode and is returned to VCC via the input pin. Therefore, a large load capacitance should not also be connected directly to an input pin. A capacitor of up to 500 pF may be connected directly to the input of a CMOS IC, but when a larger capacitor is required, a current-limiting resistor (Rs) should be connected between the IC input and a capacitor as shown in Figure 2.1.
CMOS ICs with an input-tolerant function do not need a current-limiting resistor (Rs).
The potential problem is the current through the ESD protection diode between the input pin and VCC (which is not shown in the circuit above). Size the series resistor so that that current is not exceeeded. In any case, the absolute maximum ratings of the equivalent families are pretty much identical between TI and that other vendor, so you can use the same numbers.
If you add a capacitor to get a delay or decoupling, this also requires a resistor, which makes the signal edges slower. For devices without Schmitt-trigger inputs, you have to ensure that these edges do not exceed the input transition rise or fall rate (Δt/Δv) limit, which is listed in the datasheet and depends on family and supply voltage.
Using our new HCS family of logic devices (has the same supply range as the families you listed) you won't have to worry about input transition rate. Typically, a resistor isn't required when adding a cap to the input, but as Clemens said if you plan on the signal going above Vcc + .5 V its necessary to have one to limit the current through the ESD diode.
