AM2434: Supports 10 Mbps with RGMII on CPSW3G

Hi Daisuke,

Since the experts on this matter are in holiday from 11/14 - 11/15, so the response may be delayed. Thank you for your patience.
Best regards,
Ming

Hi Daisuke Maeda,

Apologies for delayed response.Yes, In band mode is needed for 10 Mbps RGMII.

To operate on 10 Mbps RGMII mode, make the following change in "EnetApp_initLinkArgs" function in your project:

Change as shown below:

After this, rebuild your project. Please let me know if you face any issues with the same.

Regards,
Shaunak

Hi Shaunak-san,

Thank you for your reply.

Could you also answer the rest of my questions?

Daisuke Maeda said:

Are there any requirements for PHY to be used at 10 Mbps with RGMII on CPSW3G?

For use at 10 Mbps with RGMII on CPSW3G, is it required to use in-band mode and a PHY that supports in-band status?

Best regards,

Daisuke

Hi Shaunak-san,

I do not have EVM handy, so I cannot check it right away.

I found a post that tried the change "EnetApp_initLinkArgs" but had an issue.

e2e.ti.com/.../am243x-cpsw-10mbps-packet-transmission-error

You said let me try and reproduce it locally.

I would appreciate it if you could try it with other examples or with the latest MCU+ SDK 09.00.00.35.

Best regards,

Daisuke

Hi Daisuke-san,

Yes, In band mode is required for 10 Mbps RGMII to work. I'll leave a couple of references down here if you want to read more about it:

• CPSW In-Band Operating Mode of RGMII question... - Processors forum - Processors - TI E2E support forums
• RGMII 10Mbps problem - Processors forum - Processors - TI E2E support forums

The other issue reported with 10 Mbps UDP communication is being looked into right now. I'll keep you posted on the same after some internal testing. I'll get back to you by early next week.

Regards.
Shaunak

Hi Shaunak-san,

Thank you for your reply.

How to modify the code to set the EXT_EN bit in the CPSW_PN_MAC_CONTROL_REG_k register?

In the MCU+ SDK, "CSL_CPGMAC_SL_enableExtControl()" in csl_cpgmac_sl.c is provided to set the EXT_EN bit in the CPSW_PN_MAC_CONTROL_REG_k register, and other functions and macros are defined to access the Enet registers, but they seem to be unused and seem to be instead accessed via the IOCTL interface.

How to set the EXT_EN bit in the CPSW_PN_MAC_CONTROL_REG_k register via the IOCTL interface?

It seems that the relevant ENET registers are set in EnetApp_driverOpen().

Can "CSL_CPGMAC_SL_enableExtControl()" be added after EnetApp_driverOpen()?

Best regards,

Daisuke

Hi Shaunak-san,

Thank you for your support. Our customer is waiting for your reply.

Please give me an answer as soon as possible. Your prompt reply would be appreciated.

Best regards,

Daisuke

Hi Shaunak-san,

Sorry for many times. Our customer is waiting for your reply.

Please give me an answer as soon as possible. Your prompt reply would be appreciated.

Best regards,

Daisuke

Hi Daisuke,
You may call it after EnetApp_driverOpen(), however calling there does not seems a good idea from software point of view,
Our suggestion is to modify in the below function in driver source code.
 
File :'source/networking/enet/core/src/mod/cpsw_macport.c':

static int32_t CpswMacPort_setInterface(CSL_Xge_cpswRegs *regs,
                                        Enet_MacPort macPort,
                                        const EnetMacPort_Interface *mii)
{

....

    else if (EnetMacPort_isRgmii(mii))
    {
-       CSL_FINS(macControl, XGE_CPSW_PN_MAC_CONTROL_REG_EXT_EN, 0U);
+       CSL_FINS(macControl, XGE_CPSW_PN_MAC_CONTROL_REG_EXT_EN, 1U);
        CSL_FINS(macControl, XGE_CPSW_PN_MAC_CONTROL_REG_GIG_FORCE, 1U);
        status = ENET_SOK;
    }
...
}

After the above change, you have to clean & recompile the libraries:

gmake -s DEVICE:=am243x PROFILE:=release libs-clean
gmake -s DEVICE:=am243x PROFILE:=release libs
gmake -s DEVICE:=am243x PROFILE:=debug libs-clean
gmake -s DEVICE:=am243x PROFILE:=debug libs-clean

Then recompile your application / project along with the changes done in "EnetApp_initLinkArgs" function to set link speed as 10mbps-

Thanks and regards,

Pradeep

Hi Pradeep-san,

Thank you for your reply.

I modified the code, built the library and example below, and ran it on EVM, but it still links up at 1-Gbps.

C:\ti\mcu_plus_sdk_am243x_09_00_00_35\examples\networking\enet_layer2_cpsw

After running it, the EXT_EN bit in the CPSW_PN_MAC_CONTROL_REG_0 register (0802 2330h) was set to 1b.

Additionally, I cleared the GIG_FORCE bit in the CPSW_PN_MAC_CONTROL_REG_0 register (0802 2330h) to 0b, but it still links up at 1-Gbps.

Have your proposed modifications been tested?

What other modifications are needed for it to link at 10M-bps?

Best regards,

Daisuke

Hi Pradeep-san,

I suspect that the PHY (DP83867) is still set to 1-Gbps.

Does the change below also force the PHY side to 10-Mbps?

linkCfg->speed = ENET_SPEED_10MBIT;

If no, how to modify to force the PHY to 10-Mbps?

Best regards,

Daisuke

Hi Pradeep-san,

Sorry for many times. Our customer is waiting for your reply.

To link up the DP83867 at 10-Mbps, the bits in the following registers will need to be set.

ANAR[8].TX_FD = 0b: 100BASE-TX Full Duplex not supported
ANAR[7].TX = 0b: 100BASE-TX not supported
ANAR[6].10_FD = 1b: 10BASE-Te Full Duplex is supported by the local device
ANAR[5].10BASETe_EN = 1b: 10BASE-Te is supported by the local device.

CFG1[9].1000BASE-T FULL DUPLEX = 0b: Do not advertise 1000Base-T Full Duplex ability
CFG1[8].1000BASE-T HALF DUPLEX = 0b: Do not advertise 1000Base-T Half Duplex ability

DP83867IR/CR Robust, High Immunity 10/100/1000 Ethernet Physical Layer Transceiver datasheet (Rev. G)
Table 8-13. Auto-Negotiation Advertisement Register (ANAR), Address 0x0004 (Page 63)
Table 8-18. Configuration Register 1 (CFG1), Address 0x0009 (Page 69)

How to modify the code to set the PHY registers?

The codes below seems to be used to set the PHY registers, but I cannot find it to modify.

C:\ti\mcu_plus_sdk_am243x_09_00_00_35\source\networking\enet\core\src\phy\
dp83867.c
enetphy.c

Please give me an answer as soon as possible. Your prompt reply would be appreciated.

Best regards,

Daisuke

Hi Daisuke,

About this

Daisuke Maeda said:

Does the change below also force the PHY side to 10-Mbps?

linkCfg->speed = ENET_SPEED_10MBIT;

Yes, it does.

Does your PHY support In-band signaling mode?  The same solution is suggested to another customer and it has worked, more details - https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1292683/am243x-cpsw-10mbps-packet-transmission-error

Daisuke Maeda said:

The codes below seems to be used to set the PHY registers, but I cannot find it to modify.

C:\ti\mcu_plus_sdk_am243x_09_00_00_35\source\networking\enet\core\src\phy\
dp83867.c
enetphy.c

Please give me an answer as soon as possible. Your prompt reply would be appreciated.

Thanks for your patience! I will recreate this today and let you know more details in a day.

With regards,
Pradeep

Hi Pradeep-san,

Thank you for your reply.

PRADEEP HN said:

Does your PHY support In-band signaling mode?  The same solution is suggested to another customer and it has worked, more details - https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1292683/am243x-cpsw-10mbps-packet-transmission-error

I guess they are testing with a 10-Mbps link partner.

PRADEEP HN said:

Thanks for your patience! I will recreate this today and let you know more details in a day.

Thank you for your kindly support!
Please give me an answer as soon as possible. Your prompt reply would be appreciated.

Best regards,

Daisuke