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Original question:

TMS320F28388D: MCAN Debug

TMS320F28388D: C28x Cache, Pipeline, and ECC

Lawrence Wong
Genius 16360 points

Part Number: TMS320F28388D

Tool/software:

Customer have a couple questions regarding cache and pipelines on the C28x processor.

 

Cache

They have read that the FLASH memory has cache and prefetch features that can be disabled.  

  1. They want to confirm that there are no other cache on this chip like for example a RAM cache.  Is this correct?

 

Pipeline

The Technical Reference Manual references a pipeline for the CLA, CLB, DMA, and an instruction pipeline.  

  1. Is there any other pipeline functionality on the chip other than these?  
  2. Can you disable any pipeline functionality?
  3. What is the impact if data is corrupted in the pipeline? 
  4. Is pipeline data ECC protected?

 

ECC

They are using the ECC feature of FLASH memory to store our application code, however, they copy a lot of this code into ECC protected RAM space(LSRAM sectors) so that it executes faster.  They are wondering how this copying works with ECC.

  1. Does the chip copy the already calculated ECC section of FLASH into RAM along with the code?  Or does it regenerate the ECC at the time of copying?
  2. Is register RAM ECC protected?  For example, are ADC configuration registers protected by ECC?
  • 0
    TI__Genius 11081 points

    Hello Lawrence,

    In general, for functional safety questions I would recommend reviewing the safety manual for this device. That will provide a lot more detail than I can cover in this post.

    On cache: The data cache is specifically a part of the Flash wrapper to improve performance of data read accesses to Flash. It is disabled by default and must be enabled by software to function.

    On ECC: For this architecture, ECC is not centralized - it does not have end-to-end safety on the data and peripheral buses. The Flash module has its own ECC logic, and the memory controller for the RAMs has its own ECC logic. ECC is decoded and error checking happens when Flash memory is read, before it goes on the bus. When writing the data to a RAM that is ECC protected, the memory controller computes the ECC associated with each word and writes it along with the data coming from the data bus.

    Peripheral registers are generally not ECC protected. Message RAMs (e.g. for CAN) generally have parity protection. Global RAM (GSx) is also parity-protected. For details, please refer to the device data sheet.

    Pipelines: There is no other pipeline other than what is described in the TRM. The C28x and CLA instruction pipelines are fundamental to the CPU architecture, so there is no such concept as disabling them. This device does not have a lockstep feature; for a similar performance device with lockstep CPU, perhaps take a look at the F28P65x device. Similarly for the DMA, the pipeline is fundamental to the architecture of the module, so there is no concept of disabling it.

    On CLB pipeline mode: this is required for high frequency CLB operation (>100MHz). It does have an enable bit that is software controlled.

    Best regards,
    Ibukun

  • 0
    TI__Genius 11081 points

    On the question of cached memories: There is no cache other than the "data cache" in the Flash which is really just a line buffer for performance (not a cache in the traditional sense). It only serves as a line buffer to improve sequential read performance on data accesses. The C28x architecture is designed for maximal real-time performance, and part of that DNA means we do not use caching on principle in order to maintain strict determinism and low latency for processing operations.

    Best regards,
    Ibukun

  • 0 in reply to Ibukun Olumuyiwa
    TI__Genius 16360 points

    Thanks Ibukun,

    Let me share this with the customer and will let you know if there are any follow up questions.

    Regards,

    Lawrence