TMS320F28388D: C28x Cache, Pipeline, and ECC

Hello Lawrence,

In general, for functional safety questions I would recommend reviewing the safety manual for this device. That will provide a lot more detail than I can cover in this post.

On cache: The data cache is specifically a part of the Flash wrapper to improve performance of data read accesses to Flash. It is disabled by default and must be enabled by software to function.

On ECC: For this architecture, ECC is not centralized - it does not have end-to-end safety on the data and peripheral buses. The Flash module has its own ECC logic, and the memory controller for the RAMs has its own ECC logic. ECC is decoded and error checking happens when Flash memory is read, before it goes on the bus. When writing the data to a RAM that is ECC protected, the memory controller computes the ECC associated with each word and writes it along with the data coming from the data bus.

Peripheral registers are generally not ECC protected. Message RAMs (e.g. for CAN) generally have parity protection. Global RAM (GSx) is also parity-protected. For details, please refer to the device data sheet.

Pipelines: There is no other pipeline other than what is described in the TRM. The C28x and CLA instruction pipelines are fundamental to the CPU architecture, so there is no such concept as disabling them. This device does not have a lockstep feature; for a similar performance device with lockstep CPU, perhaps take a look at the F28P65x device. Similarly for the DMA, the pipeline is fundamental to the architecture of the module, so there is no concept of disabling it.

On CLB pipeline mode: this is required for high frequency CLB operation (>100MHz). It does have an enable bit that is software controlled.

Best regards,
Ibukun

On the question of cached memories: There is no cache other than the "data cache" in the Flash which is really just a line buffer for performance (not a cache in the traditional sense). It only serves as a line buffer to improve sequential read performance on data accesses. The C28x architecture is designed for maximal real-time performance, and part of that DNA means we do not use caching on principle in order to maintain strict determinism and low latency for processing operations.

Best regards,
Ibukun