• State TI Thinks Resolved
  • Locked Locked
  • Replies 10 replies
  • Answers 1 answer
  • Subscribers 64 subscribers
  • Views 289 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

TPS650864: Troubleshooting PMIC used to power Xilinx ZU3

TPS650864: TPS65086401RSKT Power supply issue

Santosh Singh
Prodigy 130 points
Part Number: TPS650864
Other Parts Discussed in Thread: TPS650861

Hi,

We are using  PMIC to power up our Xilinx Ultrascale MPSOC XCZU11EG. The power supply from PMIC is not stable and keeps dipping. We have observed the following problem:

1) When CTL1 is high, Buck 2 comes up

2) Then after some miliseconds, Buck1 and LDOA1 and LDOA2 starts ramping but as they reach their level , Buck1 and LDOA2 starts falling down slowly after a points , LDOA1 falls sharply to zero and all starts rising again and this process goes on

3) Buck 6 also goes up and then ramp down

GPO1 is always low and we have disconnected all loads from the supply

Please let us know what the issue is and how we can resolve it. Schematic is attached for your reference.

.1185.PMIC schematic.pdf

  • 0
    TI__Mastermind 18620 points

    Hi Santosh,

    This repeated reset behavior indicates that the PMIC is experiencing a power fault during power-up and is resetting the sequence. Since CTL1 is pulled HIGH the power sequence attempts to restart after every reset.

    Please go through the TPS65086x Schematic and Layout Checklist (Rev. A) and mark each item as "Used (or Not Used) & Complete". Once that is done, share the document here and I can give the schematic a second pass.

    Do you have the ability to read the registers from the device using I2C? If you can, a full register dump would help determine where the IC is detecting a fault (specifically registers 0x02, 0x05, and 0xB2 through 0xB6).

    Regards,

    James

  • 0 in reply to James Steenbock
    Prodigy 130 points

    Hi James,

    We are trying to access the device using I2C (using aardvark tool) but we are not getting any acknowledgement from the device at default address 0X5E. We are getting LDO3P3 and LDO5P0 supply on our board. Can you suggest how can we access the I2C of this device ?.

    In the checklist , I2C are recommended to pull up with 1.8V supply but we have pull up with LDO3P3 supply . As per the datasheet, it operating voltage is upto 3.3V supply. Also the control signal are recommended to pull up with 1.8V supply but we have pulled with LDO3P3. Please suggest if it is ok to pull up with 3.3V? Also suggest way to connect to I2C for debugging.

    Regards

    Santosh Kr. singh

  • 0 in reply to Santosh Singh
    TI__Mastermind 18620 points

    Hi Santosh,

    The 3.3V pull-up is fine for both I2C and CTLx pins.

    If the I2C lines are already pulled up to 3.3V using LDO3V3, you should only need a device that can drive the I2C lines externally and handle any handoffs for read/write.

    I'm not familiar with the aardvark so I don't have any specific advice for that tool. I would probe the I2C lines when you send a command to see where the protocol is failing (i.e. check each stage of the I2C command on oscilloscope to see if the SDA/SCL lines are being pulled down correctly according to the protocol).

    As long as you have VSYS above UVLO with LDO3P3 and LDO5P0 active, the digital internals should be awake and the device can receive I2C commands. If possible you will want to use the lowest capacitance probes you have to view the I2C lines (pF if possible) but anything you can to to get an idea of the I2C behavior will work.

    Regards,

    James

  • 0 in reply to James Steenbock
    Prodigy 130 points

    We have probed the I2C signal on our board through Tektronix oscilloscope. We have configured 100KHz clock speed from our tool and device address 0X5E. When we tried to detect our PMIC device using this address, we did not get any acknowledgement bit from PMIC device. As per the datasheet , the default address of the device is 5E. Can you please review our schematic and let us know if there is any issue. We have updated the checklist for the schematic and the same is attached for your reference.TPS650860 Schematic Checklist^J Layout Checklist.xlsx8203.PMIC schematic.pdf

  • 0 in reply to Santosh Singh
    TI__Mastermind 18620 points

    Hi Santosh,

    Thank you for providing the schematic document. We have a large amount of support going on right now so review turnaround time is 1 week. I will try to fit this review in sooner but there's some urgent lab testing that needs to be finished by Thursday this week.

    Regards,

    James

  • 0 in reply to James Steenbock
    Prodigy 130 points

    Hi James,

    We are able to read the register,  we came to know that the power fault is due to SWA1 (register B2 value was 01000000). We have ground the SWA1 input and kept the SWA1 output floating but still the power fault was there in SWA1. So we disabled the SWA1 through I2C and all power came . Currently we are testing without any load on supplies. Can you tell us why SWA1 is causing power fault and sequence reset? 

    Regards

    Santosh Kr. singh

  • 0 in reply to Santosh Singh
    TI__Guru* 79203 points

    Hi Santosh, 

    James will not be able to respond until Tuesday (Friday is a US holiday and he will be out on Monday). Let's see if he finds anything when he reviews the schematic that might provide insight into the fault on SWA1.

    Best regards,

    Matt

  • 0 in reply to Matt Sunna
    Prodigy 130 points

    Hello,

    SWA1 issue resolved when we pulled down CTL5 pin.

    But after connecting load to all the supplies, there is a power fault in LDOA3 due to which the power sequence restarted and all the power supplies were showing glitch. When we disable the LDOA3 since we are not using it, the BUCK5 supply is not coming. 

    (1.) Why there is a power fault in LDOA3, which was not there when there was no load ?

    (2.) Why does BUCK5 supply get disabled when we disable the LDOA3 through I2C ?

    (3.) How can we enable BUCK5 while disabling the LDOA3 ?

    Best regards,

    Santosh

  • 0 in reply to Santosh Singh
    TI__Guru* 79203 points

    Hi Santosh,

    James should be able to provide further guidance when he returns tomorrow (4/2).

    Best regards,

    Matt

  • 0 in reply to Matt Sunna
    TI__Mastermind 18620 points

    Hi Santosh,

    I have some feedback on your schematic:

    • The BUCK1 output is labeled as BUCK5_1V8 but it is set up for 5V output with the resistor divider configuration.
      • BUCK1 should be set to 1.8V by default for the TPS65086401 so you do not need the R649 and R661 components.

    • It is recommended to use a 10uF capacitor for each PVINx input for stability

    • V5ANA output should have a 1uF bypass capacitor

    • VTT output needs at least 35uF output capacitance (after derating)

    • SWA1 is enabled by default for the TPS65086401 so you will need to use the 0.1uF output capacitor on this rail. You will also need to supply the correct input voltage (3.3V) to the PVIN_SWA1 pin to avoid a power fault. Disabling this rail through I2C or masking the SWA1 PGOOD would allow you to operate the device without SWA1 components.

    • GPO1 is an open drain output which means this pin will require a pull-up source to function. It doesn't look like the GPO1 output is tied to a pull-up source yet.
      • This would affect the operation of CTL4 and CTL6 from what I understand.
    • CTL2 does not appear to be connected to a pull-up source since the resistor connection to LDP3P3 is marked as NU.

    • GPO3 doesn't appear to be connected to a pull-up source either but if GPO3 is unused it can remain floating.

    To answer your questions:

    Santosh Singh said:
    Why there is a power fault in LDOA3, which was not there when there was no load ?

    There may be an issue with LDOA3 in the sequence or there may be an issue with a different rail that causes LDOA3 to trip a power fault. We need scope captures of the power sequence starting from VSYS, LDO5P0, LDO3P3, and CTL1 in order to begin tracking down the first fault. I would use an o-scope to follow the power up sequence until you find a power rail that fails to ramp up to the correct voltage. The goal is to find the first source of a reset condition.

    Make sure the current limit of the LDO is not exceeded as this would cause a voltage drop and power fault.

    Santosh Singh said:
    Why does BUCK5 supply get disabled when we disable the LDOA3 through I2C ?

    BUCK5 is tied to LDOA3 PGOOD and SWB1_B2 PGOOD internal signals for this IC version. This means that if LDOA3 does not reach PGOOD status, BUCK5 will not enable.

    Santosh Singh said:
    How can we enable BUCK5 while disabling the LDOA3 ?

    The PGOOD dependencies are part of the programming registers so you would need to enter programming mode on the PMIC in order to change the PGOOD settings.

    For pre-programmed versions like the TPS65086401 we do NOT recommend changing the programming permanently as this creates confusion later when the settings don't match our records. For custom programming we always recommend the TPS650861 which is the user-programmable version that comes with a blank OTP bank to start.

    A quick workaround you could do after every power cycle is changing BUCK5 to ENABLED by writing register 0xA0 bit 4 = 1'b. This should circumvent the PGOOD requirement from LDOA3 and SWB1_B2.

    Regards,

    James