UCC28019A: UCC28019A

Hello Sir, 

Yes, the gain and phase compensations of the current loop (Figure 30) and the voltage loop (Figure 32) are satisfied independently.

The 0dB cross-over frequency of the current-loop is generally up at several kHz, while the cross-over frequency of the voltage loop is generally around 10Hz.

Regards,
Ulrich

Hello Sir, 

In a stable feedback loop, there is always some degree of phase margin and gain margin.  
In typical DC-DC voltage or current regulation control, the designer typically strives to attain at least 45 degrees phase margin at 0dB gain, and 20dB gain margin at 180 degree phase shift. 

In the UCC28019A, the current loop compensation has limited flexibility for design.  
In the gain/phase plot you posted above, the 0dB crossover is at 10kHz and has ~40 degrees phase margin. At 180 degrees, it has more than 80dB gain margin.  This is less than ideal phase margin, however it is still a reasonably stable loop. 

Higher ICOMP capacitance can decrease the crossover but reduce the phase margin even more.
Lower ICOMP capacitance can increase the crossover and increase the phase margin, but leave the loop susceptible to reaction to high frequency disturbances and increases harmonic distortion. 

With the UCC28019A, the compensation of the ICOMP loop is a tradeoff between amount of phase margin versus amount of harmonic distortion.

Regards,
Ulrich

Hello Sir,

I have modified the UCC28109A design calculator as I think is appropriate for your application.

It is attached here, and if you use the compensation values that I have entered, I believe that you will have a stable design.  
1781.UCC28019A Design Calculator_標準電源(2025-04-04).xls

Regards,

Ulrich

Hello Sir, 

The usual course of design for PFC is to design for stability at maximum load and minimum input line. 
Most people design for phase margin, without worrying about gain margin.     

When the prototype board is constructed, the designer will evaluate operation over the full load and line ranges to verify stability and performance. 
If compensation adjustments are required for any particular set of operating conditions, they are addressed at that time. 

Regards,
Ulrich

Hello ?? ??, 

I'm sorry, but I don't have time to prepare an explanation of loop compensation theory for this device. 

When properly used, the UCC28019A Calculator tool will generate component values for voltage-loop and current-loop compensation that will provide good performance over the line and load range.  Further optimization of transient response can be done by empirical variation of those values during prototype evaluation. 

But only one set of values are normally used to cover all line and load conditions, and good results are obtained despite being less optimal at some conditions than at others.
If you require optimal phase and gain margin at all line and load conditions, this will involve some kind of active, adaptive compensation scheme where values adjust with the conditions. 
Such a scheme is beyond the scope of this support forum.   

Regards,
Ulrich

Hello, 

For calculations with an inductance that changes with DC bias current, use the lowest inductance at the highest peak line current, not the peak ripple current.
For example, for a 1000W PFC input power at 85Vac, Iin_rms = 11.765Arms.  The peak of this line current= 16.64A. 
For input at cell C57 on the 'CALCULATIONS' sheet, use the inductance of the coil when biased with 16.64A current. 

Your understanding of the phase and gain margins of Figures 30 and 32 in the UCC28019A datasheet is correct. 
The author of the applications section and of the calculator tool apparently calculates the Phase of the Current-Loop response, but calculates the Phase Margin of the Voltage-Loop response. 

I don't know the reason for this inconsistency. 
The results are correct, but the user should be aware that one graph plots Phase and the other plots Phase Margin. 

Regards,
Ulrich

Hello, 

To address your questions from the last three postings: 

1.  It is possible to estimate the rise time of PFC, but the result may be a wide range depending on input voltage, output loading, and a few other factors  during the power-up time.  Some of those factors are whether or not the AC input exceeds the VINS brown-in threshold, whether VCC is in-spec before or after AC voltage is applied, and how much inrush current-limiting there is and for how long. 

2.  I believe the PFC is not operating after the 20ms line interruption because I believe that the VINS voltage has fallen below the brown-out threshold and triggered an IBOP fault.  This fault then discharged the COMP voltage.  Restart time for the UCC28019 is the time needed for Vvins to rise to the brown-in threshold plus the soft-start time for Vcomp to rise high enough to deliver full power to the PFC output. 
By the way, your waveform of the PFC output restarting gives a good indication of the PFC rise time without the need for calculations. 

3.  I think that extending the current-loop stability calculations to a no-load condition is taking the concept of loop-stability and phase-margin too far. 
I am not aware of anyone who was ever concerned about this (for a PFC design).   No-load output power means 0A input, so current-loop stability is not an issue in that case.

Consider that for a very light but non-zero load, the ideal input current would be very small. Even a completely unstable current loop can only oscillate at the crossover frequency and that frequency is broken up over several switching cycles so the main result is that there will be high harmonics in the input current.  At the same time there will be purely sinusoidal reactive current in the EMI filter X-caps which will dominate over the PFC load current, so the actual distortion seen by a current probe will be small.  To the extent that the current loop is only marginally stable and not completely unstable is actually a better situation.  
And the current-loop is hidden within the PFC voltage-loop which does not become marginally stable, so the PFC output is unaffected. 

I suggest to evaluate the PFC performance while varying the line and load and see if there are any points of operation that show unacceptable behavior.
Then those points, if any, can be addressed as needed. 

Regards,
Ulrich

You are correct that the output voltage initially rises in just capacitor input form, but after exceeding Vcc and Browne-in threshold, the output voltage rises based on the amount of input current allowed by the VCOMP voltage as the VCOMP voltage rises. 
This does not actually follow any fixed soft-start slope.  

Instead, since the AC input current varies with the AC input voltage at the same time that the amount of current is increasing with rising VCOMP, the output voltage will exhibit variable rates of rise until it settles into regulation.  

Because the soft start is not an independent function, but actually is a side-effect of the VCOMP compensation component values, the slow loop response often results in a slight output overshoot before it settles into regulation, unless the output is heavily loaded during start-up time. 

So many variables make it very difficult to derive any generalized equation to calculate the exact rising voltage waveshape. 
To do so would be an academic exercise, because normally such a prediction is not necessary.  
Worst-case estimations using minimum and maximum conditions and parameters are usually sufficient for most design work. 

Regards,
Ulrich

Hello Sir, 

The voltage of VCOMP should normally always be smooth except under two conditions: 
1.  An internal "FAULT" signal will pull VCOMP voltage to GND very suddenly.  FAULT can be from 1 of 3 different faults: VCC UVLO, IBOP (Brownout), and OLP (open-loop protection, where VSENSE < 0.82V).  When a FAULT clears, the UCC28019A restarts in a Softstart mode. 

2. The EDR (Enhanced dynamic response) function will increase the gain of the VCOMP error amplifier by about 10X, which will cause VCOMP voltage it increase much aster than when EDR is no tin effect.  EDR happens when VSENSE falls <95% of regulation (5.00V).  

The jagged drops in VCOMP are not normal responses to internal signals.  Do you have any external circuits attached to VCOMP other than the usual 2C +1R compensation components?  

The difference in VCOMP rise time just before the 20ms dropout and the rise time just after the dropout ends is the difference in error-amp gain due to EDR.
Prior to the 20ms dropout, VSENSE was in regulation and SS was finished, so EDR is enabled.  When the 20ms dropout began, VSENSE began dropping and triggered EDR at 4.95V.  SO VCOMP rose very fast. 
But the VINS input voltage dropped below the Brownout threshold (~0.82V) triggering IBOP fault which discharged VCOMP immediately.  When the dropout cleared and AC restored, a soft-start began and EDR is disabled during soft start, so VCOMP rise is slower. 

Note: for a 20ms AC dropout, you can avoid the shutdown and restart if you increase the capacitor on the VINS input.  I suggest to double its value. 

Regards,
Ulrich

Hello Sir, 

The VCOMP waveform at start-up can be seen as Ch2 trace in Figure 12 in the UCC28019A EVM User guide (page 11): 
https://www.ti.com/lit/pdf/sluu325 

I don't have any ICOMP waveform examples to show, but normally ICOMP resembles a rectified sine wave offset above GND by about 1.5V.  

Regards,
Ulrich

Hello Sir, 

You are correct; when starting from 0V the VCOMP voltage is not linear over its entire ramp, but it is mostly linear over the important part of soft-start.

Your simulation starts with the capacitor initial conditions of 0V.  The current source drives 30uA first into C1.  As the voltage of C1 rises quickly (because of its low value) some current begins to flow into R1 as the voltage across R1 rises.  Therefore the current into C1 reduces and its dv/dt reduces, but Vc1 continues to rise and Ir1 continues to increase.

As the current in R1 increases, the voltage on C2 begins to rise.  At some point, the current into C1 has decreased enough and the current into C2 has increased enough that both capacitors' voltages rise at the same dv/dt.  
This is the second part of the VCOMP curve and this is the "linear" slope that controls the soft-start. 

In the EVM waveform, it can be seen that VCOMP starts with a 1.9V offset before the "linear" slope begins. 
There is a Pre-charge circuit in the UCC28019A that rapidly charges up the VCOMP capacitor (C15 on the EVM) to 1.9V and C17 is charging through R18.  
Once C17 has charged high enough that the pre-charge current has fallen to 30uA, then both C15 and C17 rise linearly during the soft-start interval. 

The voltage loop error amplifier is a transconductance amplifier with a gM value of -42uS; that is, -42uA/V.  It is current limited to +/-30uA during soft-start. 
As the VSENSE input voltage approaches the 5V reference, the gM amp input error voltage reduces below -30uA and decreases until PFC Vout settles into regulation.  

Regards,
Ulrich