Voltage Rail	Freq Range	Target Impedance (mOhms)
VDD_CORE (0.75V)	Low (< 1MHz)	7.0
	Mid (1 - 20 MHz)	11.7
	High (20 - 50 MHz)	23.4
VDD_CORE (0.85V)	Low (< 1MHz)	6.9
	Mid (1 - 20 MHz)	11.4
	High (20 - 50 MHz)	22.9
VDD_DDR (1.1V)	Low (< 1MHz)	104.5
	Mid (1 - 20 MHz)	174.2
	High (20 - 50 MHz)	348.3

For frequencies above 50 MHz the board decoupling caps do not play a critical role. SoC and Package decaps (if any) will be dominant beyond 50 MHz

Note: We do not include Buck output inductance in PDN simulations.

Note 1: For VDDS_DDR: we do not recommend using target impedance as the signoff..
Refer to the AM62Ax, AM62Px, AM62Dx LPDDR4 Board Design and Layout Guidelines which outlines all details of power aware SI/PI simulations that need to be run. The eye mask checks from these power aware simulations are the signoff.

We only provide impedance targets for VDD_CORE. This information can be found under processor specific section "Example:AM62Ax" (starting on page 31) in the following document: www.ti.com/.../sprac76
As noted in the document, rails not listed are not simulated by TI due to low load transients. For more information, see the device-specific EVM layout for example implementation of these rails.
Other rails like the IOs are highly dependent on external peripherals. From the SoC perspective, if you look at the MAX current ratings for the IOs, the total current (after combining all the IOs of the same voltage) is still very low < 350mA so we don't simulate this rails/No data available.
Regarding your other questions related to PET, the supply names are not expected to match with processor (Example AM62A) pin names because the power estimates in the PET are itemized by supply groups. The power supply consolidation for these supply groups match the EVM.

Power Distribution Networks: Implementation and Analysis

Sitara Processor Power Distribution Networks: Implementation and Analysis

https://www.ti.com/lit/pdf/sprac76

High Speed Board design and Signal integrity simulation

https://www.ti.com/lit/pdf/spraar7

https://www.ti.com/lit/pdf/spracn9

SYSCONFIG

DDR subsystem register configuration tool

interactive and intuitive graphical tool for enabling, configuring and generating initialization code for device pin multiplexing

Technical Documents

Collaterals and application notes

https://www.ti.com/product/AM62D-Q1#tech-docs

Technical Support

AM62D-Q1 Custom board design - FAQs

Previous E2E threads - Keywords AM62Dx, AM62D-Q1

Starting a new thread

(2) TI E2E support forums

Useful links

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1450769/faq-am62d-q1---custom-board-hardware-design---design-and-review-notes-for-reuse-of-audio-am62d--evm-schematics

https://e2e.ti.com/support/interface-group/interface/f/interface-forum/1114327/faq-what-is-the-difference-between-rmii-slave-signaling-and-rmii-master-signaling

SOC POH
https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1492996/am620-q1-the-definition-of-power-of-hour-for-automotive-grade/5736233#5736233

Notes

Always ensure you are using the latest version of the documentation.
Check the product folder regularly for the latest version.
On Ti.com, device product folder page, there is a "Notifications" button. Registering here enables automatic notification of device document changes.
If you have any queries or clarification, use E2E to find similar queries or ask a new question.

Regards,

Sreenivasa

0 Kallikuppa Sreenivasa over 1 year ago in reply to Kallikuppa Sreenivasa

TI__Guru**** 226425 points

Hi Board designers,

Inputs regarding Package shelf life

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1520415/am625-package-shelf-life

Please refer below links

https://www.ti.com/support-quality/quality-policies-procedures/product-shelf-life.html

https://www.ti.com/support-quality/faqs/product-shelf-life-faqs.html

https://www.ti.com/packaging/docs/mslsearch.tsp?OPN=AM6254BTGFHIAMCRQ1&searchSelected=devpartno&searchkey=AM625#divline

https://www.ti.com/support-quality/reliability/reliability-home.html

https://www.ti.com/lit/an/spraby1a/spraby1a.pdf

https://www.ti.com/lit/pdf/snoa550

https://www.ti.com/lit/an/slva840/slva840.pdf

/cfs-file/__key/communityserver-discussions-components-files/791/Baking-Procedure.pdf

(+) AM62P: Air Humidity for Storage and Operation - Processors forum - Processors - TI E2E support forums

I got the ask from a customer if we define the storage air humidity and the air humidity in operation for the AM62P?

I guess not, but I wanted to doublechekc with you.

Also, this is the requirements they are asking for:

Storage air humidity: 30% to 95% RH
Air humidity in operation: 30% to 95% RH

Prior to board assembly but removed from sealed packaging -> device is specified as MSL3, rated for 168hrs exposure at ≤30°C/60%RH ambient conditions without a re-bake being required before board assembly.

We have no spec for operational humidity specification, but device completed and passed relevant qualification at MSL3 moisture precondition + 1000hrs 85°C/85%RH THB (Temperature, Humidity, Bias) per standard JEDEC test conditions

Regards,

Sreenivasa

0 Kallikuppa Sreenivasa 8 months ago in reply to Kallikuppa Sreenivasa

TI__Guru**** 226425 points

Hi Board designers,

Inputs regarding weight and material content

https://www.ti.com/materialcontent/home

Regards,

Sreenivasa